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11. 发明授权

US06501312B1 Fast-locking DLL circuit and method with phased output clock 有权
标题翻译：快速锁定DLL电路和分相输出时钟的方法
公开(公告)号：US06501312B1
公开(公告)日：2002-12-31
申请号：US10122595
申请日：2002-04-15
申请人： Andy T. Nguyen
发明人： Andy T. Nguyen
IPC分类号： H03L700
CPC分类号： H03K5/00006 , H03K5/131 , H03K5/133 , H03L7/0814 , H03L7/085 , Y10S331/02
摘要： A delay-lock loop (DLL) circuit and method that accept an input clock signal and a feedback clock signal, and provide the necessary additional delay to synchronize the feedback clock signal to the input clock signal. In a first mode, the DLL circuit counts and stores a first number of delays necessary to synchronize the two signals. In some embodiments, the circuit also stores a second value representing the number of unit delays in one clock period. In a second mode, the DLL circuit uses the first stored value to add the correct number of unit delays to the input clock signal. In some embodiments, the second stored value is used to generate phased output signals.
摘要翻译：延迟锁定环路（DLL）电路和方法，接受输入时钟信号和反馈时钟信号，并提供必要的附加延迟，使反馈时钟信号与输入时钟信号同步。在第一模式中，DLL电路计数并存储同步两个信号所需的第一数目的延迟。在一些实施例中，电路还存储表示一个时钟周期内的单位延迟数量的第二值。在第二模式中，DLL电路使用第一存储值将正确数量的单位延迟添加到输入时钟信号。在一些实施例中，第二存储值用于生成定相输出信号。

12. 发明授权

US06879202B2 Multi-purpose digital frequency synthesizer circuit for a programmable logic device 有权
标题翻译：用于可编程逻辑器件的多功能数字频率合成器电路
公开(公告)号：US06879202B2
公开(公告)日：2005-04-12
申请号：US10772788
申请日：2004-02-05
申请人： Andy T. Nguyen
发明人： Andy T. Nguyen
IPC分类号： G06F1/08 , H03K23/00 , H03K19/177
CPC分类号： G06F1/08 , H03K23/00
摘要： A digital frequency synthesizer (DFS) circuit adds little additional delay on the clock path. True and complement versions of an input clock signal are provided to a first and second passgates, respectively. Under the direction of a control circuit, the passgates pass selected rising edges of the true clock signal, and selected falling edges of the complement clock signal, to an output clock terminal of the DFS circuit. When neither the true nor the complement clock signal is passed, a keeper circuit retains the value already present at the output clock terminal. In some embodiments, both passgates can be disabled and a ground or power high signal can be applied to the output terminal. Other embodiments include PLDs in which the DFS circuits are employed to allow individual clock control for each programmable logic block.
摘要翻译：数字频率合成器（DFS）电路在时钟路径上增加了一些额外的延迟。输入时钟信号的真实和补码版本分别提供给第一和第二传送门。在控制电路的方向下，通路将真实时钟信号的所选上升沿和补码时钟信号的选择的下降沿传送到DFS电路的输出时钟端。当不通过真实和补码时钟信号时，保持器电路保留已经存在于输出时钟端子上的值。在一些实施例中，两个通过的门都可被禁用，并且接地或功率高的信号可被施加到输出端。其他实施例包括其中使用DFS电路以允许每个可编程逻辑块的单独时钟控制的PLD。

13. 发明授权

US06842043B1 High-speed, low current level shifter circuits for integrated circuits having multiple power supplies 有权
标题翻译：具有多个电源的集成电路的高速，低电流电平移位器电路
公开(公告)号：US06842043B1
公开(公告)日：2005-01-11
申请号：US10386993
申请日：2003-03-11
申请人： Andy T. Nguyen , Shi-dong Zhou , Ronald L. Cline
发明人： Andy T. Nguyen , Shi-dong Zhou , Ronald L. Cline
IPC分类号： H03K3/356 , H03K19/0175
CPC分类号： H03K3/356113
摘要： Level shifter circuits that provide fast operation when changing state while generating little crowbar current. Various embodiments are presented that include some of the following features added to conventional level shifters: additional pull-down transistors coupled to each output node and gated by the associated input signal; additional pull-up transistors coupled to each output node or cross-coupled internal node and gated by the associated input signal; additional pull-up transistors coupled to the cross-coupled internal nodes and gated by the opposing output node; and additional pull-down transistors on the output nodes gated by a low voltage power high. Some of these additional transistors allow the input signal to operate more quickly on the output nodes, causing more rapid transitions on the output signals and reducing crowbar current. The pull-downs gated by the low voltage power high ensure that little or no crowbar current occurs during the power-up sequence.
摘要翻译：电平移位器电路在产生小撬棒电流时改变状态时提供快速操作。提出了各种实施例，其包括添加到传统电平移位器中的一些以下特征：耦合到每个输出节点并由相关联的输入信号选通的附加下拉晶体管; 耦合到每个输出节点或交叉耦合内部节点并由相关联的输入信号选通的附加上拉晶体管; 耦合到交叉耦合内部节点并由相对输出节点选通的附加上拉晶体管; 并且输出节点上的附加下拉晶体管由低电压功率高。这些附加晶体管中的一些允许输入信号在输出节点上更快地操作，从而导致输出信号上的更快速的转换并减少撬棒电流。通过低电压电源门控的下拉电阻确保在上电序列期间发生短路或无短路电流。

14. 发明授权

US06809555B1 Glitch-free digital phase detector circuits and methods with optional offset and lock window extension 有权
标题翻译：无毛刺的数字相位检测器电路和方法，具有可选的偏移和锁定窗口扩展
公开(公告)号：US06809555B1
公开(公告)日：2004-10-26
申请号：US10428342
申请日：2003-05-02
申请人： Andy T. Nguyen
发明人： Andy T. Nguyen
IPC分类号： H04L702
CPC分类号： H03L7/095 , H03K5/133 , H03K5/26 , H03K2005/00058 , H03L7/0814 , H03L7/091
摘要： Simple, glitch-free phase detector circuits provide add and subtract output signals indicating the phase relationship between two input clock signals. Some embodiments also provide a lock output signal having a lock window, and in some of these embodiments, the size of the lock window is programmable. An optionally delayed version of the feedback clock signal is stored a first time when the input clock signal goes high, then stored a second time after a predetermined delay. In some embodiments, the predetermined delay is programmable. When both stored values are low, the subtract output signal is active. When the first stored value is high, the add output signal is active, regardless of the state of the second stored value. When the first stored value is low and the second stored value is high, the two clocks are synchronized and the phase detector indicates a lock condition.
摘要翻译：简单的，无毛刺的相位检测器电路提供表示两个输入时钟信号之间的相位关系的加法和减法输出信号。一些实施例还提供具有锁定窗口的锁定输出信号，并且在这些实施例的一些实施例中，锁定窗口的尺寸是可编程的。当输入时钟信号变高时，第一次存储反馈时钟信号的可选延迟版本，然后在预定延迟之后第二次存储。在一些实施例中，预定延迟是可编程的。当两个存储值都为低电平时，减法输出信号有效。当第一个存储值为高时，无论第二个存储值的状态如何，加法输出信号都是有效的。当第一存储值为低并且第二存储值为高时，两个时钟同步，并且相位检测器指示锁定状态。

15. 发明授权

US06788120B1 Counter-based duty cycle correction systems and methods 有权
标题翻译：基于计数器的占空比校正系统和方法
公开(公告)号：US06788120B1
公开(公告)日：2004-09-07
申请号：US10460031
申请日：2003-06-11
申请人： Andy T. Nguyen
发明人： Andy T. Nguyen
IPC分类号： H03K3017
CPC分类号： H03K5/1565
摘要： Counter-based duty cycle correction (DCC) circuits and methods. A first counter is periodically enabled to count for one input clock period. After completion of the count, the result is divided by two and stored in a register. Thus, the value stored in the register represents a point halfway through the input clock period. Each time the input clock signal changes from a first state to a second state, an output clock generator also changes the output clock signal from the first state to the second state, and the second counter is enabled. A comparator compares the value in the second counter to the value stored in the register. When the second counter has reached the value stored in the register, the half-way point of the input clock cycle has been reached, and the output clock generator changes the output clock signal from the second state back to the first state.
摘要翻译：基于计数器的占空比校正（DCC）电路和方法。周期性地使第一个计数器对一个输入时钟周期进行计数。计数完成后，将结果除以2并存储在寄存器中。因此，存储在寄存器中的值表示输入时钟周期中途的点。每当输入时钟信号从第一状态变为第二状态时，输出时钟发生器也将输出时钟信号从第一状态改变到第二状态，并且第二计数器被使能。比较器将第二个计数器中的值与存储在寄存器中的值进行比较。当第二个计数器达到存储在寄存器中的值时，输入时钟周期的中间点已经到达，输出时钟发生器将输出时钟信号从第二个状态改变到第一个状态。

16. 发明授权

US06683481B1 Power on reset generator circuit providing hysteresis in a noisy power environment 有权
标题翻译：电源复位发电机电路在噪声电源环境中提供滞后
公开(公告)号：US06683481B1
公开(公告)日：2004-01-27
申请号：US10162236
申请日：2002-06-03
申请人： Shi-dong Zhou , Andy T. Nguyen
发明人： Shi-dong Zhou , Andy T. Nguyen
IPC分类号： H03L700
CPC分类号： H03K17/223
摘要： A power on reset (POR) generator circuit includes a modified bandgap POR circuit in series with a modified RC POR circuit. During a fast or slow power up, the circuit behaves like a traditional bandgap POR circuit, providing a POR signal when the voltage on an internal node rises higher than a reference voltage. During a fast power up, the capacitor on the bandgap output signal ensures that the POR signal remains active long enough to reset the associated circuitry. During a slow power up, the capacitor prevents glitches in the bandgap output from being passed to the POR output signal. A feedback pulldown optionally included in the bandgap portion of the circuit helps to prevent glitches from reaching the POR output signal by raising the voltage on the internal node after the reference voltage is exceeded. Various embodiments include programmable logic devices and systems that include the described circuits.
摘要翻译：上电复位（POR）发生器电路包括与改进的RC POR电路串联的改进的带隙POR电路。在快速或慢速上电期间，电路的行为像传统的带隙POR电路，当内部节点上的电压升高到高于参考电压时，提供POR信号。在快速上电期间，带隙输出信号上的电容器可确保POR信号保持足够长的时间以复位相关的电路。在缓慢上电期间，电容器可防止带隙输出中的毛刺传递到POR输出信号。可选地包括在电路的带隙部分中的反馈下拉有助于通过在超过参考电压之后通过提高内部节点上的电压来防止毛刺到达POR输出信号。各种实施例包括包括所述电路的可编程逻辑器件和系统。

17. 发明授权

US06600355B1 Clock generator circuit providing an output clock signal from phased input clock signals 有权
标题翻译：时钟发生器电路从相控输入时钟信号提供输出时钟信号
公开(公告)号：US06600355B1
公开(公告)日：2003-07-29
申请号：US10166908
申请日：2002-06-10
申请人： Andy T. Nguyen
发明人： Andy T. Nguyen
IPC分类号： G06F104
CPC分类号： G06F1/08
摘要： A clock generator circuit accepts phased input clock signals having an input clock frequency, and generates from the phased signals an output clock signal having low jitter and a clock frequency created by dividing or multiplying the input clock frequency. In exemplary embodiments having four phased input signals and a duty cycle correction feature, a clock generator circuit provides output clock frequencies of the input clock frequency divided by X/2, where X is an integer. In other embodiments not having duty cycle correction, a clock generator circuit provides output clock frequencies of the input clock frequency divided by X/4. The delay through the clock generator circuit is minimal, and is independent of the divisor. Variations include programmable divisors and multipliers and optional phase shifting.
摘要翻译：时钟发生器电路接收具有输入时钟频率的相位输入时钟信号，并且从相控信号产生具有低抖动的输出时钟信号和通过分频或乘以输入时钟频率而产生的时钟频率。在具有四个相位输入信号和占空比校正特征的示例性实施例中，时钟发生器电路将输入时钟频率的输出时钟频率除以X / 2，其中X是整数。在不具有占空比校正的其他实施例中，时钟发生器电路将输入时钟频率的输出时钟频率除以X / 4。通过时钟发生器电路的延迟很小，独立于除数。变化包括可编程除数和乘法器以及可选的相移。

18. 发明授权

US06501315B1 High-speed flip-flop operable at very low voltage levels with set and reset capability 有权
标题翻译：高速触发器可在非常低的电压电平下进行设置和复位功能
公开(公告)号：US06501315B1
公开(公告)日：2002-12-31
申请号：US10020369
申请日：2001-12-12
申请人： Andy T. Nguyen
发明人： Andy T. Nguyen
IPC分类号： H03K312
CPC分类号： H03K3/037 , H03K3/012
摘要： Flip-flops both operable at high speed and reliable at low voltage levels. A first flip-flop includes first and second cross-coupled latches. Whenever a high value is passed to one node of a latch in the flip-flop, a low value is passed to the other node of the latch. Therefore, the latches can safely ignore all high input values, which permits the flip-flops of the invention to function at very low voltages. Because writing a high value is normally slower than writing a low value, the flip-flops of the invention also function at very high clock rates, even at very low voltages. In some embodiments, pull-ups and pull-downs are coupled directly to the nodes of the latches, enabling the use of inverters instead of NAND and NOR gates to implement set and reset flip-flops, and thereby increasing the operating frequency of these flip-flops.
摘要翻译：触发器均可在高速度下可操作并且在低电压电平下可靠。第一触发器包括第一和第二交叉耦合锁存器。无论何时高触发器中的一个锁存器的一个节点传递一个高值，一个低电平值被传递到锁存器的另一个节点。因此，锁存器可以安全地忽略所有高输入值，这允许本发明的触发器在非常低的电压下起作用。由于写入较高的值通常比写入低的值慢，所以即使在非常低的电压下，本发明的触发器也以非常高的时钟速率工作。在一些实施例中，上拉和下拉直接耦合到锁存器的节点，使得能够使用反相器代替NAND和或非门来实现设置和复位触发器，从而增加这些翻转的操作频率 -flops。

19. 发明授权

US06496045B1 Programmable even-number clock divider circuit with duty cycle correction and optional phase shift 有权
标题翻译：可编程的偶数时钟分频电路，具有占空比校正和可选相移
公开(公告)号：US06496045B1
公开(公告)日：2002-12-17
申请号：US10142395
申请日：2002-05-09
申请人： Andy T. Nguyen
发明人： Andy T. Nguyen
IPC分类号： H03B1900
CPC分类号： H03K23/00 , G06F1/08 , G06F7/68
摘要： A clock divider circuit includes a state machine that receives an input clock signal and generates mutually exclusive set and reset control signals. The set and reset control signals are used to control set and reset passgates, respectively, selectively providing the input clock signal to the gate terminals of a pullup and a pulldown on the output node. The set and reset control signals are also provided to a keeper circuit that maintains a value placed on the output node.
摘要翻译：时钟分频器电路包括接收输入时钟信号并产生互斥置位和复位控制信号的状态机。设置和复位控制信号分别用于控制设置和复位通路，选择性地将输入时钟信号提供给输出节点上的上拉和下拉的门极。设置和复位控制信号也被提供给保持放置在输出节点上的值的保持器电路。

20. 发明授权

US06255880B1 One-shot DLL circuit and method 有权
标题翻译：一次性DLL电路和方法
公开(公告)号：US06255880B1
公开(公告)日：2001-07-03
申请号：US09493858
申请日：2000-01-28
申请人： Andy T. Nguyen
发明人： Andy T. Nguyen
IPC分类号： H03H1126
CPC分类号： H03K5/00006 , H03K5/131 , H03K5/133 , H03L7/0814 , H03L7/085
摘要： A delay-lock loop (DLL) circuit and method that accept an input clock signal and a feedback clock signal, and provide the necessary additional delay to synchronize the feedback clock signal to the input clock signal. Unlike previous circuits and methods, a single synchronization step is sufficient, provided that the frequency of the input clock signal is stable. A circuit according to the invention includes an input clock terminal supplying an input clock signal, and a delay line driven by the input clock signal and supplying a plurality of intermediate clock signals delayed from the input clock signal by incremental unit delays. A clock multiplexer selects from among these intermediate clock signals, under control of a multiplexer control circuit, the clock signal that provides the necessary additional delay to synchronize the feedback clock signal to the input clock signal. The output clock signal from the clock multiplexer is distributed through the clock network to provide the distributed clock signal as well as the feedback clock signal.
摘要翻译：延迟锁定环路（DLL）电路和方法，接受输入时钟信号和反馈时钟信号，并提供必要的附加延迟，使反馈时钟信号与输入时钟信号同步。与以前的电路和方法不同，单个同步步骤是足够的，只要输入时钟信号的频率是稳定的。根据本发明的电路包括提供输入时钟信号的输入时钟端子和由输入时钟信号驱动的延迟线，并通过增量单位延迟提供从输入时钟信号延迟的多个中间时钟信号。时钟多路复用器在多路复用器控制电路的控制下从这些中间时钟信号中选择时钟信号，该时钟信号提供必要的附加延迟以使反馈时钟信号与输入时钟信号同步。来自时钟多路复用器的输出时钟信号通过时钟网络分布，以提供分布式时钟信号以及反馈时钟信号。

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