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11. 发明授权

US07864625B2 Optimizing SRAM performance over extended voltage or process range using self-timed calibration of local clock generator 有权
标题翻译：使用本地时钟发生器的自定时校准优化扩展电压或过程范围内的SRAM性能
公开(公告)号：US07864625B2
公开(公告)日：2011-01-04
申请号：US12244286
申请日：2008-10-02
申请人： Gary D. Carpenter , Jente B. Kuang , Kevin J. Nowka , Liang-Teck Pang
发明人： Gary D. Carpenter , Jente B. Kuang , Kevin J. Nowka , Liang-Teck Pang
IPC分类号： G11C8/18 , G11C8/00 , G11C7/00
CPC分类号： G11C11/417 , G11C7/22 , G11C11/419
摘要： A delay circuit has a fixed delay path at a lower voltage level, a level converter, and an adjustable delay path at a higher voltage level. The fixed delay path includes an inverter chain, and the adjustable delay path includes serially-connected delay elements selectively connected to the circuit output. In an application for a local clock buffer of a static, random-access memory (SRAM), the lower voltage level is that of the local clock buffer, and the higher voltage level is that of the SRAM. These voltages may vary in response to dynamic voltage scaling, requiring re-calibration of the adjustable delay path. The adjustable delay path may be calibrated by progressively increasing the read access time of the SRAM array until a contemporaneous read operation returns the correct output, or by using a replica SRAM path to simulate variations in delay with changes in voltage supply.
摘要翻译：延迟电路具有在较低电压电平的固定延迟路径，电平转换器和在较高电压电平下的可调延迟路径。固定延迟路径包括反相器链，并且可调延迟路径包括选择性地连接到电路输出的串联连接的延迟元件。在静态随机存取存储器（SRAM）的本地时钟缓冲器的应用中，较低的电压电平是本地时钟缓冲器的电平，而较高的电压电平是SRAM的电压电平。这些电压可以响应于动态电压缩放而变化，需要重新校准可调延迟路径。可调整的延迟路径可以通过逐渐增加SRAM阵列的读取访问时间来校准，直到同时读取操作返回正确的输出，或者通过使用复制SRAM路径来模拟延迟随电压变化的变化。

12. 发明申请

US20100085823A1 Optimizing Sram Performance over Extended Voltage or Process Range Using Self-Timed Calibration of Local Clock Generator 有权
标题翻译：使用本地时钟发生器的自定时校准优化扩展电压或过程范围的串行性能
公开(公告)号：US20100085823A1
公开(公告)日：2010-04-08
申请号：US12244286
申请日：2008-10-02
申请人： Gary D. Carpenter , Jente B. Kuang , Kevin J. Nowka , Liang-Teck Pang
发明人： Gary D. Carpenter , Jente B. Kuang , Kevin J. Nowka , Liang-Teck Pang
IPC分类号： G11C7/00 , G11C8/18 , H03H11/26 , H03K3/00 , H03L5/00 , G11C8/08
CPC分类号： G11C11/417 , G11C7/22 , G11C11/419
摘要： A delay circuit has a fixed delay path at a lower voltage level, a level converter, and an adjustable delay path at a higher voltage level. The fixed delay path includes an inverter chain, and the adjustable delay path includes serially-connected delay elements selectively connected to the circuit output. In an application for a local clock buffer of a static, random-access memory (SRAM), the lower voltage level is that of the local clock buffer, and the higher voltage level is that of the SRAM. These voltages may vary in response to dynamic voltage scaling, requiring re-calibration of the adjustable delay path. The adjustable delay path may be calibrated by progressively increasing the read access time of the SRAM array until a contemporaneous read operation returns the correct output, or by using a replica SRAM path to simulate variations in delay with changes in voltage supply.
摘要翻译：延迟电路具有在较低电压电平的固定延迟路径，电平转换器和在较高电压电平下的可调延迟路径。固定延迟路径包括反相器链，并且可调延迟路径包括选择性地连接到电路输出的串联连接的延迟元件。在静态随机存取存储器（SRAM）的本地时钟缓冲器的应用中，较低的电压电平是本地时钟缓冲器的电平，而较高的电压电平是SRAM的电压电平。这些电压可以响应于动态电压缩放而变化，需要重新校准可调延迟路径。可调整的延迟路径可以通过逐渐增加SRAM阵列的读取访问时间来校准，直到同时读取操作返回正确的输出，或者通过使用复制SRAM路径来模拟延迟随电压变化的变化。

13. 发明授权

US07409305B1 Pulsed ring oscillator circuit for storage cell read timing evaluation 有权
标题翻译：脉冲环形振荡电路用于存储单元读取时序评估
公开(公告)号：US07409305B1
公开(公告)日：2008-08-05
申请号：US11682542
申请日：2007-03-06
申请人： Gary D. Carpenter , Jente B Kuang , Kevin J. Nowka , Liang-Teck Pang
发明人： Gary D. Carpenter , Jente B Kuang , Kevin J. Nowka , Liang-Teck Pang
IPC分类号： G06F3/01
CPC分类号： G01R31/31725 , G01R31/31727 , G01R31/318511 , G11C29/1201 , G11C29/50 , G11C2029/5002 , G11C2029/5006
摘要： A methor for storage cell read timing evaluation provides read strength information by using a pulsed ring oscillator. A pulse generator is coupled to a bitline to which the storage cell to be measured is connected. The storage cell thereby forms part of the ring oscillator and the read strength of the storage cell is reflected in the frequency of oscillation. A pulse regeneration circuit is included in the ring so that the storage cell read loading does not cause the oscillation to decay. Alternatively, a counter may be used to count the number of oscillations until the oscillations decay, which also yields a measure of the read strength of the storage cell. The pulse generator may have variable output current, and the current varied to determine a change in current with the storage cell enabled and disabled that produces the same oscillation frequency. The read current is the difference between currents.
摘要翻译：用于存储单元读取定时评估的方法通过使用脉冲环形振荡器来提供读取强度信息。脉冲发生器耦合到待测量的存储单元连接到的位线。因此，存储单元形成环形振荡器的一部分，并且存储单元的读取强度被反映在振荡频率中。在环中包括脉冲再生电路，使得存储单元读取负载不会导致振荡衰减。或者，可以使用计数器对振荡次数进行计数，直到振荡衰减，这也产生存储单元的读取强度的量度。脉冲发生器可以具有可变输出电流，并且电流变化以确定产生相同振荡频率的存储单元的使能和禁用的电流变化。读取电流是电流之间的差异。

14. 发明申请

US20080225615A1 PULSED RING OSCILLATOR CIRCUIT FOR STORAGE CELL READ TIMING EVALUATION 有权
标题翻译：用于存储单元的脉冲振荡器电路读取时序评估
公开(公告)号：US20080225615A1
公开(公告)日：2008-09-18
申请号：US12128526
申请日：2008-05-28
申请人： Gary D. Carpenter , Jente B. Kuang , Kevin J. Nowka , Liang-Teck Pang
发明人： Gary D. Carpenter , Jente B. Kuang , Kevin J. Nowka , Liang-Teck Pang
IPC分类号： G11C29/00
CPC分类号： G01R31/31725 , G01R31/31727 , G01R31/318511 , G11C29/1201 , G11C29/50 , G11C2029/5002 , G11C2029/5006
摘要： A pulsed ring oscillator circuit for storage cell read timing evaluation provides read strength information. A pulse generator is coupled to a bitline to which the storage cell to be measured is connected. The storage cell thereby forms part of the ring oscillator and the read strength of the storage cell is reflected in the frequency of oscillation. A pulse regeneration circuit is included in the ring so that the storage cell read loading does not cause the oscillation to decay. Alternatively, a counter may be used to count the number of oscillations until the oscillations decay, which also yields a measure of the read strength of the storage cell. The pulse generator may have variable output current, and the current varied to determine a change in current with the storage cell enabled and disabled that produces the same oscillation frequency. The read current is the difference between currents.
摘要翻译：用于存储单元读取定时评估的脉冲环形振荡器电路提供读取强度信息。脉冲发生器耦合到待测量的存储单元连接到的位线。因此，存储单元形成环形振荡器的一部分，并且存储单元的读取强度被反映在振荡频率中。在环中包括脉冲再生电路，使得存储单元读取负载不会导致振荡衰减。或者，可以使用计数器对振荡次数进行计数，直到振荡衰减，这也产生存储单元的读取强度的量度。脉冲发生器可以具有可变输出电流，并且电流变化以确定产生相同振荡频率的存储单元的使能和禁用的电流变化。读取电流是电流之间的差异。

15. 发明授权

US07620510B2 Pulsed ring oscillator circuit for storage cell read timing evaluation 有权
标题翻译：脉冲环形振荡电路用于存储单元读取时序评估
公开(公告)号：US07620510B2
公开(公告)日：2009-11-17
申请号：US12128526
申请日：2008-05-28
申请人： Gary D. Carpenter , Jente B Kuang , Kevin J. Nowka , Liang-Teck Pang
发明人： Gary D. Carpenter , Jente B Kuang , Kevin J. Nowka , Liang-Teck Pang
IPC分类号： G06F3/00
CPC分类号： G01R31/31725 , G01R31/31727 , G01R31/318511 , G11C29/1201 , G11C29/50 , G11C2029/5002 , G11C2029/5006
摘要： A pulsed ring oscillator circuit for storage cell read timing evaluation provides read strength information. A pulse generator is coupled to a bitline to which the storage cell to be measured is connected. The storage cell thereby forms part of the ring oscillator and the read strength of the storage cell is reflected in the frequency of oscillation. A pulse regeneration circuit is included in the ring so that the storage cell read loading does not cause the oscillation to decay. Alternatively, a counter may be used to count the number of oscillations until the oscillations decay, which also yields a measure of the read strength of the storage cell. The pulse generator may have variable output current, and the current varied to determine a change in current with the storage cell enabled and disabled that produces the same oscillation frequency. The read current is the difference between currents.
摘要翻译：用于存储单元读取定时评估的脉冲环形振荡器电路提供读取强度信息。脉冲发生器耦合到待测量的存储单元连接到的位线。因此，存储单元形成环形振荡器的一部分，并且存储单元的读取强度被反映在振荡频率中。在环中包括脉冲再生电路，使得存储单元读取负载不会导致振荡衰减。或者，可以使用计数器对振荡次数进行计数，直到振荡衰减，这也产生存储单元的读取强度的量度。脉冲发生器可以具有可变输出电流，并且电流变化以确定产生相同振荡频率的存储单元的使能和禁用的电流变化。读取电流是电流之间的差异。

16. 发明授权

US06483888B1 Clock divider with bypass and stop clock 失效
标题翻译：带旁路和停止时钟的时钟分频器
公开(公告)号：US06483888B1
公开(公告)日：2002-11-19
申请号：US09974987
申请日：2001-10-11
申请人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
发明人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
IPC分类号： H03K2100
CPC分类号： G06F1/08
摘要： A clock divider circuit receives a first clock signal and frequency divides the first clock signal to generate a second clock signal. The first and second clocks are inputs to multiplexer (MUX) that selects one of the clocks as the MUX output based on the state of a MUX control signal. The MUX output is combined with a latched Freeze clock signal in an AND gate to generate a clock output signal. The state of Bypass logic signal determines which clock signal is selected as the clock output signal. The Bypass logic signal is received in a latch circuit which latches the Bypass logic signal in two series latches one latch latching on the positive edge and one on the negative edge of the MUX output. The output of the second latch is latched in a third latch on when a NOR logic gate signals the first and second clock are concurrently at a logic zero assuring that the MUX output is changed only when both clocks are low. The clock output signal is gated with the latched Freeze clock signal in the AND logic gate. The clock output signal is stopped or started depending on the state of the latched Freeze clock signal. A Freeze clock signal is received in a first latch when the MUX output transitions to a logic one and is latched in a second latch when the MUX output transitions to a logic zero generating the latched Freeze clock signal. The clock output signal is stopped or started when the MUX output is a logic zero assuring that the clock output signal stops at a logic zero or starts on a next positive transition of the MUX output.
摘要翻译：时钟分频器电路接收第一时钟信号并且频率划分第一时钟信号以产生第二时钟信号。第一和第二时钟是多路复用器（MUX）的输入，其根据MUX控制信号的状态选择一个时钟作为MUX输出。 MUX输出与AND门中的锁存冻结时钟信号相结合，以产生时钟输出信号。旁路逻辑信号的状态决定了选择哪个时钟信号作为时钟输出信号。旁路逻辑信号在锁存电路中接收，锁存电路将旁路逻辑信号锁存在两个串联锁存器中，一个锁存器锁存在上升沿上，一个锁存在MUX输出的下降沿。当NOR逻辑门信号的第一和第二时钟同时处于逻辑0时，第二个锁存器的输出被锁存在第三个锁存器中，从而确保只有当两个时钟都为低电平时，MUX输出才被改变。时钟输出信号通过与逻辑门中的锁存冻结时钟信号进行门控。时钟输出信号根据锁存的冻结时钟信号的状态停止或启动。当MUX输出转变为逻辑1时，在第一锁存器中接收冻结时钟信号，并且当MUX输出转换到产生锁存的冻结时钟信号的逻辑零时，锁存在第二锁存器中。当MUX输出为逻辑0时，时钟输出信号停止或启动，确保时钟输出信号停止在逻辑0或在MUX输出的下一个正跳变时开始。

17. 发明授权

US06809602B2 Multi-mode VCO 有权
标题翻译：多模式VCO
公开(公告)号：US06809602B2
公开(公告)日：2004-10-26
申请号：US09974969
申请日：2001-10-11
申请人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
发明人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
IPC分类号： H03B2700
CPC分类号： H03K3/0315 , H03K5/133 , H03K2005/00065 , H03K2005/00195 , H03L7/0891 , H03L7/0995
摘要： A voltage controlled oscillator (VCO) is constructed using a series ring connection of an odd number K of logic inverters where K is greater than three. Each sequence of three of the logic inverters has voltage controlled feed-forward conduction circuit coupled in parallel. Each of the feed-forward circuits has the same phase between its input and output as the path it parallels. The control voltage of the feed-forward circuits operates to decrease the path delay of the logic inverters when they are conducting. Selectable inverters are connected in parallel with each logic inverter using a P and an N channel field effect transistor (FET). The N channel FET is controlled with a Mode signal and the P channel FET is controlled by a Modeb signal which is generated by inverting the Mode signal. The Mode and Modeb signals control the connection of the selectable inverters are in parallel with the logic inverters thus increasing the drive capability of the parallel combination of inverters. This reduces the delay of the circuit elements and generates a second higher frequency range over which the VCO operates. When the selectable inverters are disconnected, the VCO has a normal lower frequency range of operation.
摘要翻译：压控振荡器（VCO）使用奇数K逻辑逆变器的串联环形连接构成，其中K大于3。三个逻辑逆变器的每个序列具有并联耦合的电压控制前馈导通电路。每个前馈电路在其平行的路径上的输入和输出之间具有相同的相位。前馈电路的控制电压在导通时降低逻辑逆变器的路径延迟。可选择的逆变器使用P和N沟道场效应晶体管（FET）与每个逻辑反相器并联连接。 N沟道FET由模式信号控制，P沟道FET由通过反相模式信号产生的Modeb信号控制。 Mode和Modeb信号控制可选择的逆变器的连接与逻辑逆变器并联，从而增加了逆变器的并联组合的驱动能力。这减少了电路元件的延迟并且产生VCO工作的第二较高频率范围。当可选择的逆变器断开时，VCO具有正常较低的操作频率范围。

18. 发明授权

US06963629B2 Adaptive phase locked loop 有权
标题翻译：自适应锁相环
公开(公告)号：US06963629B2
公开(公告)日：2005-11-08
申请号：US09918809
申请日：2001-07-31
申请人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo
发明人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo
IPC分类号： H03D13/00 , H03L7/089 , H03L7/107 , H03D3/24 , H03L7/06
CPC分类号： H03L7/107 , H03D13/004 , H03L7/0898
摘要： A reference signal and a voltage controlled oscillator (VCO) output are compared for relative phase and frequency differences. A lead error signal is generated if the reference signal leads the VCO output and a lag error signal is generated if the reference signal lags the VCO output the lead and lag error may result from a combination for phase and frequency differences between the reference signal and the VCO output. A time window is used to sample the polarity of the lead and lag error signals by incrementing and decrementing a phase error signal. If the phase error signal reaches a threshold value within the time window, a Reset Delta pulse is generated and if the phase error signals does not reach the maximum delta value within the time window a Reset Total pulse is generated. A variable first gain signal is increased on each Reset Delta pulse and decreased on each Reset Total pulse and limited to a value between predetermined maximum and minimum values. The first gain signal is multiplied by a Pump current increment and added to a minimum Pump current to generate a variable Pump current. A variable second gain signal proportional to the time the reference signal leads and lags the VCO signal multiplies the Pump current. The amplified Pump current is summed with an integral of the amplified Pump current to generate a control signal. The control signal is applied to the VCO and determines the frequency of the VCO output.
摘要翻译：比较参考信号和压控振荡器（VCO）输出的相对相位和频率差。如果参考信号引导VCO输出，则产生引导误差信号，如果参考信号滞后于VCO输出引起滞后误差信号产生滞后误差，则滞后误差可能由参考信号和 VCO输出。时间窗口用于通过递增和递减相位误差信号来对引线和滞后误差信号的极性进行采样。如果相位误差信号在时间窗内达到阈值，则产生复位增量脉冲，如果相位误差信号在时间窗口内未达到最大增量值，则产生复位总脉冲。在每个复位增量脉冲上增加可变的第一增益信号，并在每个复位总脉冲上减小，并限制在预定的最大和最小值之间的值。第一个增益信号乘以泵电流增量，并加到最小泵电流以产生可变泵电流。与参考信号引导和滞后于VCO信号的时间成比例的可变第二增益信号与泵电流相乘。放大的泵电流与放大的泵电流的积分相加以产生控制信号。控制信号被施加到VCO并确定VCO输出的频率。

19. 发明授权

US06529082B1 Dual mode charge pump 失效
标题翻译：双模电荷泵
公开(公告)号：US06529082B1
公开(公告)日：2003-03-04
申请号：US09975187
申请日：2001-10-11
申请人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
发明人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
IPC分类号： H03L700
CPC分类号： H03L7/0896 , H03L7/0898 , H03L7/107
摘要： A charge pump has two charge pump nodes. The first charge pump node has a first current source (CS) with a source terminal connected to a positive supply voltage and an output terminal connected to the first charge pump node with a P channel metal oxide silicon transistor (PFET) controlled by a first control signal. The first charge pump node is also connected to a second CS with a source terminal connected to the ground supply voltage and an output terminal connected to the second CS with an NFET controlled by a second control signal. The second charge pump node has a third CS with a source terminal connected to the positive supply voltage and an output terminal connected to the second charge pump node with a PFET controlled by a third control signal. The second charge pump node is also connected to a fourth CS with a source terminal connected to the ground supply voltage and an output terminal connected to the second CS with an NFET controlled by a fourth control signal. A first bi-directional transfer gate is coupled between the output nodes of the first and third CSs and is controlled by a Mode control signal and a second bi-directional transfer gate is coupled between the output nodes of the second and fourth CSs and is also controlled by the Mode control signal. States of the control signals allow a dual mode where either a first or second current level may be delivered into or out of components coupled to the first and second charge pump nodes.
摘要翻译：电荷泵有两个电荷泵节点。第一电荷泵节点具有源极端子连接到正电源电压的第一电流源（CS）和连接到第一电荷泵节点的输出端子，其中P沟道金属氧化物硅晶体管（PFET）由第一控制信号。第一电荷泵节点还连接到具有连接到接地电源电压的源极端子的第二CS，以及通过第二控制信号控制的NFET连接到第二CS的输出端子。第二电荷泵节点具有连接到正电源电压的源极端子的第三CS和与由第三控制信号控制的PFET连接到第二电荷泵节点的输出端子。第二电荷泵节点还连接到具有连接到接地电源电压的源极端子的第四CS和连接到具有由第四控制信号控制的NFET的第二CS的输出端子。第一双向传输门耦合在第一和第三CS的输出节点之间，并且由模式控制信号控制，第二双向传输门耦合在第二和第四CS的输出节点之间，并且也是由模式控制信号控制。控制信号的状态允许双模式，其中第一或第二电流电平可以被传送到耦合到第一和第二电荷泵节点的组件中或从耦合到第一和第二电荷泵节点的组件中。

20. 发明授权

US06515530B1 Dynamically scalable low voltage clock generation system 有权
标题翻译：动态可升级的低压时钟发生系统
公开(公告)号：US06515530B1
公开(公告)日：2003-02-04
申请号：US09974985
申请日：2001-10-11
申请人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
发明人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
IPC分类号： G06F104
CPC分类号： G06F1/3237 , G06F1/08 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/128 , Y02D10/172
摘要： A phase locked loop (PLL) circuit uses a programmable frequency divider (PRFD) to generate a feedback clock from the PLL output clock. The PLL power supply voltage and a PLL reference current are generated by regulating the scalable logic supply voltage of the system in using regulator circuits. The PLL power supply voltage is regulated to a level lower than the lowest level of the scalable logic supply voltage used by the system. The PLL generates a PLL output clock whose frequency is higher than the highest frequency of operation of the system using the highest level of the scalable logic power supply voltage. The PLL output clock is divided is a second PRFD to generate a divided PLL clock. The PLL clock and a fixed auxiliary clock are selected in a glitch-free multiplexer (MUX) as the system clock for the system. The system clock frequency may be dynamically scaled by programming the divisor in the second PRFD dividing the PLL clock. If any of the scaling dynamics may affect the system clock, then the fixed frequency clock may be selected as the system clock until any transients have stabilized. The MUX may also stop the system in a known logic state. The PLL may also be optimized while the system is running.
摘要翻译：锁相环（PLL）电路使用可编程分频器（PRFD）从PLL输出时钟产生反馈时钟。通过在调节器电路中调节系统的可伸缩逻辑电源电压来产生PLL电源电压和PLL参考电流。 PLL电源电压调节到低于系统使用的可伸缩逻辑电源电压的最低电平。 PLL产生PLL输出时钟，其频率高于使用最高级别的可伸缩逻辑电源电压的系统的最高工作频率。 PLL输出时钟分为第二个PRFD，用于产生一个分频的PLL时钟。在无毛刺多路复用器（MUX）中选择PLL时钟和固定辅助时钟作为系统的系统时钟。可以通过在分频PLL时钟的第二PRFD中对除数进行编程来动态地缩放系统时钟频率。如果任何缩放动力学可能影响系统时钟，则可以选择固定频率时钟作为系统时钟，直到任何瞬变稳定为止。 MUX还可以以已知的逻辑状态停止系统。 PLL也可以在系统运行时进行优化。

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