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1. 发明授权

US06529082B1 Dual mode charge pump 失效
标题翻译：双模电荷泵
公开(公告)号：US06529082B1
公开(公告)日：2003-03-04
申请号：US09975187
申请日：2001-10-11
申请人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
发明人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
IPC分类号： H03L700
CPC分类号： H03L7/0896 , H03L7/0898 , H03L7/107
摘要： A charge pump has two charge pump nodes. The first charge pump node has a first current source (CS) with a source terminal connected to a positive supply voltage and an output terminal connected to the first charge pump node with a P channel metal oxide silicon transistor (PFET) controlled by a first control signal. The first charge pump node is also connected to a second CS with a source terminal connected to the ground supply voltage and an output terminal connected to the second CS with an NFET controlled by a second control signal. The second charge pump node has a third CS with a source terminal connected to the positive supply voltage and an output terminal connected to the second charge pump node with a PFET controlled by a third control signal. The second charge pump node is also connected to a fourth CS with a source terminal connected to the ground supply voltage and an output terminal connected to the second CS with an NFET controlled by a fourth control signal. A first bi-directional transfer gate is coupled between the output nodes of the first and third CSs and is controlled by a Mode control signal and a second bi-directional transfer gate is coupled between the output nodes of the second and fourth CSs and is also controlled by the Mode control signal. States of the control signals allow a dual mode where either a first or second current level may be delivered into or out of components coupled to the first and second charge pump nodes.
摘要翻译：电荷泵有两个电荷泵节点。第一电荷泵节点具有源极端子连接到正电源电压的第一电流源（CS）和连接到第一电荷泵节点的输出端子，其中P沟道金属氧化物硅晶体管（PFET）由第一控制信号。第一电荷泵节点还连接到具有连接到接地电源电压的源极端子的第二CS，以及通过第二控制信号控制的NFET连接到第二CS的输出端子。第二电荷泵节点具有连接到正电源电压的源极端子的第三CS和与由第三控制信号控制的PFET连接到第二电荷泵节点的输出端子。第二电荷泵节点还连接到具有连接到接地电源电压的源极端子的第四CS和连接到具有由第四控制信号控制的NFET的第二CS的输出端子。第一双向传输门耦合在第一和第三CS的输出节点之间，并且由模式控制信号控制，第二双向传输门耦合在第二和第四CS的输出节点之间，并且也是由模式控制信号控制。控制信号的状态允许双模式，其中第一或第二电流电平可以被传送到耦合到第一和第二电荷泵节点的组件中或从耦合到第一和第二电荷泵节点的组件中。

2. 发明授权

US06515530B1 Dynamically scalable low voltage clock generation system 有权
标题翻译：动态可升级的低压时钟发生系统
公开(公告)号：US06515530B1
公开(公告)日：2003-02-04
申请号：US09974985
申请日：2001-10-11
申请人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
发明人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
IPC分类号： G06F104
CPC分类号： G06F1/3237 , G06F1/08 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/128 , Y02D10/172
摘要： A phase locked loop (PLL) circuit uses a programmable frequency divider (PRFD) to generate a feedback clock from the PLL output clock. The PLL power supply voltage and a PLL reference current are generated by regulating the scalable logic supply voltage of the system in using regulator circuits. The PLL power supply voltage is regulated to a level lower than the lowest level of the scalable logic supply voltage used by the system. The PLL generates a PLL output clock whose frequency is higher than the highest frequency of operation of the system using the highest level of the scalable logic power supply voltage. The PLL output clock is divided is a second PRFD to generate a divided PLL clock. The PLL clock and a fixed auxiliary clock are selected in a glitch-free multiplexer (MUX) as the system clock for the system. The system clock frequency may be dynamically scaled by programming the divisor in the second PRFD dividing the PLL clock. If any of the scaling dynamics may affect the system clock, then the fixed frequency clock may be selected as the system clock until any transients have stabilized. The MUX may also stop the system in a known logic state. The PLL may also be optimized while the system is running.
摘要翻译：锁相环（PLL）电路使用可编程分频器（PRFD）从PLL输出时钟产生反馈时钟。通过在调节器电路中调节系统的可伸缩逻辑电源电压来产生PLL电源电压和PLL参考电流。 PLL电源电压调节到低于系统使用的可伸缩逻辑电源电压的最低电平。 PLL产生PLL输出时钟，其频率高于使用最高级别的可伸缩逻辑电源电压的系统的最高工作频率。 PLL输出时钟分为第二个PRFD，用于产生一个分频的PLL时钟。在无毛刺多路复用器（MUX）中选择PLL时钟和固定辅助时钟作为系统的系统时钟。可以通过在分频PLL时钟的第二PRFD中对除数进行编程来动态地缩放系统时钟频率。如果任何缩放动力学可能影响系统时钟，则可以选择固定频率时钟作为系统时钟，直到任何瞬变稳定为止。 MUX还可以以已知的逻辑状态停止系统。 PLL也可以在系统运行时进行优化。

3. 发明授权

US06501304B1 Glitch-less clock selector 失效
标题翻译：无毛刺时钟选择器
公开(公告)号：US06501304B1
公开(公告)日：2002-12-31
申请号：US09974990
申请日：2001-10-11
申请人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
发明人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
IPC分类号： H03K1700
CPC分类号： G06F1/08
摘要： A glitch-free clock selector selects between asynchronous clock signals. In one embodiment a select signal has two logic states corresponding to the two clock signals. A clock output signal is gated with a latched compare signal which compares a new select signal state to a stored current select signal state. A multiplexer (MUX) selects between the two clock signals in response to a select latch output signal. If the new and current select signals do not compare the clock output signal is forced to a logic zero by the output of a compare latch which latches the compare signal when the MUX output (present selected clock signal) goes to a logic zero. While the present clock signal is held low, the MUX switches to the new clock signal. The new clock signal (MUX output) latches the new select state as the current select state causing the new and current select signal to compare. The new clock signal (MUX output) latches the compare signal and again enables the clock output signal when the new clock signal transitions from a one to a zero. The clock output signal now transitions to a logic one on the next positive transition of the new clock signal guaranteeing glitch free operation. In another embodiment more than two clock signals are selected by providing a multi-bit select signal and registers instead of single bit latches. The select signal is decoded to provide the select signal for the MUX which now selects between more than two clock signals.
摘要翻译：无干扰时钟选择器在异步时钟信号之间进行选择。在一个实施例中，选择信号具有对应于两个时钟信号的两个逻辑状态。时钟输出信号通过锁存的比较信号选通，该比较信号将新的选择信号状态与存储的当前选择信号状态进行比较。多路复用器（MUX）响应于选择锁存器输出信号在两个时钟信号之间进行选择。如果新的和当前的选择信号不比较，当MUX输出（当前选定的时钟信号）变为逻辑0时，通过比较锁存器的输出将时钟输出信号强制为逻辑0，该比较锁存器锁存比较信号。当本时钟信号保持低电平时，MUX切换到新的时钟信号。新的时钟信号（MUX输出）将新的选择状态锁定为当前选择状态，导致新的和当前的选择信号进行比较。新的时钟信号（MUX输出）锁存比较信号，并且当新的时钟信号从一个转换到零时，再次启用时钟输出信号。时钟输出信号现在在保证无毛刺操作的新时钟信号的下一个正转换时转变为逻辑1。在另一个实施例中，通过提供多位选择信号来选择两个以上的时钟信号，并且寄存器而不是单个位锁存器。选择信号被解码以提供现在在两个以上的时钟信号之间选择的MUX的选择信号。

4. 发明授权

US06483888B1 Clock divider with bypass and stop clock 失效
标题翻译：带旁路和停止时钟的时钟分频器
公开(公告)号：US06483888B1
公开(公告)日：2002-11-19
申请号：US09974987
申请日：2001-10-11
申请人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
发明人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
IPC分类号： H03K2100
CPC分类号： G06F1/08
摘要： A clock divider circuit receives a first clock signal and frequency divides the first clock signal to generate a second clock signal. The first and second clocks are inputs to multiplexer (MUX) that selects one of the clocks as the MUX output based on the state of a MUX control signal. The MUX output is combined with a latched Freeze clock signal in an AND gate to generate a clock output signal. The state of Bypass logic signal determines which clock signal is selected as the clock output signal. The Bypass logic signal is received in a latch circuit which latches the Bypass logic signal in two series latches one latch latching on the positive edge and one on the negative edge of the MUX output. The output of the second latch is latched in a third latch on when a NOR logic gate signals the first and second clock are concurrently at a logic zero assuring that the MUX output is changed only when both clocks are low. The clock output signal is gated with the latched Freeze clock signal in the AND logic gate. The clock output signal is stopped or started depending on the state of the latched Freeze clock signal. A Freeze clock signal is received in a first latch when the MUX output transitions to a logic one and is latched in a second latch when the MUX output transitions to a logic zero generating the latched Freeze clock signal. The clock output signal is stopped or started when the MUX output is a logic zero assuring that the clock output signal stops at a logic zero or starts on a next positive transition of the MUX output.
摘要翻译：时钟分频器电路接收第一时钟信号并且频率划分第一时钟信号以产生第二时钟信号。第一和第二时钟是多路复用器（MUX）的输入，其根据MUX控制信号的状态选择一个时钟作为MUX输出。 MUX输出与AND门中的锁存冻结时钟信号相结合，以产生时钟输出信号。旁路逻辑信号的状态决定了选择哪个时钟信号作为时钟输出信号。旁路逻辑信号在锁存电路中接收，锁存电路将旁路逻辑信号锁存在两个串联锁存器中，一个锁存器锁存在上升沿上，一个锁存在MUX输出的下降沿。当NOR逻辑门信号的第一和第二时钟同时处于逻辑0时，第二个锁存器的输出被锁存在第三个锁存器中，从而确保只有当两个时钟都为低电平时，MUX输出才被改变。时钟输出信号通过与逻辑门中的锁存冻结时钟信号进行门控。时钟输出信号根据锁存的冻结时钟信号的状态停止或启动。当MUX输出转变为逻辑1时，在第一锁存器中接收冻结时钟信号，并且当MUX输出转换到产生锁存的冻结时钟信号的逻辑零时，锁存在第二锁存器中。当MUX输出为逻辑0时，时钟输出信号停止或启动，确保时钟输出信号停止在逻辑0或在MUX输出的下一个正跳变时开始。

5. 发明授权

US06809602B2 Multi-mode VCO 有权
标题翻译：多模式VCO
公开(公告)号：US06809602B2
公开(公告)日：2004-10-26
申请号：US09974969
申请日：2001-10-11
申请人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
发明人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo , Kevin J. Nowka
IPC分类号： H03B2700
CPC分类号： H03K3/0315 , H03K5/133 , H03K2005/00065 , H03K2005/00195 , H03L7/0891 , H03L7/0995
摘要： A voltage controlled oscillator (VCO) is constructed using a series ring connection of an odd number K of logic inverters where K is greater than three. Each sequence of three of the logic inverters has voltage controlled feed-forward conduction circuit coupled in parallel. Each of the feed-forward circuits has the same phase between its input and output as the path it parallels. The control voltage of the feed-forward circuits operates to decrease the path delay of the logic inverters when they are conducting. Selectable inverters are connected in parallel with each logic inverter using a P and an N channel field effect transistor (FET). The N channel FET is controlled with a Mode signal and the P channel FET is controlled by a Modeb signal which is generated by inverting the Mode signal. The Mode and Modeb signals control the connection of the selectable inverters are in parallel with the logic inverters thus increasing the drive capability of the parallel combination of inverters. This reduces the delay of the circuit elements and generates a second higher frequency range over which the VCO operates. When the selectable inverters are disconnected, the VCO has a normal lower frequency range of operation.
摘要翻译：压控振荡器（VCO）使用奇数K逻辑逆变器的串联环形连接构成，其中K大于3。三个逻辑逆变器的每个序列具有并联耦合的电压控制前馈导通电路。每个前馈电路在其平行的路径上的输入和输出之间具有相同的相位。前馈电路的控制电压在导通时降低逻辑逆变器的路径延迟。可选择的逆变器使用P和N沟道场效应晶体管（FET）与每个逻辑反相器并联连接。 N沟道FET由模式信号控制，P沟道FET由通过反相模式信号产生的Modeb信号控制。 Mode和Modeb信号控制可选择的逆变器的连接与逻辑逆变器并联，从而增加了逆变器的并联组合的驱动能力。这减少了电路元件的延迟并且产生VCO工作的第二较高频率范围。当可选择的逆变器断开时，VCO具有正常较低的操作频率范围。

6. 发明授权

US06963629B2 Adaptive phase locked loop 有权
标题翻译：自适应锁相环
公开(公告)号：US06963629B2
公开(公告)日：2005-11-08
申请号：US09918809
申请日：2001-07-31
申请人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo
发明人： David W. Boerstler , Gary D. Carpenter , Hung C. Ngo
IPC分类号： H03D13/00 , H03L7/089 , H03L7/107 , H03D3/24 , H03L7/06
CPC分类号： H03L7/107 , H03D13/004 , H03L7/0898
摘要： A reference signal and a voltage controlled oscillator (VCO) output are compared for relative phase and frequency differences. A lead error signal is generated if the reference signal leads the VCO output and a lag error signal is generated if the reference signal lags the VCO output the lead and lag error may result from a combination for phase and frequency differences between the reference signal and the VCO output. A time window is used to sample the polarity of the lead and lag error signals by incrementing and decrementing a phase error signal. If the phase error signal reaches a threshold value within the time window, a Reset Delta pulse is generated and if the phase error signals does not reach the maximum delta value within the time window a Reset Total pulse is generated. A variable first gain signal is increased on each Reset Delta pulse and decreased on each Reset Total pulse and limited to a value between predetermined maximum and minimum values. The first gain signal is multiplied by a Pump current increment and added to a minimum Pump current to generate a variable Pump current. A variable second gain signal proportional to the time the reference signal leads and lags the VCO signal multiplies the Pump current. The amplified Pump current is summed with an integral of the amplified Pump current to generate a control signal. The control signal is applied to the VCO and determines the frequency of the VCO output.
摘要翻译：比较参考信号和压控振荡器（VCO）输出的相对相位和频率差。如果参考信号引导VCO输出，则产生引导误差信号，如果参考信号滞后于VCO输出引起滞后误差信号产生滞后误差，则滞后误差可能由参考信号和 VCO输出。时间窗口用于通过递增和递减相位误差信号来对引线和滞后误差信号的极性进行采样。如果相位误差信号在时间窗内达到阈值，则产生复位增量脉冲，如果相位误差信号在时间窗口内未达到最大增量值，则产生复位总脉冲。在每个复位增量脉冲上增加可变的第一增益信号，并在每个复位总脉冲上减小，并限制在预定的最大和最小值之间的值。第一个增益信号乘以泵电流增量，并加到最小泵电流以产生可变泵电流。与参考信号引导和滞后于VCO信号的时间成比例的可变第二增益信号与泵电流相乘。放大的泵电流与放大的泵电流的积分相加以产生控制信号。控制信号被施加到VCO并确定VCO输出的频率。

7. 发明授权

US08285765B2 System and method for implementing simplified arithmetic logic unit processing of value-based control dependence sequences 有权
标题翻译：用于实现基于价值的控制依赖序列的简化算术逻辑单元处理的系统和方法
公开(公告)号：US08285765B2
公开(公告)日：2012-10-09
申请号：US11608907
申请日：2006-12-11
申请人： Lei Chen , Hung C. Ngo , Kevin J. Nowka
发明人： Lei Chen , Hung C. Ngo , Kevin J. Nowka
IPC分类号： G06F7/38
CPC分类号： G06F9/3885 , G06F7/575 , G06F9/30021 , G06F9/30094 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3844 , G06F9/3857
摘要： A system and method for implementing arithmetic logic unit (ALU) support for value-based control dependence sequences. According to a first embodiment of the present invention, an ALU generates a carry-out signal designating one of a first and second value as a larger value. In response to the carry-out signal, the ALU updates a storage location with a third value, which is the larger value. According to a second embodiment of the present invention, an ALU generates a carry-out signal designating one of a first and second value as a larger value. In response to the carry-out signal, the ALU updates a storage location with a third value. The third value is a fourth value, if the carry-out signal designates the first value as the larger value or the third value is a fifth value, if the carry-out signal designates the second value as the larger value.
摘要翻译：用于实现算术逻辑单元（ALU）的系统和方法支持基于值的控制依赖序列。根据本发明的第一实施例，ALU产生指定第一和第二值中的一个作为较大值的进位输出信号。响应于进位信号，ALU用第三个值更新存储位置，该值是较大的值。根据本发明的第二实施例，ALU产生指定第一和第二值中的一个作为较大值的进位信号。响应于进位信号，ALU用第三个值更新存储位置。如果进位信号指定第二值作为较大值，则第三值是第四值，如果进位信号指定第一值作为较大值或第三值是第五值。

8. 发明授权

US07129754B2 Controlled load limited switch dynamic logic circuitry 失效
标题翻译：受控负载限制开关动态逻辑电路
公开(公告)号：US07129754B2
公开(公告)日：2006-10-31
申请号：US11082805
申请日：2005-03-17
申请人： Hung C. Ngo , Jayakumaran Sivagnaname , Kevin J. Nowka , Robert K. Montoye
发明人： Hung C. Ngo , Jayakumaran Sivagnaname , Kevin J. Nowka , Robert K. Montoye
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： An LSDL circuit replaces the normal clock control of the pre-charge device for the dynamic node with a control signal that is logic zero whenever the circuit is in an active mode and is a logic one when the circuit is in standby mode. The pre-charge device holds the dynamic node at a pre-charged logic one state independent of the clock. During the logic one evaluate time of the clock, the logic tree determines the asserted state of the dynamic node. During the evaluate time, the asserted state is latched by the static LSDL section. The dynamic node then re-charges to the pre-charge state. Since the pre-charge device is not de-gated during the evaluate time, the dynamic node cannot be inadvertently discharged by noise causing an error. Likewise, since the clock does not couple to the pre-charge device a load is removed from the clock tree lowering clock power.
摘要翻译：只要电路处于活动模式，LSDL电路用动态节点的预充电装置的正常时钟控制替代逻辑零的控制信号，并且当电路处于待机模式时，逻辑为逻辑1。预充电装置将动态节点保持在与时钟无关的预充电逻辑1状态。在逻辑1期间评估时钟的时间，逻辑树确定动态节点的被断言状态。在评估时间期间，断言状态由静态LSDL部分锁存。然后动态节点重新充电到预充电状态。由于在评估时间期间预充电装置没有被去门，所以动态节点不能被无意中的噪声放电，导致错误。类似地，由于时钟不耦合到预充电装置，所以从时钟树中降低时钟功率的负载被去除。

9. 发明授权

US06975134B2 Buffer/driver circuits 失效
标题翻译：缓冲/驱动电路
公开(公告)号：US06975134B2
公开(公告)日：2005-12-13
申请号：US10821048
申请日：2004-04-08
申请人： Jente B. Kuang , Hung C. Ngo , Kevin J. Nowka
发明人： Jente B. Kuang , Hung C. Ngo , Kevin J. Nowka
IPC分类号： H03K17/16 , H03K19/00 , H03K19/003 , H03K19/017
CPC分类号： H03K19/00361 , H03K19/0016 , H03K19/01721
摘要： A buffer/driver having large output devices for driving multiple loads is configured with three parallel paths. The first logic path is made of small devices and is configured to provide the logic function of the buffer/driver without the ability to drive large loads. Second and third logic paths have the logic function of the first logic path up to the last inverting stage. The last inverting stage in each path is a single device for driving the logic states of the buffer output. The second and third logic paths have power-gating that allows the input to the pull-up and pull-down devices to float removing gate-leakage voltage stress. When the second and third logic paths are power-gated, the first logic path provides a keeper function to hold the logic state of the buffer output. The buffer/driver may be an inverter, non-inverter, or provide a multiple input logic function.
摘要翻译：具有用于驱动多个负载的大输出装置的缓冲器/驱动器配置有三个并行路径。第一个逻辑路径由小型设备组成，并配置为提供缓冲器/驱动器的逻辑功能，而无需驱动大负载。第二和第三逻辑路径具有直到上一个反相级的第一逻辑路径的逻辑功能。每个路径中的最后一个反相级是用于驱动缓冲区输出逻辑状态的单个器件。第二和第三逻辑路径具有电源门控，允许上拉和下拉器件的输入漂移去除栅极泄漏电压应力。当第二和第三逻辑路径是电源门控时，第一逻辑路径提供保持器功能以保持缓冲器输出的逻辑状态。缓冲器/驱动器可以是逆变器，非逆变器，或提供多输入逻辑功能。

10. 发明申请

US20080141046A1 PARTIAL DATA FLOW FUNCTIONAL GATING USING STRUCTURAL OR PARTIAL OPERAND VALUE INFORMATION 审中-公开
标题翻译：使用结构或部分操作价值信息的部分数据流功能评估
公开(公告)号：US20080141046A1
公开(公告)日：2008-06-12
申请号：US11567395
申请日：2006-12-06
申请人： Lei Chen , Jente B. Kuang , Brian R. Mestan , Hung C. Ngo , Kevin J. Nowka
发明人： Lei Chen , Jente B. Kuang , Brian R. Mestan , Hung C. Ngo , Kevin J. Nowka
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F9/30014 , G06F9/30105 , G06F9/30112
摘要： The present invention relates to a methodology for controlling the power consumption in a computing device based upon extended register file extension values, the method further comprising the steps of identifying an upper bit data register value and a lower bit data register value for a data register value, and inputting the upper bit data register value to a detect logic component, wherein the upper bit data register value is used to generate a data register extension value. The method further comprises the steps of utilizing the data register extension value as a power control signal serving to activate or deactivate a power supply signal to a segment of a data path, and updating the data register extension value in a subsequent data register write computational function.
摘要翻译：本发明涉及一种用于基于扩展寄存器文件扩展值来控制计算设备中的功耗的方法，所述方法还包括以下步骤：识别数据寄存器值的高位数据寄存器值和低位数据寄存器值，并将高位数据寄存器值输入到检测逻辑分量，其中高位数据寄存器值用于产生数据寄存器扩展值。该方法还包括以下步骤：利用数据寄存器扩展值作为用于激活或去激活到数据路径的段的电源信号的功率控制信号，以及在随后的数据寄存器写入计算功能中更新数据寄存器扩展值。

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