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11. 发明申请

US20060152974A1 Multi-level ONO flash program algorithm for threshold width control 有权
公开(公告)号：US20060152974A1
公开(公告)日：2006-07-13
申请号：US11034642
申请日：2005-01-13
申请人： Fatima Bathul , Darlene Hamilton , Masato Horiike
发明人： Fatima Bathul , Darlene Hamilton , Masato Horiike
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C11/5671
摘要： Methods of programming a wordline of multi-level flash memory cells (MLB) having three or more data levels per bit corresponding to three or more threshold voltages are provided. The present invention employs an interactive program algorithm that programs the bits of the wordline of memory cells in two programming phases, comprising a rough programming phase and a fine programming phase to achieve highly compact Vt distributions. In one example, cell bit-pairs that are to be programmed to the same program pattern are selected along a wordline. Groups of sample bits are chosen for each wordline to represent each possible program level. The sample bits are then programmed to determine a corresponding drain voltage at which each sample group is first programmed. This fast-bit drain voltage (Fvd) for each program level essentially provides a wordline specific program characterization of the Vt required for the remaining bits of that wordline. In the rough programming phase, the bits of core cells are then programmed from a starting point that is relative to (e.g., slightly less than or equal to) the fast-bit Vd and according to a predetermined Vd and Vg profile of programming pulses. The bits of the complementary bit-pairs are alternately programmed in this way until the Vt of the bits attains a rough. Vt level, which is offset lower than the final target threshold voltage level. Then in the second fine programming phase, the bits of the MLB cells of the wordline are further programmed with another predetermined Vd and Vg profile of programming pulses until the final target threshold voltage is achieved. The Vd and Vg profiles of programming pulses may further be tailored to accommodate the various bit-pair program pattern combinations possible. In this way, the bits of each wordline are fine-tune programmed to a data state to achieve a more precise Vt distribution, while compensating for the effects of complementary bit disturb.

12. 发明申请

US20050276120A1 Erase algorithm for multi-level bit flash memory 有权
标题翻译：多级位闪存的擦除算法
公开(公告)号：US20050276120A1
公开(公告)日：2005-12-15
申请号：US10864947
申请日：2004-06-10
申请人： Ed Hsia , Darlene Hamilton , Fatima Bathul , Masato Horiike
发明人： Ed Hsia , Darlene Hamilton , Fatima Bathul , Masato Horiike
IPC分类号： G11C11/56 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3413 , G11C11/5635 , G11C16/3404 , G11C16/3409
摘要： Methods of erasing a sector of multi-level flash memory cells (MLB) having three or more data states to a single data state are provided. The present invention employs an interactive sector erase algorithm that repeatedly erases, verifies, soft programs, and programs the sector in two or more erase phases to achieve highly compact data state distributions. In one example, the algorithm essentially erases all the MLB cells of the sector to an intermediate state and corresponding threshold voltage value using interactive erasing, soft programming and programming pulses in a first phase. Then in a second phase, the algorithm further erases all the MLB cells of the sector using additional interactive erasing and soft programming pulses until a final data state is achieved corresponding to a desired final threshold voltage value of the cells. Optionally, the algorithm may include one or more additional phases of similar operations that successively bring the memory cells of the sector to a compacted common erased state in preparation for subsequent programming operations. In one aspect of the method, the actual threshold values and/or data states chosen for these phases may be predetermined and input to the memory device by the user.
摘要翻译：提供了将具有三个或多个数据状态的多级闪存单元（MLB）的扇区擦除为单个数据状态的方法。本发明采用交互式扇区擦除算法，其在两个或多个擦除阶段中重复地擦除，验证，软程序和对扇区进行编程，以实现高度紧凑的数据状态分布。在一个示例中，该算法基本上将第一阶段中使用交互式擦除，软编程和编程脉冲的扇区的所有MLB单元擦除到中间状态和对应的阈值电压值。然后在第二阶段中，该算法使用额外的交互擦除和软编程脉冲进一步擦除扇区的所有MLB单元，直到达到对应于单元的期望的最终阈值电压值的最终数据状态。可选地，该算法可以包括一个或多个类似操作的附加阶段，其连续地将该扇区的存储器单元带到压缩的公共擦除状态，以备后续的编程操作。在该方法的一个方面中，为这些阶段选择的实际阈值和/或数据状态可以是预定的，并且由用户输入到存储器设备。

13. 发明授权

US06791880B1 Non-volatile memory read circuit with end of life simulation 有权
标题翻译：非易失性存储器读取电路，具有寿命终止模拟
公开(公告)号：US06791880B1
公开(公告)日：2004-09-14
申请号：US10431320
申请日：2003-05-06
申请人： Kazuhiro Kurihara , Binh Quang Le , Pau-Ling Chen , Darlene Hamilton , Edward Hsia
发明人： Kazuhiro Kurihara , Binh Quang Le , Pau-Ling Chen , Darlene Hamilton , Edward Hsia
IPC分类号： G11C1606
CPC分类号： G11C29/026 , G11C16/04 , G11C16/349 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C2029/5006
摘要： A non-volatile memory read circuit having adjustable current sources to provide end of life simulation. A flash memory device comprising a reference current source used to provide a reference current for comparison to the current of a memory cell being read, includes an adjustable current source in parallel with the memory cell being read, and an adjustable current source in parallel with the reference current source. The current from the memory cell, reference current source, and their parallel adjustable current sources are input to cascode circuits for conversion to voltages that are compared by a sense amplifier. The behavior of the cascode circuits and sense amplifier in response to changes in the memory cell and reference current source may be evaluated by adjusting the adjustable current sources so that the combined current at each input to the sense amplifier simulates the current of the circuit after aging or cycling.
摘要翻译：具有可调节电流源以提供寿命终止模拟的非易失性存储器读取电路。包括用于提供用于与正在读取的存储器单元的电流进行比较的参考电流的参考电流源的闪速存储器件包括与被读取的存储器单元并联的可调电流源，以及与可读电流源并联的可调电流源参考电流源。来自存储单元，参考电流源及其并联可调电流源的电流被输入到共源共栅电路，用于转换成由读出放大器比较的电压。可以通过调节可调电流源来评估级联电路和读出放大器响应于存储器单元和参考电流源的变化的行为，使得在读出放大器的每个输入处的组合电流在老化之后模拟电路的电流或骑自行车。

14. 发明授权

US06381550B1 Method of utilizing fast chip erase to screen endurance rejects 有权
标题翻译：利用快速芯片擦除来屏蔽耐力拒绝的方法
公开(公告)号：US06381550B1
公开(公告)日：2002-04-30
申请号：US09322195
申请日：1999-05-28
申请人： Edward Hsia , Phuong K. Banh , Darlene Hamilton
发明人： Edward Hsia , Phuong K. Banh , Darlene Hamilton
IPC分类号： G01N3700
CPC分类号： G11C16/3409 , G11C16/04 , G11C16/344 , G11C29/50 , G11C29/50004 , G11C29/50012
摘要： A method of utilizing Fast Chip Erase to screen endurance rejects. Multiple sectors in a device are selected and a time necessary to program all cells in the sectors is monitored and if the monitored time exceeds a first time, the device fails. A time necessary to erase all the cells without any overerased cells is monitored and if the time exceeds a second time, the device fails. A time necessary to correct overerased cells is monitored and if the time exceeds a third time, the device fails. The total time from erase until overerase correction is achieved is monitored and if the total time exceeds a fourth time, the device fails. The total time to determine erasability is monitored and if this time exceeds a fifth time, the device fails.
摘要翻译：利用快速芯片擦除来筛选耐力拒绝的方法。选择设备中的多个扇区，并监视对扇区中的所有单元进行编程所需的时间，如果监视时间超过第一次，则设备将失败。监视擦除所有没有任何过载单元的所有单元所需的时间，如果时间超过第二次，则设备将失败。监视修正过度细胞的时间，如果时间超过第三次，则设备将失败。监视从擦除到过高修正的总时间，如果总时间超过第四次，则设备发生故障。监视确定可擦除性的总时间，如果此时间超过第五次，则设备将失败。

15. 发明授权

US06277690B1 Elimination of N+ implant from flash technologies by replacement with standard medium-doped-drain (Mdd) implant 有权
标题翻译：通过替换标准中掺杂漏极（Mdd）植入物，消除闪存技术中的N +植入物
公开(公告)号：US06277690B1
公开(公告)日：2001-08-21
申请号：US09708982
申请日：2000-11-02
申请人： Darlene Hamilton , Len Toyoshiba
发明人： Darlene Hamilton , Len Toyoshiba
IPC分类号： H01L218247
CPC分类号： H01L27/112 , H01L21/823814
摘要： A method of manufacturing a semiconductor device that eliminates the N+ implant by replacement with resist spacers on n-channel gate structures and a standard Mdd implant. The N+ implant is thereby eliminated from the n-channel transistors and is replaced by an Mdd implant. The Mdd implant is simultaneously implanted into the core transistors and portions of the n-channel transistors unprotected by the resist spacers. The p-channel transistors are then implanted with a PLdd implant, the n-channel transistors are then planted with an NLdd implant, sidewall spacers are formed on all gate structures, the p-channel transistors are implanted with a P+ implant and the N+ and P+ contacts are then formed.
摘要翻译：一种制造半导体器件的方法，其通过在n沟道栅极结构和标准Mdd植入物上用抗蚀剂间隔物替换来消除N +注入。 N +注入由此从n沟道晶体管中消除，并由Mdd植入物代替。 Mdd注入同时被注入核心晶体管和n沟道晶体管的部分，不被抗蚀间隔物保护。然后用PLdd注入注入p沟道晶体管，然后将n沟道晶体管用NLdd注入种植，在所有栅极结构上形成侧壁间隔物，p沟道晶体管注入P +注入，N +和然后形成P +接触。

16. 发明授权

US08619450B2 Method for adjusting a resistive change element using a reference 有权
标题翻译：使用参考调整电阻变化元件的方法
公开(公告)号：US08619450B2
公开(公告)日：2013-12-31
申请号：US12873946
申请日：2010-09-01
申请人： Darlene Hamilton
发明人： Darlene Hamilton
IPC分类号： G11C27/00
CPC分类号： G11C5/06 , B82Y10/00 , G11C5/147 , G11C11/5614 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C13/0011 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C13/0097 , G11C13/025 , G11C2013/0076 , G11C2013/0092 , G11C2213/71 , G11C2213/79
摘要： A method of adjusting a resistive change element using a reference is disclosed. The method comprises inspecting a resistive change element to determine a first state; comparing the first state to a reference wherein said reference provides stimulus parameters corresponding to a transition from the first state to a second state; and applying the stimulus parameters to the resistive change element. A resistive change memory cell array is also disclosed.
摘要翻译：公开了一种使用参考调整电阻变化元件的方法。该方法包括检查电阻变化元件以确定第一状态; 将所述第一状态与参考进行比较，其中所述参考提供对应于从所述第一状态到第二状态的转变的刺激参数; 以及将所述刺激参数应用于所述电阻变化元件。还公开了一种电阻变化存储单元阵列。

17. 发明授权

US08559255B2 Controlling AC disturbance while programming 有权
标题翻译：在编程时控制交流干扰
公开(公告)号：US08559255B2
公开(公告)日：2013-10-15
申请号：US13569442
申请日：2012-08-08
申请人： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
发明人： Sung-Yong Chung , Zhizheng Liu , Yugi Mizuguchi , Xuguang Alan Wang , Yi He , Ming Kwan , Darlene Hamilton , Sung-Chul Lee , Guowei Wang , Nancy Leong
IPC分类号： G11C7/00
CPC分类号： G11C16/3418 , G11C16/0416 , G11C16/24 , G11C16/3427
摘要： A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.
摘要翻译：提供了一种能够在与诸如程序，读取和/或擦除之类的存储器相关联的AC操作期间最小化干扰的系统和方法。在AC操作期间，系统将存储器阵列中的所有或所需的位线子集预充电到指定的电压，以便于减少相邻单元之间的AC干扰。可以将预充电电压施加到存储器阵列中的块中的所有位线，或者对与所选择的存储器单元相关联的位线以及与块中所选择的存储单元相邻的相邻存储单元。该系统确保在选择存储器单元时，源极和漏极电压电平可以在相同或基本相同的时间被设置为期望的电平。这可以有助于在AC操作期间最小化所选择的存储器单元中的AC干扰。

18. 发明授权

US07692962B2 Reduced state quadbit 有权
标题翻译：减少状态四边形
公开(公告)号：US07692962B2
公开(公告)日：2010-04-06
申请号：US11958557
申请日：2007-12-18
申请人： Darlene Hamilton , Fatima Bathul , Ken Tanpairoj , Ou Li , David Rogers , Roger Tsao
发明人： Darlene Hamilton , Fatima Bathul , Ken Tanpairoj , Ou Li , David Rogers , Roger Tsao
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C11/5628 , Y10T29/49002
摘要： A reduced state memory device and methods of forming and programming multi-level flash memory cell element-pairs of the device, each element configured to store a blank level or two or more program levels are provided. In one embodiment, the reduced state memory device comprises a component configured to store in the memory cell element-pairs one pattern combination of a plurality of program pattern combinations comprising two blank levels, two program levels, and one blank level and one program level, the levels differing by less than a predetermined value. In one embodiment, a method of forming a memory device comprises forming at least one memory device of a multi-level flash memory array, each memory cell comprising two or more memory elements, each memory element configured to store three or more levels, and excluding one or more program pattern combinations that can be stored in the at least one memory cell.
摘要翻译：提供了一种简化状态存储器件以及形成和编程器件的多级闪存单元元件对的方法，每个元件被配置为存储空白电平或两个或更多个程序电平。在一个实施例中，缩减状态存储器件包括被配置为在存储器单元元件对中存储包括两个空白电平，两个程序电平以及一个空白电平和一个程序电平的多个程序模式组合的一个模式组合的组件，电平差别小于预定值。在一个实施例中，形成存储器件的方法包括形成多级闪速存储器阵列的至少一个存储器件，每个存储器单元包括两个或多个存储器元件，每个存储器元件被配置为存储三个或更多个电平，并且排除可存储在至少一个存储单元中的一个或多个程序模式组合。

19. 发明授权

US07656705B2 Fast single phase program algorithm for quadbit 有权
标题翻译：用于四位的快速单相程序算法
公开(公告)号：US07656705B2
公开(公告)日：2010-02-02
申请号：US11874076
申请日：2007-10-17
申请人： Darlene Hamilton , Fatima Bathul , Kulachet Tanpairoj , Ou Li
发明人： Darlene Hamilton , Fatima Bathul , Kulachet Tanpairoj , Ou Li
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0475 , G11C16/3418 , G11C2211/5621
摘要： Methods of rapidly programming a wordline of multi-level flash memory cells comprising memory cell element-pairs having three or more data levels per bit or element corresponding to three or more threshold voltages are provided. An interactive program algorithm rapidly programs the elements of the wordline of memory cells in a learn phase and a single core programming phase. In one embodiment, each wordline comprises learn element-pairs first programmed to provide learn drain voltages for programming core element-pairs along the wordline having the same program pattern of data levels. A set comprising one or more program patterns is chosen to correspond with each program level used on the wordline. The learn element-pairs are programmed to determine a learned program drain voltage for each program level. This learned program drain voltage essentially provides a wordline and program level specific program characterization of the Vd required for the remaining elements of that wordline.
摘要翻译：提供了快速编程多级闪存单元的字线的方法，其包括每位具有三个或更多个数据级或对应于三个或更多阈值电压的元件的存储单元元件对。交互式程序算法在学习阶段和单个核心编程阶段快速地对存储器单元的字线的元素进行编程。在一个实施例中，每个字线包括首先被编程为提供学习漏极电压的学习元件对，用于沿着具有相同数据级别的程序模式的字线编程核心元件对。选择包括一个或多个节目模式的集合以对应于字线上使用的每个节目级别。学习元件对被编程以确定每个程序级的学习程序漏极电压。这个学习的程序漏极电压基本上提供了字线和程序级特定程序表征该字母的剩余元件所需的Vd。

20. 发明申请

US20090154235A1 REDUCED STATE QUADBIT 有权
标题翻译：减少状态四分之一
公开(公告)号：US20090154235A1
公开(公告)日：2009-06-18
申请号：US11958557
申请日：2007-12-18
申请人： Darlene Hamilton , Fatima Bathul , Ken Tanpairoj , Ou Li , David Rogers , Roger Tsao
发明人： Darlene Hamilton , Fatima Bathul , Ken Tanpairoj , Ou Li , David Rogers , Roger Tsao
IPC分类号： G11C16/04 , H01S4/00
CPC分类号： G11C16/0475 , G11C11/5628 , Y10T29/49002
摘要： A reduced state memory device and methods of forming and programming multi-level flash memory cell element-pairs of the device, each element configured to store a blank level or two or more program levels are provided. In one embodiment, the reduced state memory device comprises a component configured to store in the memory cell element-pairs one pattern combination of a plurality of program pattern combinations comprising two blank levels, two program levels, and one blank level and one program level, the levels differing by less than a predetermined value. In one embodiment, a method of forming a memory device comprises forming at least one memory device of a multi-level flash memory array, each memory cell comprising two or more memory elements, each memory element configured to store three or more levels, and excluding one or more program pattern combinations that can be stored in the at least one memory cell.
摘要翻译：提供了一种简化状态存储器件以及形成和编程器件的多级闪存单元元件对的方法，每个元件被配置为存储空白电平或两个或更多个程序电平。在一个实施例中，缩减状态存储器件包括被配置为在存储器单元元件对中存储包括两个空白电平，两个程序电平以及一个空白电平和一个程序电平的多个程序模式组合的一个模式组合的组件，电平差别小于预定值。在一个实施例中，形成存储器件的方法包括形成多级闪速存储器阵列的至少一个存储器件，每个存储器单元包括两个或多个存储器元件，每个存储器元件被配置为存储三个或更多个电平，并且排除可存储在至少一个存储单元中的一个或多个程序模式组合。

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