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11. 发明申请

US20110016236A1 APPARATUS AND METHOD FOR PRODUCING IDENTIFIERS REGARDLESS OF MIXED DEVICE TYPE IN A SERIAL INTERCONNECTION 失效
标题翻译：用于生产符合串行互连的混合器件类型的标识符的装置和方法
公开(公告)号：US20110016236A1
公开(公告)日：2011-01-20
申请号：US12892215
申请日：2010-09-28
申请人： Hong Beom PYEON , HakJune OH , Jin-Ki KIM , Shuji SUMI
发明人： Hong Beom PYEON , HakJune OH , Jin-Ki KIM , Shuji SUMI
IPC分类号： G06F13/36
CPC分类号： G11C7/1078 , G11C7/1051 , G11C7/1063 , G11C7/109
摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR- and AND-type Flash memories) is serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) as a packet are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID accompanying the fed DT for another device and the fed ID is latched in a register of the device. In a case of no match, the ID generation is skipped and no ID is generated for another device. The DT is combined with the generated or the received ID depending on the device type match determination. The combined DT and ID is as a packet transferred to a next device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. With reference to device type provided to the interconnected devices, IDs are sequentially generated. The SI containing the DT, the ID and an ID generation command is transmitted in a packet basis to a next device. A memory controller can recognize the total number of one DT, in response to the ID received from the last device. In a case of a “don't care” DT is provided to the interconnected devices, IDs are sequentially generated and the total number of the interconnected devices is recognized, regardless of the differences in DTs of the devices.
摘要翻译：混合型的多个存储器件（例如，DRAM，SRAM，MRAM以及NAND，NOR和AND型闪存）被串联连接。每个设备都有其设备类型的设备类型信息。作为分组的串行输入（SI）中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。设备确定馈送的DT是否匹配设备的DT。在匹配的情况下，包括在设备中的计算器执行计算以生成伴随用于另一设备的馈送DT的ID，并且将馈送的ID锁存在设备的寄存器中。在不匹配的情况下，跳过ID生成，并且不会为其他设备生成ID。根据设备类型匹配确定，DT与所生成或接收的ID组合。组合的DT和ID作为传送到下一个设备的分组。在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。参考提供给互连设备的设备类型，依次生成ID。将包含DT，ID和ID生成命令的SI以分组的形式发送到下一个设备。响应于从最后一个设备接收的ID，存储器控制器可以识别一个DT的总数。在“不关心”的情况下，将DT提供给互连设备，不管设备的DT的差异如何，顺序地生成ID并且识别互连设备的总数。

12. 发明申请

US20100275056A1 APPARATUS AND METHOD OF PAGE PROGRAM OPERATION FOR MEMORY DEVICES WITH MIRROR BACK-UP OF DATA 有权
标题翻译：用于具有镜像备份数据的存储器件的页面程序操作的装置和方法
公开(公告)号：US20100275056A1
公开(公告)日：2010-10-28
申请号：US12832121
申请日：2010-07-08
申请人： Hong Beom PYEON , Jin-Ki KIM , HakJune OH
发明人： Hong Beom PYEON , Jin-Ki KIM , HakJune OH
IPC分类号： G06F12/16 , G06F11/20
CPC分类号： G06F13/4243 , G06F13/4247
摘要： An apparatus and method of page program operation is provided. When performing a page program operation with a selected memory device, a memory controller loads the data into the page buffer of one selected memory device and also into the page buffer of another selected memory device in order to store a back-up copy of the data. In the event that the data is not successfully programmed into the memory cells of the one selected memory device, then the memory controller recovers the data from the page buffer of the other memory device. Since a copy of the data is stored in the page buffer of the other memory device, the memory controller does not need to locally store the data in its data storage elements.
摘要翻译：提供了一种页面编程操作的装置和方法。当使用所选择的存储器件执行页面编程操作时，存储器控制器将数据加载到一个所选择的存储器件的页面缓冲器中，并将其加载到另一个选择的存储器件的页面缓冲器中，以便存储数据的备份副本。在数据未成功编程到所选存储器件的存储器单元中的情况下，存储器控制器从另一存储器件的页缓冲器中恢复数据。由于数据的副本存储在另一存储器件的页缓冲器中，所以存储器控制器不需要将数据本地存储在其数据存储元件中。

13. 发明申请

US20080155219A1 ID GENERATION APPARATUS AND METHOD FOR SERIALLY INTERCONNECTED DEVICES 有权
标题翻译： ID生成装置和用于串行互连装置的方法
公开(公告)号：US20080155219A1
公开(公告)日：2008-06-26
申请号：US11613563
申请日：2006-12-20
申请人： Hong Beom PYEON , HakJune OH , Jin-Ki KIM , Steven A. PRZYBYLSKI
发明人： Hong Beom PYEON , HakJune OH , Jin-Ki KIM , Steven A. PRZYBYLSKI
IPC分类号： G11C8/04
CPC分类号： G11C7/20 , G06F13/4291 , G11C7/10 , G11C7/1003 , G11C19/00 , G11C2029/4402
摘要： A plurality of memory devices (e.g., DRAMs, SRAMs, NAND Flash, NOR Flash) is serially interconnected. Each of the interconnected devices receives a device identifier (ID) and latches it as its ID. Each device includes a circuit for calculating another ID or an incremented ID to generate it. The generated ID is transferred to another device and the ID is incremented in each of the devices in the serial interconnection. The last device in the interconnection provides a last generated ID that is provided to a memory controller having a recognition circuit that recognizes the total number of the serially interconnected devices, from the provided last generated ID. The recognition circuit recognizes the total output latency of the devices in the serial interconnection.
摘要翻译：多个存储器件（例如，DRAM，SRAM，NAND闪存，NOR闪存）被串联连接。每个互连设备接收设备标识符（ID）并将其锁定为其ID。每个设备包括用于计算另一个ID或增加的ID以生成它的电路。生成的ID被传送到另一个设备，并且ID在串行互连中的每个设备中增加。互连中的最后一个设备提供最后生成的ID，其提供给具有从所提供的最后生成的ID识别串行互连设备的总数的识别电路的存储器控制器。识别电路识别串行互连中设备的总输出延迟。

14. 发明申请

US20080140916A1 SYSTEM AND METHOD OF OPERATING MEMORY DEVICES OF MIXED TYPE 有权
标题翻译：混合型记忆装置的操作系统及方法
公开(公告)号：US20080140916A1
公开(公告)日：2008-06-12
申请号：US11771241
申请日：2007-06-29
申请人： HakJune OH , Hong Beom PYEON , Jin-Ki KIM
发明人： HakJune OH , Hong Beom PYEON , Jin-Ki KIM
IPC分类号： G06F12/02
CPC分类号： G06F13/4239 , G11C16/08 , G11C16/20 , G11C2216/30
摘要： A memory system architecture is provided in which a memory controller controls memory devices in a serial interconnection configuration. The memory controller has an output port for sending memory commands and an input port for receiving memory responses for those memory commands requisitioning such responses. Each memory device includes a memory, such as, for example, NAND-type flash memory, NOR-type flash memory, random access memory and static random access memory. Each memory command is specific to the memory type of a target memory device. A data path for the memory commands and the memory responses is provided by the interconnection. A given memory command traverses memory devices in order to reach its intended memory device of the serial interconnection configuration. Upon its receipt, the intended memory device executes the given memory command and, if appropriate, sends a memory response to a next memory device. The memory response is transferred to the memory controller.
摘要翻译：提供了存储器系统结构，其中存储器控制器控制串行互连配置中的存储器件。存储器控制器具有用于发送存储器命令的输出端口和用于接收用于请求这样的响应的那些存储器命令的存储器响应的输入端口。每个存储器件包括诸如NAND型闪存，NOR型闪速存储器，随机存取存储器和静态随机存取存储器之类的存储器。每个存储器命令特定于目标存储器件的存储器类型。存储器命令和存储器响应的数据路径由互连提供。给定的存储器命令遍历存储器件以达到其串行互连配置的预期存储器件。在其接收时，预期的存储器件执行给定的存储器命令，并且如果适当的话，向下一个存储器件发送存储器响应。存储器响应被传送到存储器控制器。

15. 发明申请

US20120066442A1 SYSTEM AND METHOD OF PAGE BUFFER OPERATION FOR MEMORY DEVICES 有权
标题翻译：用于存储器件的页面缓冲器操作的系统和方法
公开(公告)号：US20120066442A1
公开(公告)日：2012-03-15
申请号：US13302413
申请日：2011-11-22
申请人： Hong Beom PYEON , Jin-Ki KIM , HakJune OH
发明人： Hong Beom PYEON , Jin-Ki KIM , HakJune OH
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0893 , G06F2212/1044 , G06F2212/2022 , G06F2212/3042 , G06F2212/7203 , G06F2212/7208 , G11C7/1039 , G11C7/106 , G11C7/1087 , G11C2207/2245
摘要： Systems and methods are provided for using page buffers of memory devices connected to a memory controller through a common bus. A page buffer of a memory device is used as a temporary cache for data which is written to the memory cells of the memory device. This can allow the memory controller to use memory devices as temporary caches so that the memory controller can free up space in its own memory.
摘要翻译：提供了系统和方法，用于使用通过公共总线连接到存储器控制器的存储器件的页缓冲器。使用存储器件的页缓冲器作为写入存储器件的存储器单元的数据的临时缓存。这可以允许内存控制器使用内存设备作为临时缓存，以便内存控制器可以释放自己内存中的空间。

16. 发明申请

US20110314206A1 APPARATUS AND METHOD FOR USING A PAGE BUFFER OF A MEMORY DEVICE AS A TEMPORARY CACHE 有权
标题翻译：使用存储器件的缓冲器作为临时缓存的装置和方法
公开(公告)号：US20110314206A1
公开(公告)日：2011-12-22
申请号：US13215789
申请日：2011-08-23
申请人： Hong Beom PYEON , Jin-Ki KIM , HakJune OH
发明人： Hong Beom PYEON , Jin-Ki KIM , HakJune OH
IPC分类号： G06F12/08
CPC分类号： G06F13/4243 , G06F13/4247
摘要： An apparatus and method are provided for using a page buffer of a memory device as a temporary cache for data. A memory controller writes data to the page buffer and later reads out the data without programming the data into the memory cells of the memory device. This allows the memory controller to use the page buffer as temporary cache so that the data does not have to occupy space within the memory controller's local data storage elements. Therefore, the memory controller can use the space in its own storage elements for other operations.
摘要翻译：提供了一种使用存储器件的页缓冲器作为数据的临时缓存的装置和方法。存储器控制器将数据写入页缓冲器，并且随后读出数据而不将数据编程到存储器件的存储单元中。这允许存储器控制器使用页面缓冲器作为临时缓存，使得数据不必占用存储器控制器的本地数据存储元件中的空间。因此，存储器控制器可以将其自己的存储元件中的空间用于其他操作。

17. 发明申请

US20110131383A1 MODULAR COMMAND STRUCTURE FOR MEMORY AND MEMORY SYSTEM 审中-公开
标题翻译：用于存储器和存储器系统的模块化命令结构
公开(公告)号：US20110131383A1
公开(公告)日：2011-06-02
申请号：US13016396
申请日：2011-01-28
申请人： Jin-Ki KIM , HakJune OH , Hong Beom PYEON
发明人： Jin-Ki KIM , HakJune OH , Hong Beom PYEON
IPC分类号： G06F12/06
CPC分类号： G11C7/1045 , G06F13/1678 , G11C7/10 , Y02D10/14
摘要： A system including a memory system and a memory controller is connected to a host system. The memory system has at least one memory device storing data. The controller translates the requests from the host system to one or more separatable commands interpretable by the at least one memory device. Each command has a modular structure including an address identifier for one of the at least one memory devices and a command identifier representing an operation to be performed by the one of the at least one memory devices. The at least one memory device and the controller are in a series-connection configuration for communication such that only one memory device is in communication with the controller for input into the memory system. The memory system can include a plurality of memory devices connected to a common bus.
摘要翻译：包括存储器系统和存储器控制器的系统连接到主机系统。存储器系统具有存储数据的至少一个存储器件。控制器将来自主机系统的请求转换成由至少一个存储设备可解释的一个或多个可分离命令。每个命令具有模块化结构，其包括用于至少一个存储器设备中的一个的地址标识符和表示由至少一个存储器设备之一执行的操作的命令标识符。至少一个存储器设备和控制器处于用于通信的串联连接配置中，使得仅一个存储器设备与控制器通信以输入到存储器系统中。存储器系统可以包括连接到公共总线的多个存储器件。

18. 发明申请

US20080205168A1 APPARATUS AND METHOD FOR USING A PAGE BUFFER OF A MEMORY DEVICE AS A TEMPORARY CACHE 失效
标题翻译：使用存储器件的缓冲器作为临时缓存的装置和方法
公开(公告)号：US20080205168A1
公开(公告)日：2008-08-28
申请号：US12029634
申请日：2008-02-12
申请人： Hong Beom PYEON , Jin-Ki KIM , HakJune OH
发明人： Hong Beom PYEON , Jin-Ki KIM , HakJune OH
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G06F13/4243 , G06F13/4247
摘要： An apparatus and method are provided for using a page buffer of a memory device as a temporary cache for data. A memory controller writes data to the page buffer and later reads out the data without programming the data into the memory cells of the memory device. This allows the memory controller to use the page buffer as temporary cache so that the data does not have to occupy space within the memory controller's local data storage elements. Therefore, the memory controller can use the space in its own storage elements for other operations.
摘要翻译：提供了一种使用存储器件的页缓冲器作为数据的临时缓存的装置和方法。存储器控制器将数据写入页缓冲器，并且随后读出数据而不将数据编程到存储器件的存储单元中。这允许存储器控制器使用页面缓冲器作为临时缓存，使得数据不必占用存储器控制器的本地数据存储元件中的空间。因此，存储器控制器可以将其自己的存储元件中的空间用于其他操作。

19. 发明申请

US20080155179A1 APPARATUS AND METHOD FOR PRODUCING IDS FOR INTERCONNECTED DEVICES OF MIXED TYPE 失效
标题翻译：用于生产混合类型的互连装置的ID的装置和方法
公开(公告)号：US20080155179A1
公开(公告)日：2008-06-26
申请号：US11622828
申请日：2007-01-12
申请人： Hong Beom PYEON , HakJune OH , Jin-Ki KIM
发明人： Hong Beom PYEON , HakJune OH , Jin-Ki KIM
IPC分类号： G06F13/00 , G06F12/02
CPC分类号： G06F13/4243 , G06F12/0676
摘要： A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs, and NAND-, NOR-, AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input are fed to one device of the serial interconnection configuration. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection.
摘要翻译：多个混合型存储器件（例如，DRAM，SRAM，MRAM和NAND-，NOR-，AND-型闪存）被串联连接。每个设备都有其设备类型的设备类型信息。串行输入中包含的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连配置的一个设备。设备确定馈送的DT是否匹配设备的DT。在匹配的情况下，包含在该设备中的计算器执行计算以生成另一设备的ID，并且将馈送的ID锁存在设备的寄存器中。生成的ID被传送到串行互连的另一个设备。在不匹配的情况下，跳过ID生成，并且不会为其他设备生成ID。在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。

20. 发明申请

US20120215974A1 MEMORY WITH OUTPUT CONTROL 有权
标题翻译：带输出控制的存储器
公开(公告)号：US20120215974A1
公开(公告)日：2012-08-23
申请号：US13463339
申请日：2012-05-03
申请人： HakJune OH , Hong Beom PYEON , Jin-Ki KIM
发明人： HakJune OH , Hong Beom PYEON , Jin-Ki KIM
IPC分类号： G06F12/02
CPC分类号： G11C11/5628 , G06F1/12 , G11C7/1021 , G11C7/1051 , G11C7/1078 , G11C11/5642 , G11C16/06 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3445 , G11C2207/107
摘要： An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
摘要翻译：公开了一种用于控制向半导体存储器中的串行数据链路接口的输出端口传送数据的装置，系统和方法。在一个示例中，闪存设备可以具有多个串行数据链路，多个存储器组和控制输入端口，其使得存储器设备能够将串行数据传送到存储器件的串行数据输出端口。在另一示例中，闪存器件可以具有单个串行数据链路，单个存储体，串行数据输入端口，用于接收输出使能信号的控制输入端口。闪存器件可以使用回波信号线以菊花链配置级联以在存储器件之间串行通信。

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