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    • 11. 发明授权
    • Method of fabricating a semiconductor device
    • 制造半导体器件的方法
    • US07507630B2
    • 2009-03-24
    • US11299907
    • 2005-12-13
    • Masanobu TsuchitaniHitoshi ShinoharaKeiko Kawamura
    • Masanobu TsuchitaniHitoshi ShinoharaKeiko Kawamura
    • H01L21/336
    • H01L29/4236H01L29/4238H01L29/66734H01L29/7811
    • A method of fabricating a semiconductor device includes: forming an insulating film on a semiconductor body to cover a termination area surrounding a cell area; forming a mask material film to cover the cell area and the insulating film; forming a resist film to cover the mask material film; patterning the resist film to have an opening serving as a gate-use resist pattern above the cell area and another opening serving as a dummy resist pattern above the insulating film; selectively etching the mask material film by use of the patterned resist film as a mask so that the insulating film is remained under the dummy resist pattern; selectively etching the semiconductor body by use of the patterned mask material film as another mask to form a trench in the cell area as corresponding to the gate-use resist pattern; and burying gate material in the trench to form the trench gate.
    • 制造半导体器件的方法包括:在半导体本体上形成绝缘膜以覆盖围绕单元区域的端接区域; 形成掩模材料膜以覆盖单元区域和绝缘膜; 形成抗蚀剂膜以覆盖掩模材料膜; 将抗蚀剂膜图案化成在单元区域之上具有用作栅极用途抗蚀剂图案的开口,并且在绝缘膜上方具有用作模拟抗蚀剂图案的另一开口; 通过使用图案化的抗蚀剂膜作为掩模来选择性地蚀刻掩模材料膜,使得绝缘膜保持在假抗蚀剂图案下方; 通过使用图案化掩模材料膜作为另一掩模来选择性地蚀刻半导体本体,以在对应于栅极使用抗蚀剂图案的单元区域中形成沟槽; 并将栅极材料埋入沟槽中以形成沟槽栅极。
    • 13. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20120061747A1
    • 2012-03-15
    • US13052917
    • 2011-03-21
    • Takeshi UCHIHARAYusuke KawaguchiKeiko KawamuraHitoshi ShinoharaYosefu Fujiki
    • Takeshi UCHIHARAYusuke KawaguchiKeiko KawamuraHitoshi ShinoharaYosefu Fujiki
    • H01L29/78
    • H01L29/7813H01L21/823487H01L27/088H01L29/0626H01L29/0696H01L29/0886H01L29/1095H01L29/4238H01L29/66734H01L29/7808
    • According to one embodiment, a semiconductor device includes a drift region of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, a gate electrode in a trench shape, a contact region of the second conductivity type, a drain electrode, and a source electrode. The drift region is selectively provided in a drain layer of the first conductivity type from a surface of the drain layer to an inside of the drain layer. The base region is selectively provided in the drift region from a surface of the drift region to an inside of the drift region. The source region is selectively provided in the base region from a surface of the base region to an inside of the base region. The gate electrode penetrates from a part of the source region through the base region adjacent to the part of the source region to reach a part of the drift region in a direction substantially parallel to a major surface of the drain layer. The contact region is selectively provided on the surface of the drift region. The contact region contains an impurity having a concentration higher than an impurity concentration of the base region. The drain electrode is connected to the drain layer. The source electrode is connected to the source region and the contact region. The contact region extends from a side of the drain layer toward the drift region and does not contact the drain layer.
    • 根据一个实施例,半导体器件包括第一导电类型的漂移区域,第二导电类型的基极区域,第一导电类型的源极区域,沟槽形状的栅电极,第二导电类型的接触区域 导电类型,漏电极和源电极。 漂移区选择性地设置在从漏层的表面到漏层的内部的第一导电类型的漏极层中。 基极区域选择性地设置在漂移区域中,从漂移区域的表面到漂移区域的内部。 源极区域从基极区域的表面到基极区域的内部选择性地设置在基极区域中。 栅极电极从源极区域的一部分穿过与源极区域相邻的基极区域,以在与漏极层的主表面基本平行的方向上到达漂移区域的一部分。 接触区选择性地设置在漂移区的表面上。 接触区域含有浓度高于碱性区域的杂质浓度的杂质。 漏电极连接到漏极层。 源电极连接到源极区域和接触区域。 接触区域从漏极层的侧面朝向漂移区域延伸,并且不接触漏极层。