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11. 发明申请

US20070110147A1 Equalizing a Signal for Transmission 有权
标题翻译：均衡信号传输
公开(公告)号：US20070110147A1
公开(公告)日：2007-05-17
申请号：US11618189
申请日：2006-12-29
申请人： Yoichi Koyanagi , Yasuo Hidaka , Weixin Gai , Hirotaka Tamura
发明人： Yoichi Koyanagi , Yasuo Hidaka , Weixin Gai , Hirotaka Tamura
IPC分类号： H03H7/30 , H04B15/00
CPC分类号： H04L25/03343
摘要： Equalizing a signal includes receiving a data sequence signal having an amplitude. An adjustment of the data sequence signal operable to equalize the data sequence signal is determined. A control signal operable to adjust the amplitude of the data sequence signal in accordance with the adjustment is generated, where the control signal has an analog form. The amplitude of the data sequence signal is adjusted using the control signal in order to equalize the data sequence signal.
摘要翻译：信号均衡包括接收具有振幅的数据序列信号。确定可操作以均衡数据序列信号的数据序列信号的调整。产生用于根据调整来调节数据序列信号的幅度的控制信号，其中控制信号具有模拟形式。使用控制信号调整数据序列信号的幅度，以便均衡数据序列信号。

12. 发明申请

US20070064781A1 Timing adjustment for data transmitting/receiving circuit 有权
标题翻译：数据发送/接收电路的定时调整
公开(公告)号：US20070064781A1
公开(公告)日：2007-03-22
申请号：US11362174
申请日：2006-02-27
申请人： Hisakatsu Yamaguchi , Kouichi Kanda , Junji Ogawa , Hirotaka Tamura
发明人： Hisakatsu Yamaguchi , Kouichi Kanda , Junji Ogawa , Hirotaka Tamura
IPC分类号： H04L5/16 , H03D3/24
CPC分类号： H04J3/0685 , G06F1/10 , H03L7/00 , H03M9/00 , H04J3/047
摘要： In order to provide a timing adjustment circuit capable of transmitting/receiving data without being affected by process unevenness and power voltage/temperature fluctuations even at a high data transfer rate, the phase of data outputted by a data transmitting unit is compared with the phase of a clock for regulating a data receiving timing of a data receiving unit, and the phase of a clock for regulating a data transmitting timing of the data transmitting unit is adjusted according to the comparison result.
摘要翻译：为了提供即使在高数据传输速率下也能够不受处理不均匀性和电源电压/温度波动的影响而发送/接收数据的定时调整电路，将由数据发送单元输出的数据的相位与根据比较结果调整用于调节数据接收单元的数据接收定时的时钟和用于调节数据发送单元的数据发送定时的时钟的相位。

13. 发明授权

US07173466B2 Timing signal generating circuit having simple configuration with low supply voltage and generating timing signals with high accuracy 有权
标题翻译：定时信号发生电路具有电源电压低的结构简单，准确度高的定时信号
公开(公告)号：US07173466B2
公开(公告)日：2007-02-06
申请号：US10347913
申请日：2003-01-22
申请人： Takaya Chiba , Hirotaka Tamura
发明人： Takaya Chiba , Hirotaka Tamura
IPC分类号： H03H11/16
CPC分类号： H03K5/13 , H04L7/0025 , H04L7/0337
摘要： A timing signal generating circuit receives multiphase input signals and generates a signal having a phase intermediate therebetween, and weighting is applied to the multi-phase input signals by using a variable impedance circuit. The timing signal generating circuit (receiver circuit) can operate with a low supply voltage, is simple in configuration, and can generate timing signals with high accuracy.
摘要翻译：定时信号发生电路接收多相输入信号并产生其间具有相位的信号，并通过使用可变阻抗电路对多相输入信号加权。定时信号发生电路（接收电路）可以以低电源电压工作，配置简单，可以高精度地产生定时信号。

14. 发明授权

US07098699B2 Buffer circuit device supplying a common mode voltage applicable to a next-stage circuit receiving output signals of the buffer circuit device 有权
标题翻译：提供适用于接收缓冲电路装置的输出信号的下一级电路的共模电压的缓冲电路装置
公开(公告)号：US07098699B2
公开(公告)日：2006-08-29
申请号：US10716533
申请日：2003-11-20
申请人： Hirotaka Tamura , Satoshi Matsubara
发明人： Hirotaka Tamura , Satoshi Matsubara
IPC分类号： H03B1/00
CPC分类号： H04L25/0276 , G11C7/1057 , G11C7/1069 , G11C7/1078 , H03K19/018528 , H04L25/028 , H04L25/0292 , H04L25/10
摘要： A buffer circuit device, which receives differential input signals and outputs differential output signals, has a buffer circuit, a common mode level generator circuit, a common mode voltage detection circuit, and a bias voltage adjusting circuit. The buffer circuit receives the input signals and outputs the output signals, and the common mode level generator circuit outputs a specific level of a common mode voltage of the output signals to be output from the buffer circuit. The common mode voltage detection circuit detects a common mode voltage of specific signals, and the bias voltage adjusting circuit adjusts a bias voltage to be supplied to the buffer circuit by comparing an output signal of the common mode level generator circuit with an output signal of the common mode voltage detection circuit.
摘要翻译：接收差分输入信号并输出差分输出信号的缓冲电路装置具有缓冲电路，共模电平发生电路，共模电压检测电路和偏置电压调整电路。缓冲电路接收输入信号并输出输出信号，共模电平发生器电路输出要从缓冲电路输出的输出信号的共模电压的特定电平。共模电压检测电路检测特定信号的共模电压，偏置电压调节电路通过将共模电平发生器电路的输出信号与输出信号进行比较来调整提供给缓冲电路的偏置电压共模电压检测电路。

15. 发明申请

US20060047494A1 Circuit analysis method and circuit analysis apparatus 审中-公开
标题翻译：电路分析方法和电路分析仪器
公开(公告)号：US20060047494A1
公开(公告)日：2006-03-02
申请号：US11042066
申请日：2005-01-26
申请人： Hirotaka Tamura , Hisakatsu Yamaguchi , Marcus Ierssel
发明人： Hirotaka Tamura , Hisakatsu Yamaguchi , Marcus Ierssel
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A step response of a clock synchronous circuit including a bandwidth restriction effect of a transmission path is extracted from circuit data on a simulation subject. A second discrete time model is generated by applying the response function to a first discrete time model generated from the circuit data. Using the second discrete time model, clock edge timing and an effective signal value of a signal input to/output from the clock synchronous circuit at this timing are calculated for simulation execution. Analogically accurate simulation of a circuit operation around a sampling edge of a clock enables precise simulation with a minimum calculation in a short time. Accordingly, the invention can provide an accurate simulation method for accurately modeling an analog operation of a signal transmission circuit that inputs and outputs a high-speed signal, to calculate in a short time.
摘要翻译：从模拟对象的电路数据中提取包括传输路径的带宽限制效果的时钟同步电路的阶跃响应。通过将响应函数应用于从电路数据生成的第一离散时间模型来生成第二离散时间模型。使用第二离散时间模型，计算时钟边沿定时和在该定时从时钟同步电路输入/输出的信号的有效信号值，以进行仿真执行。在时钟的采样边沿周围的电路操作的模拟精确仿真使得能够在短时间内进行最小计算的精确仿真。因此，本发明可以提供用于对输入和输出高速信号的信号传输电路的模拟操作进行精确建模的精确模拟方法，以在短时间内计算。

16. 发明申请

US20050226355A1 Receiver circuit comprising equalizer 有权
标题翻译：接收器电路包括均衡器
公开(公告)号：US20050226355A1
公开(公告)日：2005-10-13
申请号：US11050175
申请日：2005-02-04
申请人： Masaya Kibune , Hirotaka Tamura
发明人： Masaya Kibune , Hirotaka Tamura
IPC分类号： H04L25/03 , H04B3/06 , H04B3/18 , H04L1/00
CPC分类号： H04L25/0328 , H04L25/03038
摘要： A receiver circuit has an equalizer that equalizes a received signal propagating through a transmission medium; a data detection circuit that detects an analog output signal of the equalizer at a data sample timing and outputs a digital signal; an intersymbol interference detection circuit that detects an intersymbol interference level from the analog output signal of the equalizer at the data sample timing and from the digital signal of the data detection circuit; and an equalization characteristic control unit that controls the characteristic of the equalizer to minimize the detected intersymbol interference level. The receiver circuit further has a data sample timing control unit in which the data sample timing is controlled to a sample timing at which the difference between the amplitude of the analog output waveform of the equalizer with respect to an impulse and the amplitude of an ideal impulse response waveform is minimal.
摘要翻译：接收机电路具有均衡器，其均衡通过传输介质传播的接收信号; 数据检测电路，在数据采样定时检测均衡器的模拟输出信号，并输出数字信号; 符号间干扰检测电路，在数据采样定时和数据检测电路的数字信号中，从均衡器的模拟输出信号中检测出符号间干扰电平; 以及均衡特性控制单元，其控制均衡器的特性以使检测到的符号间干扰电平最小化。接收器电路还具有数据采样定时控制单元，其中数据采样定时被控制到采样定时，在该采样定时处，均衡器的模拟输出波形的相对于脉冲的幅度与理想脉冲的振幅之差响应波形最小。

17. 发明授权

US06900676B1 Clock generator for generating accurate and low-jitter clock 有权
标题翻译：时钟发生器，用于产生精确和低抖动时钟
公开(公告)号：US06900676B1
公开(公告)日：2005-05-31
申请号：US10625879
申请日：2003-07-24
申请人： Hirotaka Tamura
发明人： Hirotaka Tamura
IPC分类号： G06F1/04 , G06F1/08 , H03L7/00 , H03L7/07 , H03L7/081 , H03L7/087 , H03L7/089 , H03L7/091 , H03L7/093 , H04L7/033 , H03L7/06
CPC分类号： H03L7/087 , H03L7/07 , H03L7/0812 , H03L7/0891 , H03L7/091 , H03L7/093 , H04L7/033
摘要： A clock generator has a clock generating circuit, a phase difference detection circuit, and a control signal generating circuit. The clock generating circuit has a function for varying a clock phase in accordance with a control signal, the phase difference detection circuit compars the clock phase output from the clock generating circuit with a phase of a reference waveform, and detecting a phase difference therebetween, and the control signal generating circuit generates a control signal for controlling the clock phase of the clock generating circuit, based on phase difference information obtained from the phase difference detection circuit. The phase difference detection circuit has a plurality of phase detection units, at least one of the plurality of phase detection units carries out a direct phase detection in which a phase of the clock is directly compared with the phase of the reference waveform, and at least the other one of the plurality of phase detection units carries out an indirect phase detection using a phase-synchronized waveform generating circuit generating a waveform synchronized in phase with the reference waveform or an output of the clock generating circuit and a phase information extracting circuit extracting phase information from the phase-synchronized waveform.
摘要翻译：时钟发生器具有时钟发生电路，相位差检测电路和控制信号发生电路。时钟产生电路具有根据控制信号改变时钟相位的功能，相位差检测电路以时钟发生电路输出的时钟相位为参考波形的相位，并检测其间的相位差;以及控制信号生成电路根据从相位差检测电路得到的相位差信息，生成用于控制时钟发生电路的时钟相位的控制信号。所述相位差检测电路具有多个相位检测单元，所述多个相位检测单元中的至少一个进行直接相位检测，其中所述时钟的相位与所述参考波形的相位直接比较，至少多个相位检测单元中的另一个相位检测单元使用相位同步波形发生电路进行间接相位检测，该相位同步波形发生电路产生与参考波形同步的波形或时钟发生电路的输出，以及相位信息提取电路提取相位来自相位同步波形的信息。

18. 发明授权

US06287153B1 Cable connector with improved engagement mechanism 有权
标题翻译：电缆连接器，具有改进的接合机构
公开(公告)号：US06287153B1
公开(公告)日：2001-09-11
申请号：US09561527
申请日：2000-04-28
申请人： Motoaki Asaoka , Hirotaka Tamura
发明人： Motoaki Asaoka , Hirotaka Tamura
IPC分类号： H01R1304
CPC分类号： H01R13/04 , H01R13/424
摘要： A cable connector which includes an engagement mechanism which prevents the disengagement between the terminal and the housing irrespective of a direction of force applied to the cable. Specifically, the cable connector includes a housing with a terminal mounted therein. An engagement opening portion of the terminal engages an engagement convex portion of a lance provided in the housing. The lance is sandwiched and protected between a support block and a backup wall of the housing. Furthermore, a pair of fitting insert pieces are provided on both sides of a base portion of the terminal and these are configured so as to insert into corresponding fitting insert groove portions provided in the housing.
摘要翻译：一种电缆连接器，其包括接合机构，其防止端子和壳体之间的分离，而不管施加到电缆的力的方向如何。具体地，电缆连接器包括其中安装有端子的壳体。端子的接合开口部分接合设置在壳体中的喷枪的接合凸部。喷枪被夹持并保护在支撑块和壳体的支撑壁之间。此外，在端子的基部的两侧设置有一对装配插入件，并且这些插入件被构造成插入到设置在壳体中的相应的装配插入槽部中。

19. 发明授权

US06247138B1 Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system 失效
公开(公告)号：US06247138B1
公开(公告)日：2001-06-12
申请号：US09093056
申请日：1998-06-08
申请人： Hirotaka Tamura , Hisakatsu Araki , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
发明人： Hirotaka Tamura , Hisakatsu Araki , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
IPC分类号： G06F104
CPC分类号： H04L7/0337 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4076 , H03K2005/00052 , H04L7/0025
摘要： A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.

20. 发明授权

US08065553B2 Phase interpolator for a timing signal generating circuit 有权
标题翻译：用于定时信号发生电路的相位内插器
公开(公告)号：US08065553B2
公开(公告)日：2011-11-22
申请号：US12358861
申请日：2009-01-23
申请人： Hirotaka Tamura , Hisakatsu Yamaguchi , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
发明人： Hirotaka Tamura , Hisakatsu Yamaguchi , Shigetoshi Wakayama , Kohtaroh Gotoh , Junji Ogawa
IPC分类号： G06F1/04 , G06F1/12 , G06F1/24 , H03J7/04
CPC分类号： H04L7/0337 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/4076 , H03K2005/00052 , H04L7/0025
摘要： A semiconductor integrated circuit device has a command decoder for issuing a control command in accordance with a supplied control signal, a DRAM core, and a timing adjusting circuit for supplying the control command, set active for a predetermined period, as a DRAM control signal to the DRAM core. The timing adjusting circuit generates n different clocks that are respectively shifted in phase with respect to a supplied reference clock, and generates the DRAM control signal by setting the control command active in a prescribed operation cycle for only a period starting at a first predetermined clock pulse of a first clock of the n clocks and ending at a second predetermined clock pulse of a second clock of the n clocks. In this way, timing design with relatively high accuracy of adjustment can be done in a short period.
摘要翻译：半导体集成电路器件具有命令解码器，用于根据所提供的控制信号，DRAM内核和定时调整电路发出控制命令，该控制命令用于将预定周期内设定的控制命令设置为DRAM控制信号， DRAM内核。定时调整电路产生相对于所提供的参考时钟相位移相同步的n个不同的时钟，并且通过仅在从第一预定时钟脉冲开始的周期内将规定的操作周期中的控制命令设置为有效来产生DRAM控制信号的n个时钟的第一时钟并且以n个时钟的第二时钟的第二预定时钟脉冲结束。以这种方式，可以在短时间内进行相对较高的调整精度的定时设计。

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