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11. 发明授权

US5724297A Semiconductor integrated circuit device and method of activating the same 失效
公开(公告)号：US5724297A
公开(公告)日：1998-03-03
申请号：US762883
申请日：1996-12-12
申请人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
发明人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
IPC分类号： G11C11/407 , G11C5/14 , G11C11/4074 , H03K19/00 , H03K17/16
CPC分类号： G11C5/14 , G11C11/4074 , G11C5/147 , H03K19/0016
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

12. 发明授权

US06473358B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06473358B2
公开(公告)日：2002-10-29
申请号：US10097564
申请日：2002-03-15
申请人： Hiromasa Noda , Youji Idei , Osamu Nagashima , Tetsuo Ado
发明人： Hiromasa Noda , Youji Idei , Osamu Nagashima , Tetsuo Ado
IPC分类号： G11C800
CPC分类号： G11C29/84 , G11C7/1027 , G11C8/04 , G11C11/4087
摘要： A semiconductor memory device has a column address decoder which includes first and second pre-decoders corresponding to high-order and low-order addresses, respectively, a shift register for using the output signal of the second pre-decoder as an initial value, and an output circuit for selecting either the output signal of the second pre-decoder or the output signal of the shift register in accordance with an action mode. The select signal is formed by the output signal of the first pre-decoder and the output signal through the output circuit. The shift register includes a first shift register for an even address and a second shift register for an odd address and forms two sets of continuous select signals of the bit lines, as composed of a sequential action and an interleave action, on the basis of the initial value by combining its up and down shifting actions.
摘要翻译：一种半导体存储器件具有列地址解码器，它包括分别对应于高阶和低阶地址的第一和第二预解码器，用于使用第二预解码器的输出信号作为初始值的移位寄存器，以及输出电路，用于根据动作模式选择第二预解码器的输出信号或移位寄存器的输出信号。选择信号由第一预解码器的输出信号和通过输出电路的输出信号形成。移位寄存器包括用于偶数地址的第一移位寄存器和奇数地址的第二移位寄存器，并且基于顺序动作和交错动作形成位线的两组连续选择信号通过组合其上下移动动作的初始值。

13. 发明授权

US06275440B1 Semiconductor integrated circuit device and method of activating the same 有权
公开(公告)号：US06275440B1
公开(公告)日：2001-08-14
申请号：US09729273
申请日：2000-12-05
申请人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
发明人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
IPC分类号： G11C700
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon reaching its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

14. 发明授权

US5955905A Signal generator with synchronous mirror delay circuit 失效
标题翻译：具有同步镜延迟电路的信号发生器
公开(公告)号：US5955905A
公开(公告)日：1999-09-21
申请号：US967612
申请日：1997-11-10
申请人： Youji Idei , Masakazu Aoki , Hiromasa Noda
发明人： Youji Idei , Masakazu Aoki , Hiromasa Noda
IPC分类号： G11C11/407 , G06F1/06 , G06F1/10 , G11C7/10 , H01L27/10 , H03K5/135 , H04L7/033 , H03L7/00
CPC分类号： H03K5/135 , G11C7/1072 , H04L7/0331
摘要： A clock signal received from an external terminal through an input buffer is delayed by delay circuits. A counter circuit is started up in accordance with the clock signal transmitted through the delay circuits to count an oscillation pulse having a frequency which is sufficiently high with respect to that of the clock signal. Further, the counter circuit reversely counts the count in response to a clock signal delayed by one cycle, which has passed through the input buffer. When its count once again reaches the counter value at the start of counting, the counter circuit generates an output timing signal and transmits it to an internal circuit through a clock driver. A delay time outputted from the delay circuits is set to a delay time corresponding to the sum of a delay time of the input buffer and a delay time of the clock driver.
摘要翻译：通过输入缓冲器从外部端子接收的时钟信号被延迟电路延迟。根据通过延迟电路发送的时钟信号启动计数器电路，以对相对于时钟信号的频率足够高的频率的振荡脉冲进行计数。此外，计数器电路响应延迟了一个周期的时钟信号来反向计数，该周期已经通过输入缓冲器。当其计数在计数开始时再次达到计数值时，计数器电路产生输出定时信号，并通过时钟驱动器将其发送到内部电路。从延迟电路输出的延迟时间被设定为对应于输入缓冲器的延迟时间和时钟驱动器的延迟时间之和的延迟时间。

15. 发明授权

US06498762B2 Semiconductor integrated circuit device and method of activating the same 有权
公开(公告)号：US06498762B2
公开(公告)日：2002-12-24
申请号：US10040452
申请日：2002-01-09
申请人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
发明人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
IPC分类号： G11C700
CPC分类号： G11C5/14 , G11C5/147 , G11C11/4074 , H03K19/0016
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

16. 发明授权

US06240035B1 Semiconductor integrated circuit device and method of activating the same 有权
公开(公告)号：US06240035B1
公开(公告)日：2001-05-29
申请号：US09302437
申请日：1999-04-30
申请人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
发明人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
IPC分类号： G11C700
CPC分类号： G11C5/14 , G11C5/147 , G11C11/4074 , H03K19/0016
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon reaching its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

17. 发明授权

US6128248A Semiconductor memory device including a clocking circuit for controlling the read circuit operation 有权
标题翻译：半导体存储器件包括用于控制读取电路操作的时钟电路
公开(公告)号：US6128248A
公开(公告)日：2000-10-03
申请号：US345738
申请日：1999-07-01
申请人： Youji Idei , Masakazu Aoki , Hiromasa Noda
发明人： Youji Idei , Masakazu Aoki , Hiromasa Noda
IPC分类号： G11C11/407 , G06F1/06 , G06F1/10 , G11C7/10 , H01L27/10 , H03K5/135 , H04L7/033 , G11C8/00
CPC分类号： H03K5/135 , G11C7/1072 , H04L7/0331
摘要： A semiconductor memory device is provided which includes a memory cell array, a read circuit which reads data from said memory cell array, and an external terminal which receives an external clock signal. A first input circuit receives the external clock signal and outputs a first internal clock signal delayed from the external clock signal. A second input circuit receives the first internal clock signal and outputs a second internal clock signal delayed from the first internal clock signal. The memory device also includes a circuit which counts a clock signal having a frequency higher than that of the external clock signal and a circuit which starts the counting in response to the second internal clock signal, reverses the direction of said counting in response to the first internal clock signal and detects when a count of said counting circuit again reaches the count at the start of said counting, thereby outputting a timing signal therefrom. A clock output circuit is provided which outputs a third internal clock signal for controlling the operation of said read circuit based on the timing signal.
摘要翻译：提供一种半导体存储器件，其包括存储单元阵列，从所述存储单元阵列读取数据的读取电路和接收外部时钟信号的外部端子。第一输入电路接收外部时钟信号并输出从外部时钟信号延迟的第一内部时钟信号。第二输入电路接收第一内部时钟信号并输出从第一内部时钟信号延迟的第二内部时钟信号。存储装置还包括对具有高于外部时钟信号的频率的时钟信号进行计数的电路和响应于第二内部时钟信号开始计数的电路，响应于第一内部时钟信号反转所述计数的方向内部时钟信号，并且检测在所述计数开始时所述计数电路的计数再次达到计数，从而从其输出定时信号。提供了一种时钟输出电路，其输出用于基于定时信号控制所述读取电路的操作的第三内部时钟信号。

18. 发明授权

US06473354B2 Semiconductor integrated circuit device and method of activating the same 有权
公开(公告)号：US06473354B2
公开(公告)日：2002-10-29
申请号：US10040492
申请日：2002-01-09
申请人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
发明人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
IPC分类号： G11C700
CPC分类号： G11C5/14 , G11C5/147 , G11C11/4074 , H03K19/0016
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

19. 发明授权

US06424586B1 Semiconductor integrated circuit device and method of activating same 有权
标题翻译：半导体集成电路器件及其激活方法
公开(公告)号：US06424586B1
公开(公告)日：2002-07-23
申请号：US10040435
申请日：2002-01-09
申请人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
发明人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
IPC分类号： G11C700
CPC分类号： G11C5/14 , G11C5/147 , G11C11/4074 , H03K19/0016
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
摘要翻译：动态RAM被分成响应于从外部端子提供的输入信号的输入电路块，包括操作开始信号，响应于从输入电路块输入的信号而被激活的内部电路块，以及输出电路块用于将从内部电路块输出的信号输出到外部端子。在用于施加从外部端子提供的工作电压的电力线和用于内部电路块中的第一电路部分的内部电力线之间的并行形式提供多个开关MOSFET，其不需要在其非正常状态下的存储操作操作状态。此外，响应于通过延迟通过输入电路块提供的启动信号而产生的控制信号，开关MOSFET逐步导通，以便执行每个工作电压的供应。

20. 发明授权

US5629898A Dynamic memory device, a memory module, and a method of refreshing a dynamic memory device 失效
标题翻译：动态存储器件，存储器模块和刷新动态存储器件的方法
公开(公告)号：US5629898A
公开(公告)日：1997-05-13
申请号：US607977
申请日：1996-02-29
申请人： Youji Idei , Katsuhiro Shimohigashi , Masakazu Aoki , Hiromasa Noda , Katsuyuki Sato , Hidetoshi Iwai , Makoto Saeki , Jun Murata , Yoshitaka Tadaki , Toshihiro Sekiguchi , Osamu Tsuchiya
发明人： Youji Idei , Katsuhiro Shimohigashi , Masakazu Aoki , Hiromasa Noda , Katsuyuki Sato , Hidetoshi Iwai , Makoto Saeki , Jun Murata , Yoshitaka Tadaki , Toshihiro Sekiguchi , Osamu Tsuchiya
IPC分类号： G11C11/406 , G11C11/407 , G11C7/00
CPC分类号： G11C11/406 , G11C2211/4016 , G11C2211/4061
摘要： A period pulse corresponding to the shortest information retention time of those of dynamic memory cells is counted to form a refresh address to be assigned to a plurality of word lines. A carry signal outputted from the refresh address counter is divided by a divider. For each of said plurality of word lines assigned with the refresh address, one of a short period corresponding to an output pulse of a timer or a long period corresponding to the divided pulse from the divider is stored in a storage circuit as refresh time setting information. A memory cell refresh operation to be performed by the refresh address is made valid or invalid for each word line according to the refresh time setting information stored in the storage circuit and the refresh time setting information itself is made invalid by the output pulse of the divider.
摘要翻译：对与动态存储单元的最短信息保持时间对应的周期脉冲进行计数，以形成分配给多个字线的刷新地址。从刷新地址计数器输出的进位信号由分频器分频。对于分配有刷新地址的所述多个字线中的每一个，对应于定时器的输出脉冲的短周期中的一个或与来自分频器的分频脉冲相对应的长周期中的一个作为刷新时间设置信息被存储在存储电路中。根据存储在存储电路中的刷新时间设定信息，由刷新地址执行的存储器单元刷新动作对每个字线进行有效或无效，并且刷新时间设定信息本身被分频器的输出脉冲无效。

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