专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US08432750B2 Non-volatile memory systems and methods including page read and/or configuration features 有权
标题翻译：非易失性存储器系统和方法，包括页面读取和/或配置特征
公开(公告)号：US08432750B2
公开(公告)日：2013-04-30
申请号：US12961458
申请日：2010-12-06
申请人： Hieu Van Tran , Sakhawat M. Khan
发明人： Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
摘要翻译：为数字多位非易失性存储器集成系统提供高速电压模式感测。一个实施例具有本地源跟随器阶段，之后是高速公共源级。另一个实施例具有本地源极跟随器级，之后是高速源极跟随器级。另一个实施例具有公共源级，之后是源跟随器。使用自动归零方案。使用电容感测方案。描述多级并行操作。

12. 发明申请

US20110110170A1 Non-volatile memory systems and methods including page read and/or configuration features 有权
标题翻译：非易失性存储器系统和方法，包括页面读取和/或配置特征
公开(公告)号：US20110110170A1
公开(公告)日：2011-05-12
申请号：US12961458
申请日：2010-12-06
申请人： Hieu Van Tran , Sakhawat M. Khan
发明人： Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
摘要翻译：为数字多位非易失性存储器集成系统提供高速电压模式感测。一个实施例具有本地源跟随器阶段，之后是高速公共源级。另一个实施例具有本地源极跟随器级，之后是高速源极跟随器级。另一个实施例具有公共源级，之后是源跟随器。使用自动归零方案。使用电容感测方案。描述多级并行操作。

13. 发明授权

US07196927B2 Wide dynamic range and high speed voltage mode sensing for a multilevel digital non-volatile memory 有权
公开(公告)号：US07196927B2
公开(公告)日：2007-03-27
申请号：US10764381
申请日：2004-01-22
申请人： Hieu Van Tran , Sakhawat M. Khan
发明人： Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.

14. 发明授权

US07848159B2 Non-volatile memory systems and methods including page read and/or configuration features 有权
标题翻译：非易失性存储器系统和方法，包括页面读取和/或配置特征
公开(公告)号：US07848159B2
公开(公告)日：2010-12-07
申请号：US12275191
申请日：2008-11-20
申请人： Hieu Van Tran , Sakhawat M. Khan
发明人： Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
摘要翻译：为数字多位非易失性存储器集成系统提供高速电压模式感测。一个实施例具有本地源跟随器阶段，之后是高速公共源级。另一个实施例具有本地源极跟随器级，之后是高速源极跟随器级。另一个实施例具有公共源级，之后是源跟随器。使用自动归零方案。使用电容感测方案。描述多级并行操作。

15. 发明授权

US07035151B2 Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system 有权
公开(公告)号：US07035151B2
公开(公告)日：2006-04-25
申请号：US10868614
申请日：2004-06-14
申请人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
发明人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
IPC分类号： G11C8/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.

16. 发明授权

US06504754B2 Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system 有权
公开(公告)号：US06504754B2
公开(公告)日：2003-01-07
申请号：US09898582
申请日：2001-07-02
申请人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
发明人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.

17. 发明授权

US06396742B1 Testing of multilevel semiconductor memory 有权
标题翻译：多层半导体存储器测试
公开(公告)号：US06396742B1
公开(公告)日：2002-05-28
申请号：US09627917
申请日：2000-07-28
申请人： George J. Korsh , Sakhawat M. Khan , Hieu Van Tran
发明人： George J. Korsh , Sakhawat M. Khan , Hieu Van Tran
IPC分类号： G11C1604
CPC分类号： G11C29/028 , G11C11/56 , G11C11/5621 , G11C29/50 , G11C2029/5004
摘要： In accordance with an embodiment of the present invention, a method for testing a multilevel memory includes: performing an erase operation to place a plurality of memory cells in an erased state; programming a state of each cell in a group of the plurality of cells to within a first range of voltages; if a state of each of one or more of the cells in the group of cells does not verify to within the first range of voltages, identifying at least the one or more cells as failing; and if a state of each cell in the group of cells verifies to within the first range of voltages: applying a predetermined number of programming pulses to further program the state of each cell in the group of cells to within a second range of voltages; and verifying whether a state of each cell in the group of cells is programmed beyond the second range of voltages.
摘要翻译：根据本发明的实施例，一种用于测试多电平存储器的方法包括：执行擦除操作以将多个存储单元置于擦除状态; 将所述多个单元的组中的每个单元的状态编程为在第一电压范围内; 如果所述单元组中的一个或多个单元格中的每一个的状态未被验证到所述第一电压范围内，则至少将所述一个或多个单元识别为故障; 并且如果所述单元组中的每个单元的状态验证为在所述第一电压范围内：施加预定数量的编程脉冲以进一步将所述单元组中的每个单元的状态编程到第二电压范围内; 以及验证所述单元组中的每个单元的状态是否被编程超过所述第二电压范围。

18. 发明申请

US20090147579A1 NON-VOLATILE MEMORY SYSTEMS AND METHODS INCLUDING PAGE READ AND/OR CONFIGURATION FEATURES 有权
标题翻译：非易失性存储器系统和包括页面读取和/或配置功能的方法
公开(公告)号：US20090147579A1
公开(公告)日：2009-06-11
申请号：US12275191
申请日：2008-11-20
申请人： Hieu Van Tran , Sakhawat M. Khan
发明人： Hieu Van Tran , Sakhawat M. Khan
IPC分类号： G11C16/04 , G11C17/00 , G11C16/06 , G11C7/00
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a high speed source follower stage. Another embodiment has a common source stage followed by a source follower. An auto zeroing scheme is used. A capacitor sensing scheme is used. Multilevel parallel operation is described.
摘要翻译：为数字多位非易失性存储器集成系统提供高速电压模式感测。一个实施例具有本地源跟随器阶段，之后是高速公共源级。另一个实施例具有本地源极跟随器级，之后是高速源极跟随器级。另一个实施例具有公共源级，之后是源跟随器。使用自动归零方案。使用电容感测方案。描述多级并行操作。

19. 发明授权

US06751118B2 Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system 有权
标题翻译：数字多层非易失性存储器集成电路系统的阵列架构和操作方法
公开(公告)号：US06751118B2
公开(公告)日：2004-06-15
申请号：US09929542
申请日：2001-08-13
申请人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
发明人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
IPC分类号： C16
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.
摘要翻译：内存阵列架构和操作方法适用于超高密度千兆比特的多级非易失性存储器集成电路系统。阵列架构和操作方法包括：（1）禁止和选择分割方案; （2）一种多级存储器解码方案，其包括电源解码解码方案，馈通到存储器解码方案，馈通到驱动器解码方案和获胜者采用所有开尔文存储器解码方案; （3）不变总计程序方案; （4）包括快速慢速和2级斜坡速率控制编程; 以及参考系统方法和装置，其包括位置线性参考系，位置几何参考系和几何补偿参考系。该装置和方法能够实现多级编程，读取和保留。

20. 发明授权

US06282145B1 Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system 有权
标题翻译：数字多层非易失性存储器集成电路系统的阵列架构和操作方法
公开(公告)号：US06282145B1
公开(公告)日：2001-08-28
申请号：US09231928
申请日：1999-01-14
申请人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
发明人： Hieu Van Tran , Sakhawat M. Khan , George J. Korsh
IPC分类号： G11C800
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C16/08 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2211/5634
摘要： Memory array architectures and operating methods suitable for super high density in the giga bits for multilevel nonvolatile memory integrated circuit system. The array architectures and operating methods include: (1) an Inhibit and Select Segmentation Scheme; (2) a Multilevel Memory Decoding Scheme that includes a Power Supply Decoded Decoding Scheme, a Feedthrough-to-Memory Decoding Scheme, a Feedthrough-to-Driver Decoding Scheme, and a Winner-Take-All Kelvin Memory Decoding Scheme; (3) a constant-total-current-program scheme; (4) includes fast-slow and 2-step ramp rate control programming; and a reference system method and apparatus, which includes a Positional Linear Reference System, a Positional Geometric Reference System, and a Geometric Compensation Reference System. The apparatus and method enable multilevel programming, reading, and margining.
摘要翻译：内存阵列架构和操作方法适用于超高密度千兆比特的多级非易失性存储器集成电路系统。阵列架构和操作方法包括：（1）禁止和选择分割方案; （2）一种多级存储器解码方案，其包括电源解码解码方案，馈通到存储器解码方案，馈通到驱动器解码方案和获胜者采用所有开尔文存储器解码方案; （3）不变总计程序方案; （4）包括快速慢速和2级斜坡速率控制编程; 以及参考系统方法和装置，其包括位置线性参考系，位置几何参考系和几何补偿参考系。该装置和方法能够实现多级编程，读取和保留。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式