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11. 发明申请

US20080171415A1 Methods of Forming NAND Memory with Virtual Channel 有权
标题翻译：用虚拟通道形成NAND存储器的方法
公开(公告)号：US20080171415A1
公开(公告)日：2008-07-17
申请号：US11626784
申请日：2007-01-24
申请人： Henry Chien , George Matamis , Takashi Orimoto , James Kai
发明人： Henry Chien , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation.
摘要翻译：一系列非易失性存储单元通过源/漏区连接在一起，其包括在上层中由固定电荷产生的反型层。控制栅极在浮动栅极之间延伸，使得两个控制栅极耦合到浮动栅极。可以通过等离子体氮化形成固定电荷层。

12. 发明授权

US07795080B2 Methods of forming integrated circuit devices using composite spacer structures 有权
标题翻译：使用复合间隔结构形成集成电路器件的方法
公开(公告)号：US07795080B2
公开(公告)日：2010-09-14
申请号：US12014689
申请日：2008-01-15
申请人： Takashi Orimoto , George Matamis , James Kai , Tuan Pham , Masaaki Higashitani , Henry Chien
发明人： Takashi Orimoto , George Matamis , James Kai , Tuan Pham , Masaaki Higashitani , Henry Chien
IPC分类号： H01L21/82
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11521
摘要： Methods of fabricating integrated circuit devices are provided using composite spacer formation processes. A composite spacer structure is used to pattern and etch the layer stack when forming select features of the devices. A composite storage structure includes a first spacer formed from a first layer of spacer material and second and third spacers formed from a second layer of spacer material. The process is suitable for making devices with line and space sizes at less then the minimum resolvable feature size of the photolithographic processes being used. Moreover, equal line and space sizes at less than the minimum feature size are possible. In one embodiment, an array of dual control gate non-volatile flash memory storage elements is formed using composite spacer structures. When forming the active areas of the substrate, with overlying strips of a layer stack and isolation regions therebetween, a composite spacer structure facilitates equal lengths of the strips and isolation regions therebetween.
摘要翻译：使用复合间隔物形成工艺提供制造集成电路器件的方法。当形成设备的选择特征时，使用复合间隔物结构来图案化和蚀刻层堆叠。复合存储结构包括由第一隔离物材料层形成的第一间隔物和由第二隔离物材料层形成的第二和第三间隔物。该方法适用于制造具有小于所使用的光刻工艺的最小可分辨特征尺寸的线和空间尺寸的装置。此外，等于线和空间尺寸小于最小特征尺寸是可能的。在一个实施例中，使用复合间隔结构形成双控制非易失性闪存存储元件阵列。当形成衬底的活性区域时，具有叠层的叠层和隔离区之间的复合间隔结构有利于条之间的等长长度和隔离区。

13. 发明授权

US07495282B2 NAND memory with virtual channel 有权
标题翻译：具有虚拟通道的NAND内存
公开(公告)号：US07495282B2
公开(公告)日：2009-02-24
申请号：US11626778
申请日：2007-01-24
申请人： Takashi Orimoto , James Kai , Henry Chien , George Matamis
发明人： Takashi Orimoto , James Kai , Henry Chien , George Matamis
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation.
摘要翻译：一系列非易失性存储单元通过源/漏区连接在一起，其包括在上层中由固定电荷产生的反型层。控制栅极在浮动栅极之间延伸，使得两个控制栅极耦合到浮动栅极。可以通过等离子体氮化形成固定电荷层。

14. 发明申请

US20080170438A1 NAND Memory with Virtual Channel 有权
标题翻译： NAND存储器与虚拟通道
公开(公告)号：US20080170438A1
公开(公告)日：2008-07-17
申请号：US11626778
申请日：2007-01-24
申请人： Takashi Orimoto , James Kai , Henry Chien , George Matamis
发明人： Takashi Orimoto , James Kai , Henry Chien , George Matamis
IPC分类号： G11C11/34
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A string of nonvolatile memory cells are connected together by source/drain regions that include an inversion layer created by fixed charge in an overlying layer. Control gates extend between floating gates so that two control gates couple to a floating gate. A fixed charge layer may be formed by plasma nitridation.
摘要翻译：一系列非易失性存储单元通过源/漏区连接在一起，其包括在上层中由固定电荷产生的反型层。控制栅极在浮动栅极之间延伸，使得两个控制栅极耦合到浮动栅极。可以通过等离子体氮化形成固定电荷层。

15. 发明授权

US08097498B2 Damascene method of making a nonvolatile memory device 有权
公开(公告)号：US08097498B2
公开(公告)日：2012-01-17
申请号：US12693322
申请日：2010-01-25
申请人： Vinod Robert Purayath , George Matamis , James Kai , Takashi Orimoto
发明人： Vinod Robert Purayath , George Matamis , James Kai , Takashi Orimoto
IPC分类号： H01L21/20
CPC分类号： H01L27/101 , H01L27/1021
摘要： A method of making a device includes providing a first device level containing first semiconductor rails separated by first insulating features, forming a sacrificial layer over the first device level, patterning the sacrificial layer and the first semiconductor rails in the first device level to form a plurality of second rails extending in a second direction, wherein the plurality of second rails extend at least partially into the first device level and are separated from each other by rail shaped openings which extend at least partially into the first device level, forming second insulating features between the plurality of second rails, removing the sacrificial layer, and forming second semiconductor rails between the second insulating features in a second device level over the first device level. The first semiconductor rails extend in a first direction. The second semiconductor rails extend in the second direction different from the first direction.

16. 发明授权

US07807529B2 Lithographically space-defined charge storage regions in non-volatile memory 有权
标题翻译：非易失性存储器中的光刻空间定义电荷存储区域
公开(公告)号：US07807529B2
公开(公告)日：2010-10-05
申请号：US11960513
申请日：2007-12-19
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： Lithographically-defined spacing is used to define feature sizes during fabrication of semiconductor-based memory devices. Sacrificial features are formed over a substrate at a specified pitch having a line size and a space size defined by a photolithography pattern. Charge storage regions for storage elements are formed in the spaces between adjacent sacrificial features using the lithographically-defined spacing to fix a gate length or dimension of the charge storage regions in a column direction. Unequal line and space sizes at the specified pitch can be used to form feature sizes at less than the minimally resolvable feature size associated with the photolithography process. Larger line sizes can improve line-edge roughness while decreasing the dimension of the charge storage regions in the column direction. Additional charge storage regions for the storage elements can be formed over the charge storage regions so defined, such as by depositing and etching a second charge storage layer to form second charge storage regions having a dimension in the column direction that is less than the gate length of the first charge storage regions.
摘要翻译：在制造基于半导体的存储器件期间，使用光刻定义的间距来定义特征尺寸。牺牲特征以具有由光刻图案限定的线尺寸和空间尺寸的指定间距在衬底上形成。用于存储元件的电荷存储区域使用光刻定义的间隔在相邻的牺牲特征之间的空间中形成，以将电荷存储区域的栅极长度或尺寸固定在列方向上。可以使用指定间距处的不等的线和空间尺寸来形成小于与光刻工艺相关联的最小可解析特征尺寸的特征尺寸。较大的线尺寸可以改善线边缘粗糙度，同时减小电荷存储区域在列方向上的尺寸。存储元件的附加电荷存储区域可以形成在如此限定的电荷存储区域上，例如通过沉积和蚀刻第二电荷存储层以形成具有小于栅极长度的列方向尺寸的第二电荷存储区域的第一电荷存储区域。

17. 发明授权

US07736973B2 Non-volatile memory arrays having dual control gate cell structures and a thick control gate dielectric and methods of forming 有权
标题翻译：具有双控制栅极单元结构的非易失性存储器阵列和厚控制栅极电介质以及形成方法
公开(公告)号：US07736973B2
公开(公告)日：2010-06-15
申请号：US12020428
申请日：2008-01-25
申请人： Takashi Orimoto , George Matamis , James Kai
发明人： Takashi Orimoto , George Matamis , James Kai
IPC分类号： H01L21/3205
CPC分类号： H01L27/11521 , H01L27/11519
摘要： Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming are provided. A charge storage layer is etched into strips extending across a substrate surface in a row direction with a tunnel dielectric layer therebetween. The resulting strips may be continuous in the row direction or may comprise individual charge storage regions if already divided along their length in the row direction. A second layer of dielectric material is formed along the sidewalls of the strips and over the tunnel dielectric layer in the spaces therebetween. The second layer is etched into regions overlaying the tunnel dielectric layer in the spaces between strips. An intermediate dielectric layer is formed along exposed portions of the sidewalls of the strips and over the second dielectric layer in the spaces therebetween. A layer of control gate material is deposited in the spaces between strips. The resulting control gates are separated from the strips by the intermediate dielectric layer and from the substrate surface by the tunnel dielectric layer, the second layer of dielectric material and the intermediate dielectric layer.
摘要翻译：提供了具有双控制栅极存储单元的非易失性半导体存储器件和形成方法。电荷存储层被蚀刻成沿着行方向延伸穿过衬底表面的条带，其间具有隧道介电层。所得到的条带可以在行方向上是连续的，或者可以包括单独的电荷存储区域，如果沿着它们的行方向上的长度被划分。第二层电介质材料沿着条的侧壁和隧道介电层之间的空间形成。第二层被蚀刻到条带之间的空间中覆盖隧道介电层的区域中。沿着条的侧壁的暴露部分和在它们之间的空间中的第二介电层上方形成中间介电层。控制栅极材料层沉积在条带之间的空间中。所得到的控制栅极通过中间介电层和通过隧道介电层，第二介电材料层和中间介质层从衬底表面与条分离。

18. 发明申请

US20100055889A1 Composite Charge Storage Structure Formation In Non-Volatile Memory Using Etch Stop Technologies 有权
标题翻译：使用蚀刻停止技术在非易失性存储器中的复合电荷存储结构形成
公开(公告)号：US20100055889A1
公开(公告)日：2010-03-04
申请号：US12615154
申请日：2009-11-09
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai
IPC分类号： H01L21/28
CPC分类号： H01L27/11521 , H01L29/42324 , H01L29/7881
摘要： Semiconductor-based non-volatile memory that includes memory cells with composite charge storage elements is fabricated using an etch stop layer during formation of at least a portion of the storage element. One composite charge storage element suitable for memory applications includes a first charge storage region having a larger gate length or dimension in a column direction than a second charge storage region. While not required, the different regions can be formed of the same or similar materials, such as polysilicon. Etching a second charge storage layer selectively with respect to a first charge storage layer can be performed using an interleaving etch-stop layer. The first charge storage layer is protected from overetching or damage during etching of the second charge storage layer. Consistency in the dimensions of the individual memory cells can be increased.
摘要翻译：包括具有复合电荷存储元件的存储器单元的基于半导体的非易失性存储器在形成存储元件的至少一部分期间使用蚀刻停止层制造。适用于存储器应用的一个复合电荷存储元件包括具有比第二电荷存储区域在列方向上更大的栅极长度或尺寸的第一电荷存储区域。虽然不需要，但是不同的区域可以由相同或相似的材料形成，例如多晶硅。可以使用交错蚀刻停止层来执行相对于第一电荷存储层选择性地蚀刻第二电荷存储层。第一电荷存储层在第二电荷存储层的蚀刻期间被保护以免过蚀或损坏。可以增加各个存储单元尺寸的一致性。

19. 发明申请

US20080248621A1 Integrated Non-Volatile Memory And Peripheral Circuitry Fabrication 有权
标题翻译：集成非易失性存储器和外围电路制造
公开(公告)号：US20080248621A1
公开(公告)日：2008-10-09
申请号：US12058512
申请日：2008-03-28
申请人： James Kai , Tuan Pham , Masaaki Higashitani , George Matamis , Takashi Orimoto
发明人： James Kai , Tuan Pham , Masaaki Higashitani , George Matamis , Takashi Orimoto
IPC分类号： H01L21/336
CPC分类号： H01L27/11529 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11536 , H01L27/11539
摘要： Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array.
摘要翻译：提供非易失性存储器和集成存储器和外围电路制造工艺。使用诸如第一多晶硅层的电荷存储材料层在半导体衬底上形成诸如包括多个非易失性存储元件的NAND串的电荷存储区的集合。中间电介质层设置在电荷存储区域的上方。将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于存储元件组的选择晶体管的电荷存储区域和栅极区域的控制栅极。从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。这些器件的栅极区域可以由形成存储器阵列的控制栅极的层形成。

20. 发明授权

US08546152B2 Enhanced endpoint detection in non-volatile memory fabrication processes 有权
标题翻译：在非易失性存储器制造过程中增强端点检测
公开(公告)号：US08546152B2
公开(公告)日：2013-10-01
申请号：US11960485
申请日：2007-12-19
申请人： Takashi Orimoto , George Matamis , James Kai , Vinod Robert Purayath
发明人： Takashi Orimoto , George Matamis , James Kai , Vinod Robert Purayath
IPC分类号： H01L21/66
CPC分类号： H01L22/26 , H01L27/11521
摘要： A method of fabricating non-volatile memory is provided for memory cells employing a charge storage element with multiple charge storage regions. A first charge storage layer is formed over a tunnel dielectric layer at both a memory array region and an endpoint region of a semiconductor substrate. The first charge storage layer is removed from the endpoint region to expose the tunnel dielectric region. A second charge storage layer is formed over the first charge storage layer at the memory array region and over the tunnel dielectric layer at the endpoint region. When etching the second charge storage layer to form the stem regions of the memory cells, the tunnel dielectric layer provides a detectable endpoint signal to indicate that etching for the second charge storage layer is complete.
摘要翻译：提供一种制造非易失性存储器的方法，用于采用具有多个电荷存储区域的电荷存储元件的存储单元。第一电荷存储层在半导体衬底的存储器阵列区域和端点区域的隧道电介质层上形成。从端点区域去除第一电荷存储层以暴露隧道电介质区域。第二电荷存储层形成在存储器阵列区域的第一电荷存储层上，并在端点区域的隧道电介质层上形成。当蚀刻第二电荷存储层以形成存储器单元的干区域时，隧道介电层提供可检测的端点信号，以指示第二电荷存储层的蚀刻完成。

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