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11. 发明授权

US06671753B2 Elastic interface apparatus and method therefor 有权
公开(公告)号：US06671753B2
公开(公告)日：2003-12-30
申请号：US09961506
申请日：2001-09-24
申请人： Daniel Mark Dreps , Frank David Ferraiolo , Kevin Charles Gower
发明人： Daniel Mark Dreps , Frank David Ferraiolo , Kevin Charles Gower
IPC分类号： G06F1300
CPC分类号： G06F5/06 , G06F2205/104 , H04L7/0008 , H04L7/02
摘要： An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

12. 发明授权

US06549971B1 Cascaded differential receiver circuit 有权
标题翻译：级联差分接收电路
公开(公告)号：US06549971B1
公开(公告)日：2003-04-15
申请号：US09383735
申请日：1999-08-26
申请人： Delbert Raymond Cecchi , Daniel Mark Dreps
发明人： Delbert Raymond Cecchi , Daniel Mark Dreps
IPC分类号： G06F100
CPC分类号： H04L25/0292 , H04L25/0272
摘要： A differential receiver circuit including first, second, and third amplification stages. The first amplification stage is configured to receive a differential input signal and to produce a single ended first output signal responsive to the differential input signal. The second amplification stage is connected in parallel with the first stage and configured to receive the differential input signal and to produce a second output signal responsive to the differential input signal. The third amplification stage is configured to receive the first and second output signals and to produce a single ended third output signal indicative of the differential in the first and second output signals. In one embodiment the differential receiver circuit further includes an inhibit circuit configured receive an inhibit control signal and to drive the p-channel devices gated to the first amplifier node and the n-channel devices gated to the second amplifier node to cutoff when the inhibit control signal is in a specified inhibit state. The inhibit circuit is preferably further configured to provide a low impedance path between the first amplifier node, the second amplifier node, and the feedback node when the inhibit control signal is in a specified functional state.
摘要翻译：一种包括第一，第二和第三放大级的差分接收器电路。第一放大级被配置为接收差分输入信号并响应差分输入信号产生单端第一输出信号。第二放大级与第一级并联连接，并被配置为接收差分输入信号并响应差分输入信号产生第二输出信号。第三放大级被配置为接收第一和第二输出信号并且产生指示第一和第二输出信号中的差分的单端第三输出信号。在一个实施例中，差分接收器电路还包括禁止电路，其配置为接收禁止控制信号并驱动门控到第一放大器节点的p沟道器件和门控到第二放大器节点的n沟道器件在禁止控制信号处于指定的禁止状态。禁止电路优选地还被配置为当禁止控制信号处于指定的功能状态时，在第一放大器节点，第二放大器节点和反馈节点之间提供低阻抗路径。

13. 发明授权

US06014047A Method and apparatus for phase rotation in a phase locked loop 失效
标题翻译：在锁相环中相位旋转的方法和装置
公开(公告)号：US06014047A
公开(公告)日：2000-01-11
申请号：US4133
申请日：1998-01-07
申请人： Daniel Mark Dreps , Robert Paul Masleid , John Stephen Muhich
发明人： Daniel Mark Dreps , Robert Paul Masleid , John Stephen Muhich
IPC分类号： G06F1/06 , G06F1/04 , G06F1/10 , H03K5/135 , H03L7/06 , H03L7/081 , H03L7/099
CPC分类号： H03K5/135 , G06F1/04 , G06F1/10 , H03L7/0814 , H03L7/0991
摘要： Among a plurality of signals, each phase-shifted with respect to the others, one signal is repeatedly substituted for another as a clock signal, to reduce a phase error of the clock signal with respect to a reference clock. The substitutions are timed to occur during intervals tending to reduce disturbances to the clock signal. Also, such substitution of a signal is responsive to occurrence of at least one cycle of the signal subsequent to the clock being supplied by an immediate predecessor of the signal, which tends to prevent erroneous substitutions of one signal for another.
摘要翻译：在多个相对于其它信号相移的信号中，一个信号被重复地替换为另一个信号作为时钟信号，以减少时钟信号相对于参考时钟的相位误差。这些替代被定时在间隔期间发生，以减少对时钟信号的干扰。此外，信号的这种替换响应于由信号的直接前辈提供的时钟之后的信号的至少一个周期的发生，这倾向于防止一个信号被错误地替换为另一个信号。

14. 发明授权

US07733984B2 Implementing phase rotator circuits with embedded polyphase filter network stage 失效
标题翻译：实现具有嵌入式多相滤波器网络阶段的相位旋转电路
公开(公告)号：US07733984B2
公开(公告)日：2010-06-08
申请号：US11557695
申请日：2006-11-08
申请人： Steven John Baumgartner , Anthony Richard Bonaccio , John Francis Bulzacchelli , Daniel Mark Dreps
发明人： Steven John Baumgartner , Anthony Richard Bonaccio , John Francis Bulzacchelli , Daniel Mark Dreps
IPC分类号： H04L27/00
CPC分类号： H03H11/02
摘要： A method for implementing phase rotator circuits and phase rotator circuit of the invention includes a polyphase filter network to create a quadrature phase version of the input signal. The polyphase filter network is partitioned into a first part that is physically isolated from the phase rotator circuit and a second part that is embedded in the phase rotator circuit. The second part of the polyphase filter is coupled to the first part of the polyphase filter by a high-pass equalizing buffer stage. The second part of the polyphase filter is coupled to the phase rotator circuit by a bandlimiting buffer stage.
摘要翻译：用于实现本发明的相位旋转电路和相位旋转电路的方法包括多相滤波器网络，以产生输入信号的正交相位版本。多相滤波器网络被划分为与相位旋转电路物理隔离的第一部分和嵌入在相位旋转电路中的第二部分。多相滤波器的第二部分通过高通均衡缓冲级耦合到多相滤波器的第一部分。多相滤波器的第二部分通过带限幅缓冲器级耦合到相位旋转器电路。

15. 发明申请

US20090049339A1 Programmable Diagnostic Memory Module 失效
标题翻译：可编程诊断内存模块
公开(公告)号：US20090049339A1
公开(公告)日：2009-02-19
申请号：US11840481
申请日：2007-08-17
申请人： Moises Cases , Daniel Mark Dreps , Bhyrav M. Mutnury , Nam H. Pham , Daniel N. De Araujo
发明人： Moises Cases , Daniel Mark Dreps , Bhyrav M. Mutnury , Nam H. Pham , Daniel N. De Araujo
IPC分类号： G06F11/00
CPC分类号： G06F11/2733 , G11C5/04 , G11C29/02 , G11C29/022 , G11C29/16 , G11C29/56 , G11C2029/5602
摘要： A programmable diagnostic memory module provides enhanced testability of memory controller and memory subsystem design. The programmable diagnostic memory module includes an interface for communicating with an external diagnostic system, and the interface is used to transfer commands to the memory module to alter various behaviors of the memory module. The altered behaviors may be changing data streams that are written to the memory module to simulate errors, altering the timing and/or loading of the memory module signals, downloading programs for execution by a processor core within the memory module, changing driver strengths of output signals of the memory module, and manipulating in an analog domain, signals at terminals of the memory module such as injecting noise on power supply connections to the memory module. The memory module may emulate multiple selectable memory module types, and may include a complete storage array to provide standard memory module operation.
摘要翻译：可编程诊断内存模块提供了内存控制器和内存子系统设计的增强的可测试性。可编程诊断存储器模块包括用于与外部诊断系统通信的接口，并且该接口用于将命令传送到存储器模块以改变存储器模块的各种行为。改变的行为可能是改变被写入存储器模块的数据流，以模拟错误，改变存储器模块信号的定时和/或加载，下载由存储器模块内的处理器核心执行的程序，改变驱动器的输出强度存储器模块的信号和在模拟域中的操作，在存储器模块的端子处发出信号，例如在与存储器模块的电源连接上注入噪声。存储器模块可以模拟多个可选择的存储器模块类型，并且可以包括完整的存储阵列以提供标准存储器模块操作。

16. 发明授权

US06703866B1 Selectable interface for interfacing integrated circuit modules 有权
标题翻译：用于接口集成电路模块的可选接口
公开(公告)号：US06703866B1
公开(公告)日：2004-03-09
申请号：US09740250
申请日：2000-12-19
申请人： Ravi Kumar Arimilli , Daniel Mark Dreps
发明人： Ravi Kumar Arimilli , Daniel Mark Dreps
IPC分类号： H03K19175
CPC分类号： H04L25/028 , H03K19/017581 , H04L25/0272 , H04L25/0292
摘要： A selectable interface for interfacing integrated circuit modules is disclosed. The bus interface for interconnecting a first circuit module and a second circuit module includes a transmitter pair located within the first circuit module and a receiver pair located within the second circuit module. The transmitter pair, which can be selectable between a differential mode and a single-ended mode, transmits data from the first circuit module to the second circuit module. The receiver pair, which can also be selectable between a differential mode and a single-ended mode, receives data from the transmitter pair.
摘要翻译：公开了用于接口集成电路模块的可选接口。用于互连第一电路模块和第二电路模块的总线接口包括位于第一电路模块内的发射机对和位于第二电路模块内的接收机对。可以在差模和单端模式之间选择的发射机对将数据从第一电路模块传输到第二电路模块。也可以在差分模式和单端模式之间选择的接收器对从发送器对接收数据。

17. 发明授权

US06542999B1 System for latching first and second data on opposite edges of a first clock and outputting both data in response to a second clock 失效
标题翻译：用于在第一时钟的相对边缘上锁存第一和第二数据并响应于第二时钟输出两个数据的系统
公开(公告)号：US06542999B1
公开(公告)日：2003-04-01
申请号：US09434801
申请日：1999-11-05
申请人： Daniel Mark Dreps , Kevin Charles Gower , Frank David Ferraiolo
发明人： Daniel Mark Dreps , Kevin Charles Gower , Frank David Ferraiolo
IPC分类号： G06F112
CPC分类号： G06F5/06
摘要： An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.
摘要翻译：实现弹性接口装置和方法。弹性接口包括用于存储数据值流的多个存储单元，其中每个存储单元顺序地存储各组数据值的成员。每个数据值被存储在本地时钟的预定数量的周期内。选择电路可以耦合到存储单元以从数据流中选择相应的数据值，以存储在相应的存储单元中。与本地时钟的目标周期上的本地时钟同步地从每个存储单元顺序地输出数据。

18. 发明授权

US06442223B1 Method and system for data transfer 失效
标题翻译：数据传输方法和系统
公开(公告)号：US06442223B1
公开(公告)日：2002-08-27
申请号：US09299716
申请日：1999-04-26
申请人： Daniel Mark Dreps , Frank David Ferraiolo , Kevin Charles Gower , Toru Kobayashi , Bradley David McCredie , Hideo Sawamoto
发明人： Daniel Mark Dreps , Frank David Ferraiolo , Kevin Charles Gower , Toru Kobayashi , Bradley David McCredie , Hideo Sawamoto
IPC分类号： H04L700
CPC分类号： H04L25/05 , H04L7/0012 , H04L7/02 , H04L7/046
摘要： A method and system for increasing speeds of transferring data in a data transfer system which includes a data source and data sink. Both the data source and data sink include clocks which are synchronized to a common clock frequency. A buffer is provided at the data sink and this buffer is utilized to received data from the data source. A control circuit is provided at the data sink and this control circuit receives a bus clock signal from the data source. An N segment dynamic shift register is provided within the data sink which includes at least two segments. A selectable shift control is provided for passing the data through an M segment subset of the N segment shift register, where M is less than N. Additionally, the length of the M segment subset is determined by the phase of a clock within the data sink at the time which the bus clock signal from the data source is received at the data sink. By selectively passing the data through an M segment subset of the N segment shift register, the data is accessible at the data sink at a controllable predetermined time.
摘要翻译：一种用于在包括数据源和数据宿的数据传输系统中提高传输数据速度的方法和系统。数据源和数据宿均包含与公共时钟频率同步的时钟。在数据接收器处提供缓冲器，并且该缓冲器用于从数据源接收数据。在数据宿提供控制电路，该控制电路从数据源接收总线时钟信号。 N段动态移位寄存器提供在数据宿内，其包括至少两个段。提供了可选择的移位控制，用于使数据通过N段移位寄存器的M段子集，其中M小于N.另外，M段子集的长度由数据宿内的时钟的相位确定在数据接收器处接收到来自数据源的总线时钟信号的时间。通过选择性地将数据通过N段移位寄存器的M段子集，可以在可控的预定时间在数据宿处访问数据。

19. 发明授权

US6084432A Driver circuit having reduced noise 失效
标题翻译：驱动电路噪音降低
公开(公告)号：US6084432A
公开(公告)日：2000-07-04
申请号：US050162
申请日：1998-03-30
申请人： Daniel Mark Dreps , Douglas Ele Martin
发明人： Daniel Mark Dreps , Douglas Ele Martin
IPC分类号： H03K17/16 , H03K19/175
CPC分类号： H03K17/164 , H03K17/163
摘要： A driver circuit has an output node coupled to a chip pad. A first PFET and a first resistor are connected between a power supply and the output node, wherein the first resistor is connected between the first PFET and the output node. A first NFET and a second resistor are connected between a ground potential and the output node, wherein the second resistor is connected between the first NFET and the output node. A third resistor is connected between an input to the driver circuit and a gate electrode of the first PFET. A fourth resistor is connected between the input to the driver circuit and a gate electrode of the first NFET. The pre-drive circuitry for driving the input to the PFET may include an NFET coupled between the ground potential and the input, wherein the gate electrode of the NFET receives the data signal to be driven. The NFET pre-drive circuitry may include a PFET coupled between the power supply and the input to the NFET portion of the driver circuit, wherein the gate electrode of this PFET also receives the data signal to be driven. A plurality of these driver circuits may be connected in parallel and in series in order to modify the output impedance.
摘要翻译：驱动器电路具有耦合到芯片焊盘的输出节点。第一PFET和第一电阻器连接在电源和输出节点之间，其中第一电阻连接在第一PFET和输出节点之间。第一NFET和第二电阻器连接在接地电位和输出节点之间，其中第二电阻器连接在第一NFET与输出节点之间。第三电阻器连接在驱动电路的输入端和第一PFET的栅电极之间。在驱动电路的输入端与第一NFET的栅电极之间连接第四电阻。用于驱动输入到PFET的预驱动电路可以包括耦合在地电位和输入端之间的NFET，其中NFET的栅电极接收待驱动的数据信号。 NFET预驱动电路可以包括耦合在电源和驱动电路的NFET部分的输入之间的PFET，其中该PFET的栅电极还接收待驱动的数据信号。多个这些驱动器电路可并联并串联连接，以便修改输出阻抗。

20. 发明授权

US06072840A High speed differential CMOS sine-wave receiver with duty-cycle control means 失效
标题翻译：具有占空比控制装置的高速差分CMOS正弦波接收器
公开(公告)号：US06072840A
公开(公告)日：2000-06-06
申请号：US844504
申请日：1997-04-18
申请人： Daniel Mark Dreps
发明人： Daniel Mark Dreps
IPC分类号： H04L25/02 , H04L27/02
CPC分类号： H04L25/0292
摘要： A system and method for providing a high speed differential receiver circuit is disclosed. The system comprises a source device. A receiver is coupled to the source device. The receiver receives first and second differential signals at a first input and a second input and provides first and second output signals at a first output and a second output. The system also comprises a first plurality of load devices coupled to the first output. The first plurality of load devices control a first voltage swing at the first output. The system also comprises a second plurality of load devices coupled to the second output. The second plurality of load devices control a second voltage swing at the second output.
摘要翻译：公开了一种用于提供高速差动接收器电路的系统和方法。该系统包括源设备。接收机耦合到源设备。接收机在第一输入端和第二输入端接收第一和第二差分信号，并在第一输出和第二输出端提供第一和第二输出信号。该系统还包括耦合到第一输出的第一多个负载装置。第一组多个负载装置控制第一输出端的第一电压摆幅。该系统还包括耦合到第二输出的第二多个负载装置。第二组多个负载装置在第二输出端控制第二电压摆幅。

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