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11. 发明授权

US08098516B2 Static source plane in STRAM 有权
标题翻译： STRAM中的静态源平面
公开(公告)号：US08098516B2
公开(公告)日：2012-01-17
申请号：US12855896
申请日：2010-08-13
申请人： Hai Li , Yiran Chen , Hongyue Liu , Xuguang Wang
发明人： Hai Li , Yiran Chen , Hongyue Liu , Xuguang Wang
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1659
摘要： A memory array includes a plurality of magnetic tunnel junction cells arranged in a 2 by 2 array. Each magnetic tunnel junction cell is electrically coupled between a bit line and a source line and each magnetic tunnel junction cell electrically coupled to a transistor. Each magnetic tunnel junction cell is configured to switch between a high resistance state and a low resistance state by passing a write current passing though the magnetic tunnel junction cell. A first word line is electrically coupled to a gate of first set of two of the transistors and a second word line is electrically coupled to a gate of a second set of two of the transistors. The source line is a common source line for the plurality of magnetic tunnel junctions.
摘要翻译：存储器阵列包括以2×2阵列排列的多个磁性隧道结单元。每个磁性隧道结单元电耦合在位线和源极线之间，并且每个磁性隧道结单元电耦合到晶体管。每个磁性隧道结单元被配置为通过使经过磁性隧道结单元的写入电流通过高电阻状态和低电阻状态之间切换。第一字线电耦合到第一组晶体管的第一组的栅极，并且第二字线电耦合到第二组二个晶体管的栅极。源极线是用于多个磁性隧道结的公共源极线。

12. 发明授权

US08054673B2 Three dimensionally stacked non volatile memory units 有权
标题翻译：三维堆叠的非易失性存储单元
公开(公告)号：US08054673B2
公开(公告)日：2011-11-08
申请号：US12425084
申请日：2009-04-16
申请人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
发明人： Xuguang Wang , Yong Lu , Hai Li , Hongyue Liu
IPC分类号： G11C11/00 , G11C11/14 , G11C11/22 , H01L23/52 , H01L23/02
CPC分类号： H01L27/228 , G11C11/161 , H01L27/2436 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/14 , H01L45/142 , H01L45/146 , H01L45/147 , H01L2924/0002 , H01L2924/00
摘要： A memory unit including a first transistor spanning a first transistor region in a first layer of the memory unit; a second transistor spanning a second transistor region in a second layer of the memory unit; a first resistive sense memory (RSM) cell spanning a first memory region in a third layer of the memory unit; and a second RSM cell spanning a second memory region in the third layer of the memory unit, wherein the first transistor is electrically coupled to the first RSM cell, and the second transistor is electrically coupled to the second RSM cell, wherein the second layer is between the first and third layers, wherein the first and second transistor have an transistor overlap region, and wherein the first memory region and the second memory region do not extend beyond the first transistor region and the second transistor region.
摘要翻译：存储单元，包括跨越存储器单元的第一层中的第一晶体管区域的第一晶体管; 跨越存储器单元的第二层中的第二晶体管区域的第二晶体管; 跨越存储器单元的第三层中的第一存储器区域的第一电阻读出存储器（RSM）单元; 以及跨越存储器单元的第三层中的第二存储器区域的第二RSM单元，其中第一晶体管电耦合到第一RSM单元，并且第二晶体管电耦合到第二RSM单元，其中第二层是在第一和第三层之间，其中第一和第二晶体管具有晶体管重叠区域，并且其中第一存储区域和第二存储器区域不延伸超过第一晶体管区域和第二晶体管区域。

13. 发明授权

US08045412B2 Multi-stage parallel data transfer 有权
标题翻译：多级并行数据传输
公开(公告)号：US08045412B2
公开(公告)日：2011-10-25
申请号：US12487165
申请日：2009-06-18
申请人： Yong Lu , Harry Hongyue Liu , Hai Li , Andrew John Carter , Daniel Reed
发明人： Yong Lu , Harry Hongyue Liu , Hai Li , Andrew John Carter , Daniel Reed
IPC分类号： G11C7/00
CPC分类号： G11C13/0064 , G11C11/1675 , G11C11/56 , G11C13/0069 , G11C2013/0078 , G11C2013/0088 , G11C2211/5622 , G11C2211/5642 , G11C2211/5643 , G11C2213/79
摘要： Apparatus and associated method for transferring data to memory, such as resistive sense memory (RSM). In accordance with some embodiments, input data comprising a sequence of logical states are transferred to a block of memory by concurrently writing a first logical state from the sequence to each of a first plurality of unit cells during a first write step, and concurrently writing a second logical state from the sequence to each of a second non-overlapping plurality of unit cells during a second write step.
摘要翻译：用于将数据传送到存储器的装置和相关方法，例如电阻读出存储器（RSM）。根据一些实施例，包括逻辑状态序列的输入数据通过在第一写入步骤期间同时向第一多个单位单元中的每个单元写入第一逻辑状态而将第一逻辑状态写入存储器块，并且同时写入在第二写入步骤期间从序列到第二非重叠多个单位单元中的每一个的第二逻辑状态。

14. 发明申请

US20110228598A1 TRANSMISSION GATE-BASED SPIN-TRANSFER TORQUE MEMORY UNIT 有权
标题翻译：基于传输门控的转子转矩记忆单元
公开(公告)号：US20110228598A1
公开(公告)日：2011-09-22
申请号：US13149136
申请日：2011-05-31
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Yang Li
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Yang Li
IPC分类号： G11C11/14
CPC分类号： G11C11/1657 , G11C11/1659 , G11C11/1675 , Y10S977/935
摘要： A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.
摘要翻译：描述基于传输门的自旋转移转矩存储单元。存储单元包括电耦合到位线和源极线的磁性隧道结数据单元。 NMOS晶体管与PMOS晶体管并联电连接，并且它们与源极线和磁性隧道结数据单元电连接。磁隧道结数据单元被配置为通过使极化写入电流通过磁性隧道结数据单元在高电阻状态和低电阻状态之间切换。 PMOS晶体管和NMOS晶体管可单独寻址，使得第一方向上的第一写入电流流过PMOS晶体管，并且第二方向的第二写入电流流过NMOS晶体管。

15. 发明授权

US07974119B2 Transmission gate-based spin-transfer torque memory unit 有权
标题翻译：基于传输栅极的自旋转移转矩存储单元
公开(公告)号：US07974119B2
公开(公告)日：2011-07-05
申请号：US12170549
申请日：2008-07-10
申请人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Yang Li
发明人： Yiran Chen , Hai Li , Hongyue Liu , Yong Lu , Yang Li
IPC分类号： G11C11/00
CPC分类号： G11C11/1657 , G11C11/1659 , G11C11/1675 , Y10S977/935
摘要： A transmission gate-based spin-transfer torque memory unit is described. The memory unit includes a magnetic tunnel junction data cell electrically coupled to a bit line and a source line. A NMOS transistor is in parallel electrical connection with a PMOS transistor and they are electrically connected with the source line and the magnetic tunnel junction data cell. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell. The PMOS transistor and the NMOS transistor are separately addressable so that a first write current in a first direction flows through the PMOS transistor and a second write current in a second direction flows through the NMOS transistor.
摘要翻译：描述基于传输门的自旋转移转矩存储单元。存储单元包括电耦合到位线和源极线的磁性隧道结数据单元。 NMOS晶体管与PMOS晶体管并联电连接，并且它们与源极线和磁性隧道结数据单元电连接。磁隧道结数据单元被配置为通过使极化写入电流通过磁性隧道结数据单元在高电阻状态和低电阻状态之间切换。 PMOS晶体管和NMOS晶体管可单独寻址，使得第一方向上的第一写入电流流过PMOS晶体管，并且第二方向的第二写入电流流过NMOS晶体管。

16. 发明申请

US20110122679A1 Resistive Sense Memory Calibration for Self-Reference Read Method 有权
标题翻译：用于自参考读取方法的电阻式感应存储器校准
公开(公告)号：US20110122679A1
公开(公告)日：2011-05-26
申请号：US13015085
申请日：2011-01-27
申请人： Yiran Chen , Hai Li , Wenzhong Zhu , Xiaobin Wang , Henry Huang , Hongyue Liu
发明人： Yiran Chen , Hai Li , Wenzhong Zhu , Xiaobin Wang , Henry Huang , Hongyue Liu
IPC分类号： G11C11/00
CPC分类号： G11C13/004 , G11C11/1673 , G11C27/02 , G11C2013/0057 , G11C2207/2254
摘要： Resistive memory calibration for self-reference read methods are described. One method of self-reference reading a resistive memory unit includes setting a plurality of resistive memory units to a first resistive data state. The resistive memory units forms a memory array. Reading a sensed resistive data state for each resistive memory unit by applying a first read current and a second read current through each resistive memory unit and then comparing voltages formed by the first read current and the second read current to determine the sensed resistive data state for each resistive memory unit. Then the method includes adjusting the first or the second read current, read voltages, or storage device capacitance for each resistive memory unit where the sensed resistive data state was not the same as the first resistive data state until the sensed resistive data state is the same as the first resistive data state.
摘要翻译：描述了自参考读取方法的电阻记忆校准。读取电阻性存储器单元的一种自参考方法包括将多个电阻存储器单元设置为第一电阻数据状态。电阻存储器单元形成存储器阵列。通过施加第一读取电流和第二读取电流通过每个电阻性存储器单元，然后比较由第一读取电流和第二读取电流形成的电压，来为每个电阻式存储器单元读取感测的电阻数据状态，以确定感测的电阻数据状态每个电阻存储器单元。然后，该方法包括调整每个电阻性存储器单元的第一或第二读取电流，读取电压或存储器件电容，其中感测的电阻数据状态与第一电阻数据状态不同，直到感测的电阻数据状态相同作为第一电阻数据状态。

17. 发明授权

US07936625B2 Pipeline sensing using voltage storage elements to read non-volatile memory cells 有权
标题翻译：管道感应使用电压存储元件来读取非易失性存储单元
公开(公告)号：US07936625B2
公开(公告)日：2011-05-03
申请号：US12409671
申请日：2009-03-24
申请人： Yiran Chen , Hai Li , Harry Hongyue Liu , KangYong Kim , Henry F. Huang
发明人： Yiran Chen , Hai Li , Harry Hongyue Liu , KangYong Kim , Henry F. Huang
IPC分类号： G11C7/00
CPC分类号： G11C7/1039 , G11C7/08 , G11C11/1673 , G11C11/1675 , G11C11/1693 , G11C11/56 , G11C11/5607 , G11C13/00 , G11C13/004 , G11C13/0061 , G11C2013/0054
摘要： Various embodiments are generally directed to a method and apparatus for carrying out a pipeline sensing operation. In some embodiments, a read voltage from a first memory cell is stored in a voltage storage element (VSE) and compared to a reference voltage to identify a corresponding memory state of the first memory cell while a second read voltage from a second memory cell is stored in a second VSE. In other embodiments, bias currents are simultaneously applied to a first set of memory cells from the array while read voltages generated thereby are stored in a corresponding first set of VSEs. The read voltages are sequentially compared with at least one reference value to serially output a logical sequence corresponding to the memory states of the first set of memory cells while read voltages are stored for a second set of memory cells in a second set of VSEs.
摘要翻译：各种实施例通常涉及用于执行流水线检测操作的方法和装置。在一些实施例中，来自第一存储器单元的读取电压被存储在电压存储元件（VSE）中并与参考电压进行比较，以识别第一存储器单元的相应存储器状态，而来自第二存储器单元的第二读取电压为存储在第二个VSE中。在其他实施例中，偏置电流同时从阵列施加到第一组存储器单元，而由此产生的读取电压被存储在对应的第一组VSE中。读取电压与至少一个参考值顺序地比较，以串行输出对应于第一组存储器单元的存储器状态的逻辑序列，而在第二组VSE中为第二组存储器单元存储读取电压。

18. 发明授权

US07936622B2 Defective bit scheme for multi-layer integrated memory device 有权
标题翻译：多层集成存储器件的不良位方案
公开(公告)号：US07936622B2
公开(公告)日：2011-05-03
申请号：US12502194
申请日：2009-07-13
申请人： Hai Li , Yiran Chen , Dadi Setiadi , Harry Hongyue Liu , Brian Lee
发明人： Hai Li , Yiran Chen , Dadi Setiadi , Harry Hongyue Liu , Brian Lee
IPC分类号： G11C29/00
CPC分类号： G11C5/04 , G11C5/02 , G11C5/025 , G11C29/44 , G11C29/808 , G11C2029/0403
摘要： Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.
摘要翻译：本发明的各种实施例一般涉及用于处理多层集成存储器件中的不良位的装置和相关方法。根据一些实施例，多层集成存储器件由多个垂直堆叠的半导体层形成，每个半导体层具有多个存储子阵列和冗余子阵列。测试每个半导体层以确定每个阵列的缺陷率，并且将具有相对较高缺陷率的第一半导体层的缺陷部分存储到具有相对较低缺陷率的第二半导体层的冗余子阵列中。

19. 发明授权

US07898838B2 Resistive sense memory calibration for self-reference read method 有权
标题翻译：电阻式记忆校准用于自参考读取方法
公开(公告)号：US07898838B2
公开(公告)日：2011-03-01
申请号：US12390728
申请日：2009-02-23
申请人： Yiran Chen , Hai Li , Wenzhong Zhu , Xiaobin Wang , Henry Huang , Hongyue Liu
发明人： Yiran Chen , Hai Li , Wenzhong Zhu , Xiaobin Wang , Henry Huang , Hongyue Liu
IPC分类号： G11C11/00 , G11C7/06 , G11C5/14
CPC分类号： G11C13/004 , G11C11/1673 , G11C27/02 , G11C2013/0057 , G11C2207/2254
摘要： Resistive memory calibration for self-reference read methods are described. One method of self-reference reading a resistive memory unit includes setting a plurality of resistive memory units to a first resistive data state. The resistive memory units forms a memory array. Reading a sensed resistive data state for each resistive memory unit by applying a first read current and a second read current through each resistive memory unit and then comparing voltages formed by the first read current and the second read current to determine the sensed resistive data state for each resistive memory unit. Then the method includes adjusting the first or the second read current, read voltages, or storage device capacitance for each resistive memory unit where the sensed resistive data state was not the same as the first resistive data state until the sensed resistive data state is the same as the first resistive data state.
摘要翻译：描述了自参考读取方法的电阻记忆校准。读取电阻性存储器单元的一种自参考方法包括将多个电阻存储器单元设置为第一电阻数据状态。电阻存储器单元形成存储器阵列。通过施加第一读取电流和第二读取电流通过每个电阻性存储器单元，然后比较由第一读取电流和第二读取电流形成的电压，来为每个电阻性存储器单元读取感测的电阻数据状态，以确定感测的电阻数据状态每个电阻存储器单元。然后，该方法包括调整每个电阻性存储器单元的第一或第二读取电流，读取电压或存储器件电容，其中感测的电阻数据状态与第一电阻数据状态不同，直到感测的电阻数据状态相同作为第一电阻数据状态。

20. 发明申请

US20100262424A1 Method of Eliminating Background Noise and a Device Using the Same 有权
标题翻译：消除背景噪声的方法及使用其的设备
公开(公告)号：US20100262424A1
公开(公告)日：2010-10-14
申请号：US12613510
申请日：2009-11-05
申请人： Hai Li , Kunping Xu , Lizhen Zhang , Yun Yang , Wei Feng
发明人： Hai Li , Kunping Xu , Lizhen Zhang , Yun Yang , Wei Feng
IPC分类号： G10L15/20
CPC分类号： G10L21/0208 , G10L2021/02168
摘要： The present invention provides a method of eliminating background noise and a device using the same. The method of eliminating background noise comprises the steps of: detecting an effective value of a received audio signal, and generating an average power signal of the received audio signal; generating a noise eliminating control signal by comparing the average power signal with a first threshold; and eliminating the noise, and amplifying the voice signal using the noise eliminating control signal. A device of eliminating background noise comprises a detecting unit, which is configured to detect an effective value, and generate an average power signal of the received audio signal; a first signal generating unit, which is configured to generate a noise eliminating control signal; and an amplifying unit, which is configured to eliminate the noise, and amplify the voice signal.
摘要翻译：本发明提供一种消除背景噪声的方法和使用该方法的装置。消除背景噪声的方法包括以下步骤：检测所接收的音频信号的有效值，并产生所接收的音频信号的平均功率信号; 通过将所述平均功率信号与第一阈值进行比较来产生噪声消除控制信号; 并消除噪声，并使用噪声消除控制信号放大语音信号。消除背景噪声的装置包括：检测单元，被配置为检测有效值，并产生所接收的音频信号的平均功率信号; 第一信号生成单元，其被配置为生成噪声消除控制信号; 以及放大单元，其被配置为消除噪声并放大语音信号。

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