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11. 发明授权

US06633174B1 Stepper type test structures and methods for inspection of semiconductor integrated circuits 有权
标题翻译：步进式测试结构和半导体集成电路检测方法
公开(公告)号：US06633174B1
公开(公告)日：2003-10-14
申请号：US09648093
申请日：2000-08-25
申请人： Akella V. S. Satya , David L. Adler , Neil Richardson , Gustavo A. Pinto , David J. Walker
发明人： Akella V. S. Satya , David L. Adler , Neil Richardson , Gustavo A. Pinto , David J. Walker
IPC分类号： G01R31305
CPC分类号： G01R31/307 , G01N21/66 , G01N21/9501 , G01N21/956 , G01R31/2884 , H01J2237/2817 , H01L22/12 , H01L22/34 , Y10S977/85 , Y10S977/86 , Y10S977/881
摘要： Disclosed is a method of inspecting a sample. The method includes moving to a first field associated with a first group of test structures. The first group of test structures are partially within the first field. The method further includes scanning the first field to determine whether there are any defects present within the first group of test structures. When it is determined that there are defects within the first group of test structures, the method further includes repeatedly stepping to areas and scanning such areas so as to determine a specific defect location within the first group of test structures. A suitable test structure for performing this method is also disclosed.
摘要翻译：公开了一种检查样品的方法。该方法包括移动到与第一组测试结构相关联的第一字段。第一组测试结构部分在第一个领域内。该方法还包括扫描第一场以确定在第一组测试结构内是否存在任何缺陷。当确定在第一组测试结构内存在缺陷时，该方法还包括重复地步进到区域并扫描这些区域，以便确定第一组测试结构内的特定缺陷位置。还公开了用于执行该方法的合适的测试结构。

12. 发明授权

US06576923B2 Inspectable buried test structures and methods for inspecting the same 有权
公开(公告)号：US06576923B2
公开(公告)日：2003-06-10
申请号：US10178329
申请日：2002-06-21
申请人： Akella V. S. Satya , Robert Thomas Long , Lynda C. Mantalas , Gustavo A. Pinto , Neil Richardson
发明人： Akella V. S. Satya , Robert Thomas Long , Lynda C. Mantalas , Gustavo A. Pinto , Neil Richardson
IPC分类号： H01L2358
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S977/712 , Y10S977/723 , Y10S977/888 , Y10S977/89 , H01L2924/00
摘要： Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element. Methods for inspecting and fabricating such semiconductor die are also disclosed.

13. 发明授权

US06509197B1 Inspectable buried test structures and methods for inspecting the same 有权
公开(公告)号：US06509197B1
公开(公告)日：2003-01-21
申请号：US09648212
申请日：2000-08-25
申请人： Akella V. S. Satya , Robert Thomas Long , Lynda C. Mantalas , Gustavo A. Pinto , Neil Richardson
发明人： Akella V. S. Satya , Robert Thomas Long , Lynda C. Mantalas , Gustavo A. Pinto , Neil Richardson
IPC分类号： H01L2100
CPC分类号： H01L22/34 , G01N21/66 , G01N21/956 , G01R31/2884 , G01R31/307 , H01J2237/2817 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor die having a lower test structure formed in a lower metal layer of the semiconductor die. The lower conductive test structure has a first end and a second end. The first end is coupled to a predetermined voltage level. The semiconductor die also includes an insulating layer formed over the lower metal layer. The die further includes an upper test structure formed in an upper metal layer of the semiconductor die. The upper conductive test structure is coupled with the second end of the lower conductive test structure. The upper metal layer is formed over the insulating layer. In a specific implementation, the first end of the lower test structure is coupled to ground. In another embodiment, the semiconductor die also includes a substrate and a first via coupled between the first end of the lower test structure and the substrate. In yet another aspect, the lower test structure is an extended metal line, and the upper test structure is a voltage contrast element. Methods for inspecting and fabricating such semiconductor die are also disclosed.

14. 发明申请

US20070267631A1 System and Method for Increasing Productivity of Combinatorial Screening 有权
标题翻译：提高组合筛选生产力的系统和方法
公开(公告)号：US20070267631A1
公开(公告)日：2007-11-22
申请号：US11419174
申请日：2006-05-18
申请人： Kurt H. Weiner , Tony P. Chiang , Gustavo A. Pinto
发明人： Kurt H. Weiner , Tony P. Chiang , Gustavo A. Pinto
IPC分类号： H01L23/58
CPC分类号： H01L22/10 , H01L21/67005 , H01L22/34
摘要： The present invention provides systems and methods for simultaneous, parallel and/or rapid serial testing of material parameters or other parameters of the result of a process. The testing is typically used for screening different methods or materials to select those methods or materials with desired properties. A reactor structure used to form the materials may consist of an array of small isolated reaction chambers that overlie the substrate so that the substrate forms a bottom surface of each isolated reaction chamber. Test structures are formed on the substrate, where the location of each test structure corresponds to an isolated reaction chamber area of the reaction structure. Test structures are used to measure certain parameters, such as by probing contact pads for each test structure, or such testing may be performed in-situ during processing.
摘要翻译：本发明提供用于同时，并行和/或快速连续测试材料参数或过程结果的其它参数的系统和方法。测试通常用于筛选不同的方法或材料以选择具有所需性质的那些方法或材料。用于形成材料的反应器结构可以由覆盖在基板上的小的分离的反应室的阵列组成，使得基板形成每个分离的反应室的底表面。在基板上形成测试结构，其中每个测试结构的位置对应于反应结构的分离的反应室区域。测试结构用于测量某些参数，例如通过探测每个测试结构的接触垫，或者可以在处理期间原位进行这种测试。

15. 发明授权

US08772772B2 System and method for increasing productivity of combinatorial screening 有权
标题翻译：提高组合筛选生产力的系统和方法
公开(公告)号：US08772772B2
公开(公告)日：2014-07-08
申请号：US11419174
申请日：2006-05-18
申请人： Kurt H. Weiner , Tony P. Chiang , Gustavo A. Pinto
发明人： Kurt H. Weiner , Tony P. Chiang , Gustavo A. Pinto
IPC分类号： H01L23/58
CPC分类号： H01L22/10 , H01L21/67005 , H01L22/34
摘要： The present invention provides systems and methods for simultaneous, parallel and/or rapid serial testing of material parameters or other parameters of the result of a process. The testing is typically used for screening different methods or materials to select those methods or materials with desired properties. A reactor structure used to form the materials may consist of an array of small isolated reaction chambers that overlie the substrate so that the substrate forms a bottom surface of each isolated reaction chamber. Test structures are formed on the substrate, where the location of each test structure corresponds to an isolated reaction chamber area of the reaction structure. Test structures are used to measure certain parameters, such as by probing contact pads for each test structure, or such testing may be performed in-situ during processing.
摘要翻译：本发明提供用于同时，并行和/或快速连续测试材料参数或过程结果的其它参数的系统和方法。测试通常用于筛选不同的方法或材料以选择具有所需性质的那些方法或材料。用于形成材料的反应器结构可以由覆盖在基板上的小的分离的反应室的阵列组成，使得基板形成每个分离的反应室的底表面。在基板上形成测试结构，其中每个测试结构的位置对应于反应结构的分离的反应室区域。测试结构用于测量某些参数，例如通过探测每个测试结构的接触垫，或者可以在处理期间原位进行这种测试。

16. 发明授权

US07179661B1 Chemical mechanical polishing test structures and methods for inspecting the same 有权
标题翻译：化学机械抛光试验结构及检验方法
公开(公告)号：US07179661B1
公开(公告)日：2007-02-20
申请号：US09648095
申请日：2000-08-25
申请人： Akella V. S. Satya , Lynda C. Mantalas , Gustavo A. Pinto
发明人： Akella V. S. Satya , Lynda C. Mantalas , Gustavo A. Pinto
IPC分类号： H01L21/00
CPC分类号： H01L22/34
摘要： Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment, the semiconductor die also includes a plurality of conductive layers and a substrate. The underlying test structure includes a first layer portion formed from a first one of the plurality of conductive layer and a via coupling the first layer portion to the at least one dummy filling. In another aspect, the underlying test structure also has a via coupling the first layer portion to the substrate, and the underlying test structure comprises a plurality of layer portions and vias to form a multilevel test structure.
摘要翻译：公开了一种具有多个虚拟填料的半导体管芯，其中所述多个虚拟填料的位置和尺寸被设计成使化学机械抛光期间的缺陷最小化。虚拟填充物中的至少一个耦合到底层测试结构。在优选实施例中，半导体管芯还包括多个导电层和衬底。下面的测试结构包括由多个导电层中的第一个形成的第一层部分和将第一层部分连接到至少一个虚拟填充物的通孔。在另一方面，基础测试结构还具有将第一层部分耦合到衬底的通孔，并且底层测试结构包括多个层部分和通孔以形成多层测试结构。

17. 发明授权

US07655482B2 Chemical mechanical polishing test structures and methods for inspecting the same 有权
标题翻译：化学机械抛光试验结构及检验方法
公开(公告)号：US07655482B2
公开(公告)日：2010-02-02
申请号：US11621512
申请日：2007-01-09
申请人： Akella V. S. Satya , Lynda C. Mantalas , Gustavo A. Pinto
发明人： Akella V. S. Satya , Lynda C. Mantalas , Gustavo A. Pinto
IPC分类号： H01L21/00
CPC分类号： H01L23/5226 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor die having a plurality of dummy fillings positioned and sized to minimize defects during chemical mechanical polishing is disclosed. At least one of the dummy fillings is coupled to an underlying test structure. In a preferred embodiment, the semiconductor die also includes a plurality of conductive layers and a substrate. The underlying test structure includes a first layer portion formed from a first one of the plurality of conductive layer and a via coupling the first layer portion to the at least one dummy filling. In another aspect, the underlying test structure also has a via coupling the first layer portion to the substrate, and the underlying test structure comprises a plurality of layer portions and vias to form a multilevel test structure.
摘要翻译：公开了一种具有多个虚拟填料的半导体管芯，其中所述多个虚拟填料的位置和尺寸被设计成使化学机械抛光期间的缺陷最小化。虚拟填充物中的至少一个耦合到底层测试结构。在优选实施例中，半导体管芯还包括多个导电层和衬底。下面的测试结构包括由多个导电层中的第一个形成的第一层部分和将第一层部分连接到至少一个虚拟填充物的通孔。在另一方面，基础测试结构还具有将第一层部分耦合到衬底的通孔，并且底层测试结构包括多个层部分和通孔以形成多层测试结构。

18. 发明授权

US06977791B2 Media servowriting system 失效
标题翻译：媒体伺服系统
公开(公告)号：US06977791B2
公开(公告)日：2005-12-20
申请号：US10395051
申请日：2003-03-22
申请人： Jun Zhu , Alex Moraru , Teodor Zanetti , Franklin Tao , Dan L. Kilmer , Harald Hess , Tom Carr , Matt Bellis , Gustavo A. Pinto , Patrick Rodney Lee
发明人： Jun Zhu , Alex Moraru , Teodor Zanetti , Franklin Tao , Dan L. Kilmer , Harald Hess , Tom Carr , Matt Bellis , Gustavo A. Pinto , Patrick Rodney Lee
IPC分类号： G11B5/596 , G11B21/02
CPC分类号： G11B5/59633
摘要： A system and methods for efficiently performing media writing functions is disclosed. The system and methods include: detecting media movement with respect to a base and heads during reading and writing, and moving the heads in response; using an interferometer, such as a dual beam differential interferometer, to dynamically monitor disk position and address perceived errors; and minimizing repeatable and non repeatable runout error by writing data, such as servo bursts, in multiple revolutions to average adverse runout conditions. The present system has the ability to use an interferometer to enhance media certification and perform on line, in situ monitoring of the media, and includes shrouding, head mounting, disk biasing, and related mechanical aspects beneficial to media writing.
摘要翻译：公开了一种用于有效执行媒体写入功能的系统和方法。该系统和方法包括：在读取和写入期间相对于基座和头部检测媒体移动，并且响应地移动头部; 使用诸如双光束差分干涉仪的干涉仪来动态地监测磁盘位置并解决感知到的错误; 并通过以多次旋转将数据（例如伺服脉冲串）写入平均不利的跳动条件来最小化可重复和不可重复的跳动误差。本系统能够使用干涉仪来增强媒体认证，并在线进行现场监控媒体，并且包括遮蔽，头部安装，磁盘偏置以及有利于媒体写作的相关机械方面。

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