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11. 发明授权

US08743973B2 Receiver resistor network for common-mode signaling 失效
标题翻译：用于共模信号的接收电阻网络
公开(公告)号：US08743973B2
公开(公告)日：2014-06-03
申请号：US13115838
申请日：2011-05-25
申请人： Lei Luo , Brian S. Leibowitz , Jared L. Zerbe , Barry W. Daly , Wayne D. Dettloff , John C. Eble, III , John Wilson
发明人： Lei Luo , Brian S. Leibowitz , Jared L. Zerbe , Barry W. Daly , Wayne D. Dettloff , John C. Eble, III , John Wilson
IPC分类号： H04B3/00 , H04L25/00
CPC分类号： H04L5/20
摘要： A receiver circuit to receive signals from first and second pairs of transmission lines includes first and second interfaces, each with first and second input nodes to receive respective signals. The receiver circuit also includes a resistor network with first, second, third, and fourth resistive elements. The first and second resistive elements are each connected between the input nodes of a respective interface. The third and fourth resistive elements each include a pair of resistors connected in series between the input nodes of a respective interface, and an intermediate node between the resistors. The intermediate nodes are connected to an AC ground. The receiver circuit further includes a differential amplifier with first and second inputs coupled respectively to the first and second interfaces and an output to provide a signal derived from common mode components of the signals received at the input nodes.
摘要翻译：接收来自第一和第二对传输线的信号的接收机电路包括第一和第二接口，每个具有第一和第二输入节点以接收相应的信号。接收器电路还包括具有第一，第二，第三和第四电阻元件的电阻器网络。第一和第二电阻元件各自连接在相应接口的输入节点之间。第三和第四电阻元件各自包括串联连接在相应接口的输入节点和电阻器之间的中间节点的一对电阻器。中间节点连接到交流接地。接收器电路还包括差分放大器，其具有分别耦合到第一和第二接口的第一和第二输入以及输出，以提供从在输入节点处接收的信号的共模分量得到的信号。

12. 发明申请

US20140143687A1 Computer Peripheral Display and Communication Device Providing an Adjunct 3d User Interface 有权
标题翻译：计算机外围显示和通信设备提供一个辅助的3d用户界面
公开(公告)号：US20140143687A1
公开(公告)日：2014-05-22
申请号：US14009610
申请日：2011-04-13
申请人： Min-Liang Tan , John Wilson , Patrick Hahn
发明人： Min-Liang Tan , John Wilson , Patrick Hahn
IPC分类号： G06F3/0481 , A63F13/00 , H04L12/58
CPC分类号： G06F3/0481 , A63F13/00 , G06F3/04815 , G06F3/1462 , G09G2370/022 , H04L51/04
摘要： A system for providing a visual user environment includes a processing unit, a memory, a primary display device for providing a primary visual interface, and an adjunct communication device for providing an adjunct visual interface. In an embodiment, the adjunct display device is configured to present quasi-3D or 3D images. A process can include detecting an adjunct content event corresponding to adjunct visual content associated with an aspect of an application program; and selectively transferring one of an adjunct content notification and adjunct visual content to the adjunct communication device, wherein the adjunct content event corresponds to one of an application program installation sequence, an application program event, an indication of user proficiency in interacting with the application program, a communication session with a remote system, and a predefined visual sequence that is automatically selected for presentation to the user during one of application program installation and application program execution.
摘要翻译：一种用于提供视觉用户环境的系统包括处理单元，存储器，用于提供主视觉界面的主显示设备，以及用于提供辅助视觉界面的辅助通信设备。在一个实施例中，辅助显示设备被配置为呈现准3D或3D图像。过程可以包括检测与应用程序的方面相关联的附加视觉内容相对应的附加内容事件; 以及选择性地将附加内容通知和辅助视觉内容中的一个附加到所述辅助通信设备，其中所述附加内容事件对应于应用程序安装顺序，应用程序事件，与所述应用程序交互的用户熟练程度的指示，与远程系统的通信会话，以及在应用程序安装和应用程序执行期间被自动选择以呈现给用户的预定义的视觉序列。

13. 发明申请

US20130249612A1 METHOD AND APPARATUS FOR SOURCE-SYNCHRONOUS SIGNALING 有权
标题翻译：用于同源信号的方法和装置
公开(公告)号：US20130249612A1
公开(公告)日：2013-09-26
申请号：US13523631
申请日：2012-06-14
申请人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
发明人： Jared L. Zerbe , Brian S. Leibowitz , Hsuan-Jung Su , John Cronan Eble, III , Barry William Daly , Lei Luo , Teva J. Stone , John Wilson , Jihong Ren , Wayne D. Dettloff
IPC分类号： H03L7/00
CPC分类号： H03L7/091 , G11C7/04 , G11C7/1066 , G11C7/1093 , G11C7/222 , H03L7/00 , H03L7/0802 , H03L7/099 , H04L7/0008 , H04L7/0037 , H04L7/0079 , H04L7/0087 , H04L7/033
摘要： A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.
摘要翻译：在各种实施例中描述了低功率，高性能的源同步芯片接口，其提供快速开启并且促进位于不同芯片上的发射机和接收机之间的高信令速率。芯片接口的一些实施例包括：分段的“快速接通”偏置电路，以减少快速上电过程期间的电源振铃; 电流模式逻辑时钟缓冲器在芯片接口的时钟路径中进一步降低电源振铃的影响; 乘法注入锁定振荡器（MILO）时钟发生器，用于从参考时钟产生更高频率的时钟信号; 一个数字控制延时线，可以插入到时钟通路中，以减轻由MILO时钟发生器引起的确定性抖动; 以及用于周期性地重新评估是否安全地重新计算参考时钟域中的数据信号的电路直接用较快的时钟信号。

14. 发明申请

US20130212078A1 Detecting and Combating Attack In Protection System of an Industrial Control System 有权
公开(公告)号：US20130212078A1
公开(公告)日：2013-08-15
申请号：US13370389
申请日：2012-02-10
申请人： John Wilson
发明人： John Wilson
IPC分类号： G06F17/30
CPC分类号： H04L63/1416
摘要： A method for detecting and combating an attack in an industrial control system includes sending a command stream from a protection network of an industrial control system to at least one zone, the command stream comprising at least one command; concatenating the at least one command into at least one sequential command package comprising units or work; passing the at least one sequential command package to a crypto hash generator; generating at least one of unit of work hash codes or sequence hash codes; comparing the generated hash codes against a database of existing valid unit of work hash codes and sequence hash codes; and if a command stream fault is detected, generating an alert and accessing a database comprising emergency procedures.

15. 发明申请

US20130009686A1 Methods and Apparatus for Transmission of Data 有权
标题翻译：数据传输的方法和装置
公开(公告)号：US20130009686A1
公开(公告)日：2013-01-10
申请号：US13635028
申请日：2011-02-26
申请人： Michael Bucher , John Wilson
发明人： Michael Bucher , John Wilson
IPC分类号： H03H11/16
CPC分类号： G11C7/1051 , G06F1/0342 , G06F1/04 , G06F1/06 , G06F13/38 , G06F13/4243 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/1093 , H04B3/32 , H04L7/0008 , H04L25/026 , H04L25/0264
摘要： A system includes a transmitter circuit and a receiver circuit that are coupled together through transmission lines. The transmitter circuit generates an early timing signal, a nominal timing signal, and a late timing signal. A multiplexer circuit selects between the early and the late timing signals based on a data signal to generate an encoded output signal that encodes the data signal. The nominal timing signal and the encoded output signal are transmitted through the transmission lines to the receiver circuit. The receiver circuit samples the encoded output signal in response to the nominal timing signal to generate even and odd sampled data signals. Complementary timing signals can be transmitted through transmission lines on opposite sides of the encoded output signal to provide crosstalk cancellation.
摘要翻译：一种系统包括通过传输线耦合在一起的发射机电路和接收机电路。发射机电路产生早期定时信号，标称定时信号和延迟定时信号。多路复用器电路基于数据信号在早期和晚期定时信号之间进行选择，以产生对数据信号进行编码的编码输出信号。标称定时信号和编码的输出信号通过传输线传输到接收器电路。接收器电路响应于标称定时信号对编码的输出信号进行采样，以产生偶数和奇数采样数据信号。互补定时信号可以通过编码输出信号相对侧的传输线传输，以提供串扰消除。

16. 发明授权

US08260278B2 Framework for agile mobile applications 有权
标题翻译：敏捷移动应用框架
公开(公告)号：US08260278B2
公开(公告)日：2012-09-04
申请号：US11790421
申请日：2007-04-25
申请人： Seth M. Landsman , Brandon T. Wolfe , Richard Byrne , John Wilson , Harry Sleeper , Juhan Sonin
发明人： Seth M. Landsman , Brandon T. Wolfe , Richard Byrne , John Wilson , Harry Sleeper , Juhan Sonin
IPC分类号： H04M3/00
CPC分类号： H04L67/12
摘要： A framework for enabling the usage of mobile devices in a remote sensing and reporting role are provided herein. Embodiments of the present invention provide methods and systems for enabling the usage of mobile devices in a remote sensing and reporting role. Embodiments of the present invention use existing mobile network infrastructure to engage mobile users in remote sensing and reporting tasks. Further, embodiments of the present invention enable rapid set up of remote sensing and reporting applications with relatively little technical skills.
摘要翻译：本文提供了一种用于使遥控和报告角色中的移动设备的使用的框架。本发明的实施例提供了用于使得能够在遥感和报告角色中使用移动设备的方法和系统。本发明的实施例使用现有的移动网络基础设施来使移动用户参与遥感和报告任务。此外，本发明的实施例能够以相对较少的技术技能快速建立遥感和报告应用。

17. 发明申请

US20120206280A1 Multiple Word Data Bus Inversion 有权
标题翻译：多字数据总线反转
公开(公告)号：US20120206280A1
公开(公告)日：2012-08-16
申请号：US13502474
申请日：2010-10-08
申请人： Aliazam Abbasfar , John Wilson
发明人： Aliazam Abbasfar , John Wilson
IPC分类号： H03M7/34
CPC分类号： H04L25/4915 , G06F13/4072 , G06F13/4204 , G11C7/1006 , H04L25/0272
摘要： A data encoding scheme for transmission of data from one circuit to another circuit considers the Hamming Weight of combined multiple words to determine whether to invert or not invert an individual word to be transmitted. The multi-word data encoding scheme performs DBI encoding with data inversion conducted based on the total HW in the combined multiple words. The decision to invert or not invert each of the multiple words is made based on the sum of the individual Hamming Weights of each of the words. Such encoding has the advantage that SSO noise is dramatically reduced when the encoded data has a large number of words transmitted from one circuit to another circuit over a wide parallel bus.
摘要翻译：用于将数据从一个电路传输到另一电路的数据编码方案考虑组合的多个字的汉明权重来确定是否反转要发送的单个字。多字数据编码方案基于组合的多个字中的总HW执行数据反转来执行DBI编码。基于每个单词的个体汉明重量的总和，决定反转或不反转每个多个单词。这种编码的优点在于，当编码数据具有通过宽并行总线从一个电路发送到另一个电路的大量字时，SSO噪声显着降低。

18. 发明授权

US08198930B2 Reducing power-supply-induced jitter in a clock-distribution circuit 有权
标题翻译：降低时钟分配电路中的电源引起的抖动
公开(公告)号：US08198930B2
公开(公告)日：2012-06-12
申请号：US12913754
申请日：2010-10-27
申请人： Jared Zerbe , Brian Leibowitz , Lei Luo , John Wilson , Anshuman Bhuyan , Marko Aleksic
发明人： Jared Zerbe , Brian Leibowitz , Lei Luo , John Wilson , Anshuman Bhuyan , Marko Aleksic
IPC分类号： H03H11/26
CPC分类号： H03H11/265 , G06F1/10 , H03K5/1506 , H03K2005/00039 , H03K2005/0013 , H03K2217/0018
摘要： A system for compensating for power-supply-induced jitter (PSIJ) in a chain of clock buffers within an integrated circuit is described. During operation, the system couples a first supply voltage from a first voltage source to a supply node of each clock buffer in a first chain of clock buffers. Note that a change in the first supply voltage causes a change in a first propagation delay associated with the first chain of the clock buffers. The system also couples a second chain of clock buffers in series with the first chain of clock buffers. The system then couples the first voltage source to each clock buffer in the second chain of clock buffers through coupling circuitry. Next, the system adjusts the coupling circuitry so that the change in the first supply voltage from the first voltage source causes a change in a second propagation delay associated with the second chain of the clock buffers, wherein the change in the first propagation delay and the change in the second propagation delay are complementary.
摘要翻译：描述了用于补偿集成电路内的时钟缓冲器链中的电源诱发抖动（PSIJ）的系统。在操作期间，系统将第一电压源的第一电源电压耦合到第一时钟缓冲器链中的每个时钟缓冲器的电源节点。注意，第一电源电压的改变导致与时钟缓冲器的第一链相关联的第一传播延迟的改变。该系统还将第二链时钟缓冲器与第一链时钟缓冲器串联耦合。然后，系统通过耦合电路将第一电压源耦合到第二时钟缓冲器链中的每个时钟缓冲器。接下来，系统调整耦合电路，使得来自第一电压源的第一电源电压的变化引起与时钟缓冲器的第二链相关联的第二传播延迟的改变，其中第一传播延迟和第二传播延迟的变化是互补的。

19. 发明申请

US20110293041A1 Receiver Resistor Network for Common-Mode Signaling 失效
标题翻译：用于共模信号的接收器电阻网络
公开(公告)号：US20110293041A1
公开(公告)日：2011-12-01
申请号：US13115838
申请日：2011-05-25
申请人： Lei Luo , Brian S. Leibowitz , Jared L. Zerbe , Barry W. Daly , Wayne D. Dettloff , John C. Eble, III , John Wilson
发明人： Lei Luo , Brian S. Leibowitz , Jared L. Zerbe , Barry W. Daly , Wayne D. Dettloff , John C. Eble, III , John Wilson
IPC分类号： H04L27/00
CPC分类号： H04L5/20
摘要： A receiver circuit to receive signals from first and second pairs of transmission lines includes first and second interfaces, each with first and second input nodes to receive respective signals. The receiver circuit also includes a resistor network with first, second, third, and fourth resistive elements. The first and second resistive elements are each connected between the input nodes of a respective interface. The third and fourth resistive elements each include a pair of resistors connected in series between the input nodes of a respective interface, and an intermediate node between the resistors. The intermediate nodes are connected to an AC ground. The receiver circuit further includes a differential amplifier with first and second inputs coupled respectively to the first and second interfaces and an output to provide a signal derived from common mode components of the signals received at the input nodes.
摘要翻译：接收来自第一和第二对传输线的信号的接收机电路包括第一和第二接口，每个具有第一和第二输入节点以接收相应的信号。接收器电路还包括具有第一，第二，第三和第四电阻元件的电阻器网络。第一和第二电阻元件各自连接在相应接口的输入节点之间。第三和第四电阻元件各自包括串联连接在相应接口的输入节点和电阻器之间的中间节点的一对电阻器。中间节点连接到交流接地。接收器电路还包括差分放大器，其具有分别耦合到第一和第二接口的第一和第二输入端和输出端，以提供从在输入节点接收的信号的共模分量得到的信号。

20. 发明申请

US20110102043A1 REDUCING POWER-SUPPLY-INDUCED JITTER IN A CLOCK-DISTRIBUTION CIRCUIT 有权
标题翻译：在时钟分配电路中减少供电电感器
公开(公告)号：US20110102043A1
公开(公告)日：2011-05-05
申请号：US12913754
申请日：2010-10-27
申请人： Jared Zerbe , Brian Leibowitz , Lei Luo , John Wilson , Anshuman Bhuyan , Marko Aleksic
发明人： Jared Zerbe , Brian Leibowitz , Lei Luo , John Wilson , Anshuman Bhuyan , Marko Aleksic
IPC分类号： H03H11/26
CPC分类号： H03H11/265 , G06F1/10 , H03K5/1506 , H03K2005/00039 , H03K2005/0013 , H03K2217/0018
摘要： A system for compensating for power-supply-induced jitter (PSIJ) in a chain of clock buffers within an integrated circuit is described. During operation, the system couples a first supply voltage from a first voltage source to a supply node of each clock buffer in a first chain of clock buffers. Note that a change in the first supply voltage causes a change in a first propagation delay associated with the first chain of the clock buffers. The system also couples a second chain of clock buffers in series with the first chain of clock buffers. The system then couples the first voltage source to each clock buffer in the second chain of clock buffers through coupling circuitry. Next, the system adjusts the coupling circuitry so that the change in the first supply voltage from the first voltage source causes a change in a second propagation delay associated with the second chain of the clock buffers, wherein the change in the first propagation delay and the change in the second propagation delay are complementary.
摘要翻译：描述了用于补偿集成电路内的时钟缓冲器链中的电源诱发抖动（PSIJ）的系统。在操作期间，系统将第一电压源的第一电源电压耦合到第一时钟缓冲器链中的每个时钟缓冲器的电源节点。注意，第一电源电压的改变导致与时钟缓冲器的第一链相关联的第一传播延迟的改变。该系统还将第二链时钟缓冲器与第一链时钟缓冲器串联耦合。然后，系统通过耦合电路将第一电压源耦合到第二时钟缓冲器链中的每个时钟缓冲器。接下来，系统调整耦合电路，使得来自第一电压源的第一电源电压的变化引起与时钟缓冲器的第二链相关联的第二传播延迟的改变，其中第一传播延迟和第二传播延迟的变化是互补的。

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