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11. 发明申请

US20060023532A1 Method of operating a complementary bit resistance memory sensor 失效
标题翻译：操作互补位电阻存储器传感器的方法
公开(公告)号：US20060023532A1
公开(公告)日：2006-02-02
申请号：US11236562
申请日：2005-09-28
申请人： Glen Hush , Jake Baker
发明人： Glen Hush , Jake Baker
IPC分类号： G11C7/00
CPC分类号： G11C13/0011 , G11C7/062 , G11C11/16 , G11C13/004 , G11C2013/0042 , G11C2213/79
摘要： A method and apparatus is disclosed for sensing the resistance state of a Programmable Conductor Random Access Memory (PCRAM) element using complementary PCRAM elements, one holding the resistance state being sensed and the other holding a complementary resistance state. A sense amplifier detects voltages discharging through the high and low resistance elements to determine the resistance state of an element being read.
摘要翻译：公开了一种用于使用互补PCRAM元件感测可编程导体随机存取存储器（PCRAM）元件的电阻状态的方法和装置，一个保持正在感测的电阻状态，另一个保持互补电阻状态。读出放大器检测通过高电阻和低电阻元件放电的电压，以确定被读取元件的电阻状态。

12. 发明授权

US5598156A Serial to parallel conversion with phase locked loop 失效
标题翻译：具有锁相环的串并转换
公开(公告)号：US5598156A
公开(公告)日：1997-01-28
申请号：US372412
申请日：1995-01-13
申请人： Glen Hush , Jake Baker , Tom Voshell
发明人： Glen Hush , Jake Baker , Tom Voshell
IPC分类号： H03L7/08 , H03M9/00 , H04L7/033 , H04L7/04 , H04L7/06 , H04L7/08 , H04N5/12
CPC分类号： H03M9/00 , H03L7/08 , H04N5/126 , H04L7/033 , H04L7/044 , H04L7/06
摘要： A serial to parallel conversion circuit uses a dynamic shift register in a phase locked loop for an index to access a parallel holding register. The composite input signal includes serial data to be sampled and a synchronizing signal at an integer factor of the sampling serial data rate. The phase locked loop generates a control signal for sampling the serial data at a multiple of the synchronizing frequency by incorporating a delay between a variable frequency oscillator output and a phase comparator input. The delay element in one embodiment includes a shift register with a walking-one pattern that overflows to the phase comparator. The walking-one pattern is used to identify which position of the holding register should store the next sample of the input signal. The shift register is self-initialized by a logic combination of all shift register outputs. Power dissipation by the serial to parallel conversion circuit is minimal because only one 7-transistor shift register cell draws current at a time.
摘要翻译：串行到并行转换电路在锁相环中使用动态移位寄存器用于访问并行保持寄存器的索引。复合输入信号包括要采样的串行数据和采样串行数据速率的整数因子的同步信号。锁相环产生一个控制信号，用于通过结合可变频率振荡器输出和相位比较器输入之间的延迟以同步频率的倍数对串行数据进行采样。一个实施例中的延迟元件包括移位寄存器，其具有溢出到相位比较器的步行模式。步行模式用于识别保持寄存器的哪个位置应存储输入信号的下一个采样。移位寄存器由所有移位寄存器输出的逻辑组合进行自初始化。串并转换电路的功耗最小，因为只有一个7晶体管移位寄存器单元一次抽出电流。

13. 发明申请

US20080225571A1 Complementary bit PCRAM sense amplifier and method of operation 失效
标题翻译：互补位PCRAM读出放大器及其操作方法
公开(公告)号：US20080225571A1
公开(公告)日：2008-09-18
申请号：US12073901
申请日：2008-03-11
申请人： Glen Hush , Jake Baker
发明人： Glen Hush , Jake Baker
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0011 , G11C7/062 , G11C11/16 , G11C13/004 , G11C2013/0042 , G11C2213/79
摘要： A method and apparatus is disclosed for sensing the resistance state of a Programmable Conductor Random Access Memory (PCRAM) element using complementary PCRAM elements, one holding the resistance state being sensed and the other holding a complementary resistance state. A sense amplifier detects voltages discharging through the high and low resistance elements to determine the resistance state of an element being read.
摘要翻译：公开了一种用于使用互补PCRAM元件感测可编程导体随机存取存储器（PCRAM）元件的电阻状态的方法和装置，一个保持正在感测的电阻状态，另一个保持互补电阻状态。读出放大器检测通过高电阻和低电阻元件放电的电压，以确定被读取元件的电阻状态。

14. 发明申请

US20050018509A1 Complementary bit resistance memory sensor and method of operation 失效
标题翻译：互补位电阻存储器传感器和操作方法
公开(公告)号：US20050018509A1
公开(公告)日：2005-01-27
申请号：US10866091
申请日：2004-06-14
申请人： Glen Hush , Jake Baker
发明人： Glen Hush , Jake Baker
IPC分类号： G11C13/00 , G11C11/16 , G11C11/34 , G11C16/02 , H01L27/10 , H01L27/105 , H01L45/00 , G11C7/00
CPC分类号： G11C13/0011 , G11C7/062 , G11C11/16 , G11C13/004 , G11C2013/0042 , G11C2213/79
摘要： A method and apparatus are disclosed for sensing the resistance state of resistance-based memory element using complementary resistance-based elements, one holding the resistance state being sensed and the other holding a complementary resistance state. A sense amplifier detects voltages discharging through the high and low resistance elements to determine the resistance state of an element being read.
摘要翻译：公开了一种用于感测使用基于互补电阻的元件的电阻型存储元件的电阻状态的方法和装置，一种保持正在感测的电阻状态，另一种保持互补电阻状态。读出放大器检测通过高电阻和低电阻元件放电的电压，以确定被读取元件的电阻状态。

15. 发明申请

US20060099797A1 Integrated circuits with contemporaneously formed array electrodes and logic interconnects 审中-公开
标题翻译：具有同时形成的阵列电极和逻辑互连的集成电路
公开(公告)号：US20060099797A1
公开(公告)日：2006-05-11
申请号：US11315731
申请日：2005-12-22
申请人： Mirmajid Seyyedy , Glen Hush , Mark Tuttle , Terry Vollman
发明人： Mirmajid Seyyedy , Glen Hush , Mark Tuttle , Terry Vollman
IPC分类号： H01L21/4763 , H01L21/336 , H01L21/8242
CPC分类号： H01L27/228 , G11C5/06 , G11C11/14 , H01L27/105 , H01L27/10882 , H01L27/10897
摘要： The invention relates to interconnects for an integrated circuit memory device. Embodiments of the invention include processes to fabricate interconnects for memory devices in relatively few steps. Embodiments of the invention further include memory devices with metallization layers having unequal pitch dimensions in different areas of the chip, thereby permitting simultaneous fabrication of array electrodes and electrical interconnects in different areas of the chip. This reduces the number of fabrication steps used to make interconnects, thereby speeding up fabrication and reducing production costs.
摘要翻译：本发明涉及用于集成电路存储器件的互连。本发明的实施例包括以相对较少的步骤制造用于存储器件的互连的工艺。本发明的实施例还包括具有在芯片的不同区域中具有不等间距尺寸的金属化层的存储器件，从而允许在芯片的不同区域中同时制造阵列电极和电互连。这减少了用于制造互连的制造步骤的数量，从而加快制造并降低生产成本。

16. 发明申请

US20060083094A1 Method and apparatus for controlling refresh operations in a dynamic memory device 有权
公开(公告)号：US20060083094A1
公开(公告)日：2006-04-20
申请号：US11295856
申请日：2005-12-07
申请人： Manoj Sinha , Glen Hush
发明人： Manoj Sinha , Glen Hush
IPC分类号： G11C7/00
CPC分类号： G11C11/40626 , G11C11/406 , G11C2211/4061
摘要： A method and apparatus are provided for controlling refresh operations of a dynamic memory device. The temperature of the dynamic memory device is detected. The detected temperature is then used to adjust a refresh rate of the dynamic memory device to compensate for increased leakage at higher temperatures and more closely tailor the timing of the refresh operations to the conditions of the dynamic memory device.

17. 发明授权

US06954385B2 Method and apparatus for sensing resistive memory state 有权
标题翻译：用于感测电阻式存储器状态的方法和装置
公开(公告)号：US06954385B2
公开(公告)日：2005-10-11
申请号：US10918386
申请日：2004-08-16
申请人： Stephen L. Casper , Kevin Duesman , Glen Hush
发明人： Stephen L. Casper , Kevin Duesman , Glen Hush
IPC分类号： G11C13/00 , G11C11/34 , G11C13/02 , G11C16/28 , H01L27/105
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/0011 , G11C13/004 , G11C2013/0042 , G11C2013/0054 , G11C2013/009 , G11C2213/79
摘要： A sense circuit for reading a resistance level of a programmable conductor random access memory (PCRAM) cell is provided. A voltage potential difference is introduced across a PCRAM cell by activating an access transistor from a raised rowline voltage. Both a digit line and a digit complement reference line are precharged to a first predetermined voltage. The cell being sensed has the precharged voltage discharged through the resistance of the programmable conductor memory element of the PCRAM cell. A comparison is made of the voltage read at the digit line and at the reference conductor. If the voltage at the digit line is greater than the reference voltage, the cell is read as a high resistance value (e.g., logic HIGH); however, if the voltage measured at the digit line is lower than that of the reference voltage, the cell is read as a low resistance value (e.g., logic LOW).
摘要翻译：提供了用于读取可编程导体随机存取存储器（PCRAM）单元的电阻电平的读出电路。通过从升高的行线电压激活存取晶体管，通过PCRAM单元引入电压电位差。数字线和数位补码参考线都被预充电到第一预定电压。被感测的电池具有通过PCRAM单元的可编程导体存储元件的电阻放电的预充电电压。比较在数字线和参考导体读取的电压。如果数字线上的电压大于参考电压，则将单元读为高电阻值（例如，逻辑高电平）; 然而，如果在数字线处测量的电压低于参考电压的电压，则将该单元读为低电阻值（例如，逻辑低电平）。

18. 发明授权

US06873538B2 Programmable conductor random access memory and a method for writing thereto 有权
标题翻译：可编程导体随机存取存储器及其写入方法
公开(公告)号：US06873538B2
公开(公告)日：2005-03-29
申请号：US10022722
申请日：2001-12-20
申请人： Glen Hush
发明人： Glen Hush
IPC分类号： G11C13/00 , G11C7/12 , G11C11/34 , G11C13/02 , G11C16/10 , H01L27/105 , H01L45/00 , G11C11/00
CPC分类号： G11C13/0011 , G11C7/12 , G11C13/0026 , G11C13/0069 , G11C2013/009 , G11C2213/79
摘要： The present invention provides an improved write circuit and method for writing a programmable conductor random access memory (PCRAM) cell. The method comprises precharging a bit line to a first voltage and applying a second voltage to a first terminal of a chalcogenide memory element. A second terminal of the chalcogenide memory element is selectively coupled to the bit line to produce a voltage across the memory element sufficient to write a predetermined resistance state into the element. The first voltage may take on two different values to program two different resistance states into the memory element.
摘要翻译：本发明提供了一种用于写入可编程导体随机存取存储器（PCRAM）单元的改进的写入电路和方法。该方法包括将位线预充电到第一电压，并向硫族化物存储元件的第一端施加第二电压。硫族化物存储元件的第二端子被选择性地耦合到位线以产生跨过存储器元件的足以将预定电阻状态写入元件的电压。第一电压可以采取两个不同的值来将两个不同的电阻状态编程到存储器元件中。

19. 发明授权

US5703826A Video random access memory chip configured to transfer data in response to an internal write signal 失效
标题翻译：配置为响应于内部写入信号传送数据的视频随机存取存储器芯片
公开(公告)号：US5703826A
公开(公告)日：1997-12-30
申请号：US619285
申请日：1996-03-18
申请人： Glen Hush , Mike Seibert , Jeff Mailloux , Mark R. Thomann
发明人： Glen Hush , Mike Seibert , Jeff Mailloux , Mark R. Thomann
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C7/1006 , G11C7/1033 , G11C7/1075
摘要： The invention is a monolithic video random access memory (VRAM) chip that has more than one write control pin which is used to segment the VRAM into banks or sub-chips having four DQ planes such that a nibble of data can be written to the VRAM. Using the method of the invention a first bank may be written independently of a second bank, such that during a single memory cycle the first bank may be written and the second bank may be read. Using the circuit of the invention data is transferred in response to an internal write signal. The VRAM of the invention functions without the masking of a write to either bank. In addition the write memory function can be performed either through the random access memory port or through the serial access memory port.
摘要翻译：本发明是具有多于一个写入控制引脚的单片视频随机存取存储器（VRAM）芯片，其用于将VRAM分割成具有四个DQ平面的存储体或子芯片，使得可将数据的半字节写入VRAM 。使用本发明的方法，可以独立于第二组来写入第一存储体，使得在单个存储器周期期间可以写入第一存储体并且可以读取第二存储体。使用本发明的电路响应于内部写入信号传送数据。本发明的VRAM在不掩蔽任何一个存储体的写入的情况下起作用。此外，写入存储器功能可以通过随机存取存储器端口或通过串行存取存储器端口执行。

20. 发明授权

US08154004B2 Hybrid MRAM array structure and operation 有权
标题翻译：混合MRAM阵列结构和操作
公开(公告)号：US08154004B2
公开(公告)日：2012-04-10
申请号：US12614314
申请日：2009-11-06
申请人： Mirmajid Seyyedy , Glen Hush
发明人： Mirmajid Seyyedy , Glen Hush
IPC分类号： H01L45/00
CPC分类号： G11C11/1653 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C2213/71
摘要： This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.
摘要翻译：本发明涉及MRAM技术和MRAM阵列体系结构的新变型，其中包含了来自交叉点和1T-1MTJ架构的某些优点。通过组合这些布局的某些特性，可以利用1T-1MTJ架构的快速读取时间和更高的信噪比以及交叉点架构的更高的封装密度。单个访问晶体管16用于读取在“Z”轴方向上布置的多个MRAM阵列层中可以彼此垂直堆叠的列的段中的多个MRAM单元。

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