专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07333731B2 Multifunctional optoelectronic thyristor and integrated circuit and optical transceiver employing same 有权
标题翻译：多功能光电晶闸管和集成电路和采用相同的光收发器
公开(公告)号：US07333731B2
公开(公告)日：2008-02-19
申请号：US10832223
申请日：2004-04-26
申请人： Geoff W. Taylor , Rohinton Dehmubed
发明人： Geoff W. Taylor , Rohinton Dehmubed
IPC分类号： H04B10/00
CPC分类号： H01S5/06203 , H01S5/18319 , H01S5/18358 , H04B10/40
摘要： An integrated circuit (and optical transceiver module) includes an optoelectronic thyristor device formed within a resonant cavity on a substrate, and circuitry integrally formed on the substrate that dynamically switches the thyristor between a transmit mode configuration and a receive mode configuration. In the transmit mode configuration, the thyristor is modulated between a non-lasing state and a lasing state in accordance with an input digital electrical signal. In the receive mode configuration, the thyristor device is modulated between a non-lasing OFF state and a non-lasing ON state in accordance with an input digital optical signal that is injected into the resonant cavity to thereby produce an output digital electrical data signal that corresponds to the input digital optical signal. The integrated circuit (and optical transceiver module) can be used in optical fiber applications as well as free-space applications.
摘要翻译：集成电路（和光收发器模块）包括形成在衬底上的谐振腔内的光电晶闸管器件，以及一体地形成在衬底上的电路，其在发射模式配置和接收模式配置之间动态切换晶闸管。在发送模式配置中，晶闸管根据输入的数字电信号在非激光状态和激光状态之间进行调制。在接收模式配置中，晶闸管器件根据注入到谐振腔中的输入数字光信号在非激光关断状态和非激光导通状态之间进行调制，从而产生输出数字电数据信号，对应于输入数字光信号。集成电路（和光收发模块）可用于光纤应用以及自由空间应用。

12. 发明授权

US07176046B2 Apparatus and a method of fabricating inversion channel devices with precision gate doping for a monolithic integrated circuit 有权
标题翻译：用于单片集成电路的具有精密栅极掺杂的反向沟道器件的装置和方法
公开(公告)号：US07176046B2
公开(公告)日：2007-02-13
申请号：US11039559
申请日：2005-01-20
申请人： Geoff W. Taylor
发明人： Geoff W. Taylor
IPC分类号： H01L21/00
CPC分类号： H01S5/18372 , H01L29/2003 , H01L29/7785 , H01S5/0261 , H01S5/06203 , H01S5/06226 , H01S5/18308 , H01S5/18313 , H01S5/18341 , H01S5/18358 , H01S5/18369 , H01S5/3211 , H01S5/32341 , H01S5/32366
摘要： A family of high speed transistors and optoelectronic devices are obtained on a monolithic substrate by adding two sheets of planar doping together with a wideband cladding layer to the top of a pseudomorphic high electron mobility transistor (PHEMT) structure. The two sheets are of the same polarity which is opposite to the modulation doping of the PHEMT and they are separated by a lightly doped layer of specific thickness. The combination is separated from the PHEMT modulation doping by a specific thickness of undoped material. The charge sheets are thin and highly doped. The top charge sheet achieves low gate contact resistance and the bottom charge sheet defines the capacitance of the field-effect transistor (FET) with respect to the modulation doping layer of the PHEMT. The structure produces a pnp bipolar transistor, enhancement and depletion type FETs, a vertical cavity surface emitting laser, and a resonant cavity detectors.β
摘要翻译：在单片基板上通过将两片平面掺杂与宽带覆层一起添加到伪晶高电子迁移率晶体管（PHEMT）结构的顶部，获得一系列高速晶体管和光电子器件。两片具有相同的极性，与PHEMT的调制掺杂相反，并且它们被特定厚度的轻掺杂层分离。该组合与未掺杂材料的特定厚度的PHEMT调制掺杂分离。充电片薄且高度掺杂。顶部充电片实现低栅极接触电阻，并且底部电荷表定义了相对于PHEMT的调制掺杂层的场效应晶体管（FET）的电容。该结构产生pnp双极晶体管，增强型和耗尽型FET，垂直腔表面发射激光器和谐振腔检测器

13. 发明授权

US07173293B2 Semiconductor devices employing at least one modulation doped quantum well structure and one or more etch stop layers for accurate contact formation 有权
标题翻译：采用至少一个调制掺杂量子阱结构和一个或多个蚀刻停止层的半导体器件用于精确的接触形成
公开(公告)号：US07173293B2
公开(公告)日：2007-02-06
申请号：US11044636
申请日：2005-01-10
申请人： Geoff W. Taylor , Scott W. Duncan
发明人： Geoff W. Taylor , Scott W. Duncan
IPC分类号： H01L29/06
CPC分类号： H01L29/66318 , H01L29/155 , H01L29/66462 , H01L29/7371 , H01L29/802 , H03K17/79 , H03M1/667 , H03M1/74 , H03M1/808
摘要： A semiconductor device includes a series of layers formed on a substrate, the layers including a first plurality of layers including an n-type ohmic contact layer, a p-type modulation doped quantum well structure, an n-type modulation doped quantum well structure, and a fourth plurality of layers including a p-type ohmic contact layer. Etch stop layers are used to form contacts to the n-type ohmic contact layer and contacts to the n-type modulation doped quantum well structure. Thin capping layers are also provided to protect certain layers from oxidation. Preferably, each such etch stop layer is made sufficiently thin to permit current tunneling therethrough during operation of optoelectronic/electronic devices realized from this structure (including heterojunction thyristor devices, n-channel HFET devices, p-channel HFET devices, p-type quantum-well-base bipolar transistor devices, and n-type quantum-well-base bipolar transistor devices).In another aspect of the present invention, a high performance bipolar transistor device is realized from this structure by implanting p-type ions in a interdigitization pattern that forms a plurality of p-type ion implant regions on both sides of the p-type modulation doped quantum well structure to a depth that penetrates the n-type ohmic contact layer. The interdigitization pattern of the p-type implants reduces capacitance between the p-type modulation doped quantum well structure and the n-type ohmic contact layer to enable higher frequency operation.
摘要翻译：半导体器件包括在衬底上形成的一系列层，所述层包括包括n型欧姆接触层，p型调制掺杂量子阱结构，n型调制掺杂量子阱结构的第一多个层，以及包括p型欧姆接触层的第四多个层。蚀刻停止层用于形成与n型欧姆接触层的接触并与n型调制掺杂量子阱结构接触。还提供薄盖层以保护某些层免于氧化。优选地，每个这样的蚀刻停止层被制成足够薄以允许在从该结构实现的光电子/电子器件的操作期间电流隧穿（包括异质结晶闸管器件，n沟道HFET器件，p沟道HFET器件，p型量子阱器件，基极双极晶体管器件和n型量子阱基双极晶体管器件）。在本发明的另一方面，通过将p型离子注入到在p型调制掺杂的两侧上形成多个p型离子注入区的叉指形式中，从该结构实现了高性能双极晶体管器件量子阱结构到穿透n型欧姆接触层的深度。 p型植入物的叉指形式降低p型调制掺杂量子阱结构和n型欧姆接触层之间的电容，以实现更高频率的操作。

14. 发明授权

US06954473B2 Optoelectronic device employing at least one semiconductor heterojunction thyristor for producing variable electrical/optical delay 有权
标题翻译：使用至少一个半导体异质结晶闸管产生可变电/光延迟的光电器件
公开(公告)号：US06954473B2
公开(公告)日：2005-10-11
申请号：US10280892
申请日：2002-10-25
申请人： Rohinton Dehmubed , Geoff W. Taylor , Daniel C. Upp , Jianhong Cai
发明人： Rohinton Dehmubed , Geoff W. Taylor , Daniel C. Upp , Jianhong Cai
IPC分类号： H01L21/331 , H01L21/335 , H01L29/15 , H01L29/80 , H03K17/79 , H03M1/66 , H03M1/74 , H03M1/80 , H01S3/10
CPC分类号： H01L29/66318 , H01L29/155 , H01L29/66462 , H01L29/802 , H03K17/79 , H03M1/667 , H03M1/74 , H03M1/808
摘要： An optoelectronic integrated circuit includes a resonant cavity formed on a substrate. A heterojunction thyristor device is formed in the resonant cavity and operates to detect an input optical pulse (or input electrical pulse) and produce an output optical pulse via laser emission in response to the detected input pulse. The heterojunction thyristor device includes a channel region that is coupled to a current source that draws current from the channel region. Time delay between the input pulse and output optical pulse may be varied by configuring the current source to draw constant current from the channel region and modulating the intensity of the input pulse, or by varying the amount of current drawn from the channel region by the current source. The heterojunction thyristor device may be formed from a multilayer structure of group III-V materials, or from a multilayer structure of strained silicon materials. A plurality of such heterojunction thyristor based optoelectronic integrated circuits can be used to provide variable pulse delay over a plurality of channels. In addition, the heterojunction thyristor device is easily integrated with other optoelectronic devices formed from the same growth structure to form monolithic optoelectronic integrated circuits suitable for many diverse applications, including phased array communication systems.
摘要翻译：光电集成电路包括形成在基板上的谐振腔。异相结晶闸管器件形成在谐振腔中，用于检测输入光脉冲（或输入电脉冲），并响应于检测到的输入脉冲通过激光发射产生输出光脉冲。异质结晶闸管器件包括耦合到电流源的沟道区，其从沟道区抽取电流。输入脉冲和输出光脉冲之间的时间延迟可以通过配置电流源来从通道区域抽取恒定电流并调制输入脉冲的强度，或者通过改变从通道区域引出的电流量来改变电流资源。异质结晶闸管器件可以由III-V族材料的多层结构或者由应变硅材料的多层结构形成。可以使用多个这样的异质结晶闸管的光电集成电路来在多个通道上提供可变的脉冲延迟。此外，异质结晶闸管器件容易与由相同生长结构形成的其它光电器件集成，以形成适用于许多不同应用的单片光电集成电路，包括相控阵通信系统。

15. 发明授权

US06853014B2 Optoelectronic circuit employing a heterojunction thyristor device that performs high speed sampling 有权
标题翻译：采用进行高速采样的异质结晶闸管器件的光电子电路
公开(公告)号：US06853014B2
公开(公告)日：2005-02-08
申请号：US10323390
申请日：2002-12-19
申请人： Geoff W. Taylor , Jianhong Cai
发明人： Geoff W. Taylor , Jianhong Cai
IPC分类号： H01L21/331 , H01L21/335 , H01L29/15 , H01L29/80 , H03K17/79 , H03M1/66 , H03M1/74 , H03M1/80 , H01L31/072
CPC分类号： H01L29/155 , H01L29/66318 , H01L29/66462 , H01L29/802 , H01L31/1113 , H03K17/79 , H03M1/667 , H03M1/74 , H03M1/808
摘要： An optoelectronic circuit employing a heterojunction thyristor device that is configured as an optically-controlled (or electrically-controlled) sampling/switching device. First and second channel regions are disposed between the anode terminal and the cathode terminal of the device, and an electrical input terminal and an electrical output terminal are coupled to opposite ends of the first channel region. At least one control signal is supplied to the device. When the control signal corresponds to a predetermined ON condition, sufficient charge is stored in the second channel region to cause the heterojunction thyristor device to operate in an ON state whereby current flows between the anode terminal and the cathode terminal and the electrical input terminal is electrically coupled to the electrical output terminal. When the control signal corresponds to a predetermined OFF condition, the heterojunction thyristor device operates in an OFF state whereby current does not flow between the anode terminal and the cathode terminal and the electrical input terminal is electrically isolated from the electrical output terminal. The control signal can be an optical sampling clock, a digital optical signal encoding bits of information, the combination of a digital optical signal and an optical sampling clock (which defines sampling periods that overlap the bits of information in the digital optical signal), or an electrical sampling clock.
摘要翻译：采用被配置为光控（或电控））采样/切换装置的异质结晶闸管器件的光电子电路。第一和第二通道区域设置在器件的阳极端子和阴极端子之间，并且电输入端子和电输出端子耦合到第一通道区域的相对端。至少一个控制信号被提供给设备。当控制信号对应于预定的ON状态时，在第二通道区域中存储足够的电荷，使得异质结晶闸管器件工作在导通状态，由此电流在阳极端子和阴极端子之间流动，并且电输入端子电耦合到电输出端子。当控制信号对应于预定的OFF状态时，异质结晶闸管器件工作在OFF状态，由此电流不在阳极端子和阴极端子之间流动，并且电气输入端子与电气输出端子电隔离。控制信号可以是光采样时钟，编码信息位的数字光信号，数字光信号和光采样时钟（其定义与数字光信号中的信息位重叠的采样周期）的组合，或电采样时钟。

16. 发明授权

US06479844B2 Modulation doped thyristor and complementary transistor combination for a monolithic optoelectronic integrated circuit 有权
标题翻译：用于单片光电集成电路的调制掺杂晶闸管和互补晶体管组合
公开(公告)号：US06479844B2
公开(公告)日：2002-11-12
申请号：US09798316
申请日：2001-03-02
申请人： Geoff W. Taylor
发明人： Geoff W. Taylor
IPC分类号： H01L310328
CPC分类号： B82Y20/00 , G02B6/28 , G02B6/2821 , G02F1/025 , H01L27/0605 , H01L29/165 , H01L29/205 , H01L29/66227 , H01L29/7371 , H01L29/74 , H01L29/7783 , H01L31/035236 , H01L31/10 , H01L31/1113
摘要： A family of high speed transistors and optoelectronic devices is obtained on a monolithic substrate with an epitaxial layer structure comprised of two modulation doped transistor structures, one inverted with respect to the other. The transistor structures are obtained by modification of the Pseudomorphic High Electron Mobility Transistor (PHEMT) structure and are combined in a unique way to create a thyristor structure. The thyristor structure may be used as a digital modulator, a transceiver, an amplifier and a directional coupler. These devices may be realized as either waveguide or vertical cavity devices. The vertical cavity construction enables resonant cavity operation of all device modes. In addition to the multiple optoelectronic properties, the structure also produces inversion channel bipolar devices termed BICFETs having either electrons or holes as the majority carrier and heterostructure FETs with both electron and hole channels. Therefore complementary operation of FET or bipolar circuits is possible.
摘要翻译：在具有外延层结构的单片衬底上获得一系列高速晶体管和光电子器件，该外延层结构由两个相对于另一个倒相的调制掺杂晶体管结构组成。晶体管结构是通过修改Pseudomorphic高电子迁移率晶体管（PHEMT）结构获得的，并以独特的方式组合以产生晶闸管结构。晶闸管结构可以用作数字调制器，收发器，放大器和定向耦合器。这些装置可以被实现为波导或垂直腔装置。垂直腔结构可实现所有器件模式的谐振腔操作。除了多个光电子性质之外，该结构还产生称为BICFET的反向通道双极器件，其具有电子或空穴作为多数载流子，并且具有电子和空穴通道的异质结构FET。因此，FET或双极电路的互补操作是可能的。

17. 发明授权

US12100930B2 Semiconductor integrated circuit and methodology for making same 有权
公开(公告)号：US12100930B2
公开(公告)日：2024-09-24
申请号：US18367992
申请日：2023-09-13
申请人： Geoff W. Taylor
发明人： Geoff W. Taylor
IPC分类号： H01S5/00 , H01S5/026 , H01S5/042 , H01S5/062 , H01S5/183 , H01S5/20
CPC分类号： H01S5/06203 , H01S5/026 , H01S5/0424 , H01S5/18308 , H01S5/18372 , H01S5/2027
摘要： Integrated circuitry is fabricated from semiconductor layers formed on a substrate, which include at least one n-type layer, an inverted p-type modulation doped quantum well (mod-doped QW) structure, a non-inverted n-type mod-doped QW structure, and at least one p-type layer including a first P+-type layer formed below a second P-type layer. An etch operation exposes the second p-type layer. P-type ions are implanted into the exposed second p-type layer. A gate electrode of a n-channel HFET device is formed in contact with the p-type ion implanted region. Source and drain electrodes of the n-channel HFET device are formed in contact with n-type ion implanted regions formed in contact with the n-type mod-doped QW structure. P-channel HFET devices, complementary BICFET devices, stacked complementary HFET devices and circuits and/or logic gates based thereon, and a variety of optoelectronic devices and optical devices can also be formed as part of the integrated circuitry.

18. 发明授权

US11799268B2 Semiconductor integrated circuit and methodology for making same 有权
公开(公告)号：US11799268B2
公开(公告)日：2023-10-24
申请号：US17408424
申请日：2021-08-21
申请人： Geoff W. Taylor
发明人： Geoff W. Taylor
IPC分类号： H01S5/00 , H01S5/062 , H01S5/20 , H01S5/183 , H01S5/042 , H01S5/026
CPC分类号： H01S5/06203 , H01S5/026 , H01S5/0424 , H01S5/18308 , H01S5/18372 , H01S5/2027
摘要： Integrated circuitry is fabricated from semiconductor layers formed on a substrate, which include at least one n-type layer, an inverted p-type modulation doped quantum well (mod-doped QW) structure, a non-inverted n-type mod-doped QW structure, and at least one p-type layer including a first P+-type layer formed below a second P-type layer. An etch operation exposes the second p-type layer. P-type ions are implanted into the exposed second p-type layer. A gate electrode of a n-channel HFET device is formed in contact with the p-type ion implanted region. Source and drain electrodes of the n-channel HFET device are formed in contact with n-type ion implanted regions formed in contact with the n-type mod-doped QW structure. P-channel HFET devices, complementary BICFET devices, stacked complementary HFET devices and circuits and/or logic gates based thereon, and a variety of optoelectronic devices and optical devices can also be formed as part of the integrated circuitry.

19. 发明公开

US20230317819A1 SEMICONDUCTOR OPTOELECTRONIC INTEGRATED CIRCUIT AND METHODOLOGY FOR MAKING SAME EMPLOYING GATE-ALL-AROUND EPITAXIAL STRUCTURES 审中-公开
公开(公告)号：US20230317819A1
公开(公告)日：2023-10-05
申请号：US18124876
申请日：2023-03-22
申请人： Geoff W. Taylor
发明人： Geoff W. Taylor
IPC分类号： H01L29/66 , H01S5/183 , H01S5/062 , H01L29/423 , H01L29/06 , H01L31/0352 , H01L29/775 , H01L29/786 , G02B6/12 , G02B6/13 , H01L27/06
CPC分类号： H01L29/66462 , H01S5/18377 , H01S5/06203 , H01L29/42392 , H01L29/0673 , H01L31/035236 , H01L29/775 , H01L29/66439 , H01L29/78696 , G02B6/12007 , G02B6/131 , H01L27/0605 , G02B2006/1215
摘要： Integrated circuitry is fabricated from semiconductor layers formed on a substrate, which include a p-type gate-all-around layer structure that includes a plurality of quantum well structures formed between a pair of p-type thin doped layers spaced vertically from one another. A p-type layer is formed above the p-type gate-all-around layer structure. An etch operation exposes the p-type layer. P-type ions are implanted into the exposed second p-type layer to a depth that extends through the p-type gate-all-around layer structure and contacts the p-type thin doped layers of the p-type gate-all-around layer structure. A gate electrode of an n-channel HFET device is formed in contact with the ion-implanted p-type region(s). Source and drain electrodes of the n-channel HFET device are formed in contact with ion-implanted n-type regions that contact the plurality of quantum well structures of the p-type gate-all-around layer structure. P-channel GAA HFET devices, complementary BICFET devices, stacked complementary HFET devices and circuits and/or logic gates based thereon, and a variety of optoelectronic devices and optical devices can also be formed as part of the integrated circuitry.

20. 发明申请

US20150316723A1 Fiber Optic Coupler Array 有权
标题翻译：光纤耦合器阵列
公开(公告)号：US20150316723A1
公开(公告)日：2015-11-05
申请号：US14104230
申请日：2013-12-12
申请人： Geoff W. Taylor , Yan Zhang
发明人： Geoff W. Taylor , Yan Zhang
IPC分类号： G02B6/30 , G02F1/017 , G02B6/14 , G02B6/122 , G02B6/12
CPC分类号： G02B6/305 , G02B6/1228 , G02B6/14 , G02B6/421 , G02B6/423 , G02B6/4249 , G02B6/4257
摘要： An assembly includes optical fibers each having a waveguide core, a photonic integrated circuit (IC) that includes in-plane waveguides corresponding to the optical fibers, and a substrate bonded to the photonic IC with grooves that support the optical fibers. The substrate and photonic IC can have metal bumps that cooperate to provide mechanical bonding and electrical connections between the substrate and photonic IC. Portions of the optical fibers supported by the substrate grooves can define flat surfaces spaced from the optical fiber cores. The photonic IC can include passive waveguide structures with a first coupling section that interfaces to the flat surface of a corresponding optical fiber (for evanescent coupling of optical signals) and a second coupling section that interfaces to a corresponding in-plane waveguide (for adiabatic spot-size conversion of optical signals).
摘要翻译：一种组件包括各自具有波导芯的光纤，包括对应于光纤的面内波导的光子集成电路（IC）以及与支撑光纤的凹槽连接到光子IC的基板。衬底和光子IC可以具有金属凸块，其配合以在衬底和光子IC之间提供机械结合和电连接。由基板槽支撑的光纤的一部分可以限定与光纤芯间隔开的平坦表面。光子IC可以包括无源波导结构，其具有与对应光纤的平坦表面（用于光信号的渐逝耦合）相接合的第一耦合部分和与对应的平面波导（用于绝热光点）相连接的第二耦合部分光信号的尺寸转换）。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式