专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US06813181B1 Circuit configuration for a current switch of a bit/word line of a MRAM device 失效
标题翻译： MRAM器件的位/字线的电流开关的电路配置
公开(公告)号：US06813181B1
公开(公告)日：2004-11-02
申请号：US10445550
申请日：2003-05-27
申请人： Hans Viehmann , John K. DeBrosse
发明人： Hans Viehmann , John K. DeBrosse
IPC分类号： G11C1140
CPC分类号： G11C11/16 , G11C7/12 , G11C8/08
摘要： A circuit configuration for a current switch of a bit line or a word line of a magnetoresistive random access memory (MRAM) device, comprising a directional switch and a voltage driver that, in operation, reduces the ON resistance of the directional switch. In one embodiment, each terminal of the line is provided with such a switch.
摘要翻译：一种用于磁阻随机存取存储器（MRAM）器件的位线或字线的电流开关的电路配置，包括定向开关和电压驱动器，其在操作中降低了方向开关的导通电阻。在一个实施例中，线路的每个终端设置有这样的开关。

12. 发明授权

US06282113B1 Four F-squared gapless dual layer bitline DRAM array architecture 有权
标题翻译：四个F平方无间隙双层位线DRAM阵列架构
公开(公告)号：US06282113B1
公开(公告)日：2001-08-28
申请号：US09408349
申请日：1999-09-29
申请人： John K. DeBrosse
发明人： John K. DeBrosse
IPC分类号： G11C506
CPC分类号： G11C5/063 , G11C7/18 , G11C11/4097 , Y10S257/907
摘要： A semiconductor device having a compact folded bitline architecture. Bitlines for a memory cell array arranged into bitline pairs constituting, when in use, a selected bitline and its complement. The selected bitline and its complement are adjacent in upper and lower levels, and exchange levels at selected breakpoints in the lower level bitline. The breakpoints are determined so as to establish a diagonally-oriented pattern of “twist regions” across the array. Adjacent bitline pairs exchange levels in alternating twist regions. The upper bitlines are positioned at a predetermined angle, relative to the lower bitlines, in selected intervals between the twist regions. The predetermined angle introduces an offset between the upper bitlines and their associated complement lower bitlines as the upper bitlines enter twist regions to exchange levels. The diagonal orientation of the twist regions, alternating pattern of breakpoints, and offsets eliminate gaps in the memory array which would otherwise be introduced in the twist regions, providing for enhanced cell density and a minimum cell area of approximately 4F2.
摘要翻译：具有紧凑折叠位线架构的半导体器件。存储单元阵列的位线布置成位线对，在使用时构成选定的位线及其补码。所选择的位线及其补码在上下位置相邻，并且在较低级别位线中的选定断点处的交换水平。确定断点以便在整个阵列中建立“扭转区域”的对角线定向图案。相邻的位线对交替扭转区域交换水平。在扭转区域之间以选定的间隔相对于下位线将上位线定位在预定角度。当上位线进入扭转区域以交换电平时，预定角度在上位线及其相关联的补码下位线之间引入偏移。扭转区域的对角方向，断点的交替模式和偏移量消除了存储器阵列中的间隙，否则将在引导区域中引入，从而提供增强的单元密度和约4F2的最小单元面积。

13. 发明授权

US5610867A DRAM signal margin test method 失效
标题翻译： DRAM信号余量测试方法
公开(公告)号：US5610867A
公开(公告)日：1997-03-11
申请号：US535446
申请日：1995-09-28
申请人： John K. DeBrosse , Toshiaki Kirihata , Hing Wong
发明人： John K. DeBrosse , Toshiaki Kirihata , Hing Wong
IPC分类号： G11C11/401 , G11C11/409 , G11C11/4091 , G11C29/50 , G11C7/00 , G11C29/00
CPC分类号： G11C11/4091 , G11C29/50 , G06F2201/81 , G11C11/401
摘要： In the Preferred embodiment of the present invention, a bit line pair is coupled through a pair of high-resistance pass gates to a sense amp. During sense, the high-resistance pass gates act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp. A control circuit selectively switches on and off bit line equalization coincident with selectively passing either the equalization voltage or set voltages to the sense amp and an active sense amp load. Further, after it is set, the sense amp is selectively connected to LDLs through low-resistance column select pass gates. Therefore, the sense amp quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp to a second sense amplifier and off chip. After data is passed to the LDLs, the control circuit enables the active sense amp load to pull the sense amp high side to a full up level. Additionally, because the control circuit uses the equalization voltage to disable the sense amp, cell signal margin may be tested in a new way. Instead of varying the sense amp reference voltage, as in prior art signal margin tests, cell signal margin is tested by varying cell signal. V.sub.S may be selected to determine both a high and a low signal margin.
摘要翻译：在本发明的优选实施例中，位线对通过一对高电阻通过门耦合到感测放大器。在感测期间，高电阻通过门与存储在位线对上的电荷一起作为有效地用于感测放大器的高电阻无源负载。控制电路选择性地接通和断开位线均衡，与选择性地将均衡电压或设定电压通过感测放大器和主动感测放大器负载相一致。此外，在设置之后，感测放大器通过低电阻列选择通孔选择性地连接到LDL。因此，当位线电压基本保持不变时，感测放大器会快速放电连接的LDL对之一。因此，数据从感测放大器传递到第二读出放大器和芯片外。数据传送到LDL后，控制电路使主动感测放大器负载将感测放大器的高端拉到一个完整的电平。此外，由于控制电路使用均衡电压来禁用读出放大器，所以可以以新的方式测试单元信号余量。代替检测放大器参考电压，如现有技术的信号余量测试，通过改变单元信号来测试单元信号余量。可以选择VS来确定高和低信号余量。

14. 发明授权

US4873205A Method for providing silicide bridge contact between silicon regions separated by a thin dielectric 失效
标题翻译：在由薄电介质隔开的硅区域之间提供硅化物桥接触的方法
公开(公告)号：US4873205A
公开(公告)日：1989-10-10
申请号：US240421
申请日：1988-09-01
申请人： Dale L. Critchlow , John K. DeBrosse , Rick L. Mohler , Wendell P. Noble, Jr. , Paul C. Parries
发明人： Dale L. Critchlow , John K. DeBrosse , Rick L. Mohler , Wendell P. Noble, Jr. , Paul C. Parries
IPC分类号： H01L21/74 , H01L21/8242
CPC分类号： H01L27/10861 , H01L21/743 , Y10S148/025 , Y10S148/026
摘要： A method for forming a silicide bridge bewteen a diffusion region and an adjacent poly-filled trench separated by a thin dielectric. Silicon is selectively grown over exposed silicon regions under conditions that provide controlled lateral growth over the thin dielectric without also permitting lateral growth over other insulator regions. A refractory metal layer is then deposited and sintered under conditions that limit lateral silicide growth, forming the bridge. This process avoids the random fails produced by previous processes while enhancing the compatibility of bridge formation with shallow junctions, without introducing extra masking steps or other process complexities.
摘要翻译：用于形成硅化物桥的方法是由薄电介质隔开的扩散区和相邻的多晶填充沟槽。硅在暴露的硅区域选择性地生长，条件是在薄介电层上提供受控的横向生长，而不允许在其它绝缘体区域上的横向生长。然后在限制侧向硅化物生长的条件下沉积和烧结难熔金属层，形成桥。该过程避免了以前的过程产生的随机失败，同时增强了与浅结的桥形成的兼容性，而不引入额外的掩蔽步骤或其他过程复杂性。

15. 发明授权

US08446757B2 Spin-torque transfer magneto-resistive memory architecture 有权
标题翻译：自旋扭矩传递磁阻存储器架构
公开(公告)号：US08446757B2
公开(公告)日：2013-05-21
申请号：US12858879
申请日：2010-08-18
申请人： John K. DeBrosse , Yutaka Nakamura
发明人： John K. DeBrosse , Yutaka Nakamura
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , Y10S977/935
摘要： A memory array device comprising a first memory cell comprising a first magnetic tunnel junction device having a first terminal connected to a first bit line (BLTE) and a second terminal, and a first field effect transistor (FET) having a source terminal connected to a second bit line (BLC), a gate terminal connected to a word line (WL), and a drain terminal connected to the second terminal of the first magnetic tunnel junction device, and a second memory cell comprising, a second magnetic tunnel junction device having a first terminal connected to a third bit line (BLT0) and a second terminal, and a second field effect transistor (FET) having a source terminal connected to the second bit line (BLC), a gate terminal connected to the word line (WL), and a drain terminal connected to the second terminal of the second magnetic tunnel junction device.
摘要翻译：一种存储器阵列器件，包括第一存储器单元，该第一存储器单元包括具有连接到第一位线（BLTE）的第一端子和第二端子的第一磁性隧道结器件，以及具有与源极端子连接的第一场效应晶体管第二位线（BLC），连接到字线（WL）的栅极端子和连接到第一磁性隧道结装置的第二端子的漏极端子，以及第二存储单元，其包括：第二磁性隧道结装置，连接到第三位线（BLT0）和第二端子的第一端子和具有连接到第二位线（BLC）的源极端子的第二场效应晶体管（FET），连接到字线（WL）的栅极端子）和连接到第二磁性隧道结装置的第二端子的漏极端子。

16. 发明申请

US20120294071A1 Spin-Torque Transfer Magneto-Resistive Memory Architecture 失效
标题翻译：自旋转移磁阻存储器架构
公开(公告)号：US20120294071A1
公开(公告)日：2012-11-22
申请号：US13559672
申请日：2012-07-27
申请人： John K. DeBrosse , Yutaka Nakamura
发明人： John K. DeBrosse , Yutaka Nakamura
IPC分类号： G11C11/16
CPC分类号： G11C11/16 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , Y10S977/935
摘要： A system includes a processor and a memory array connected to the processor comprising a first memory cell comprising a first magnetic tunnel junction device having a first terminal connected to a first bit line and a second terminal, and a first field effect transistor having a source terminal connected to a second bit line, a gate terminal connected to a word line, and a drain terminal connected to the second terminal of the first magnetic tunnel junction device, and a second memory cell comprising a second magnetic tunnel junction device having a first terminal connected to a third bit line and a second terminal, and a second field effect transistor having a source terminal connected to the second bit line, a gate terminal connected to the word line, and a drain terminal connected to the second terminal of the second magnetic tunnel junction device.
摘要翻译：一种系统包括处理器和连接到处理器的存储器阵列，该存储器阵列包括第一存储器单元，该第一存储器单元包括具有连接到第一位线的第一端子和第二端子的第一磁性隧道结器件，以及具有源极端子的第一场效应晶体管连接到第二位线，连接到字线的栅极端子和连接到第一磁性隧道结装置的第二端子的漏极端子，以及包括第二磁性隧道结装置的第二存储单元，第二磁性隧道结装置具有第一端子连接至第三位线和第二端子，以及第二场效应晶体管，其源极端子连接到第二位线，连接到字线的栅极端子和连接到第二磁通道的第二端子的漏极端子连接装置。

17. 发明申请

US20120044754A1 Spin-Torque Transfer Magneto-Resistive Memory Architecture 有权
标题翻译：自旋转移磁阻存储器架构
公开(公告)号：US20120044754A1
公开(公告)日：2012-02-23
申请号：US12858879
申请日：2010-08-18
申请人： John K. DeBrosse , Yutaka Nakamura
发明人： John K. DeBrosse , Yutaka Nakamura
IPC分类号： G11C11/14
CPC分类号： G11C11/16 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693 , Y10S977/935
摘要： A memory array device comprising a first memory cell comprising a first magnetic tunnel junction device having a first terminal connected to a first bit line (BLTE) and a second terminal, and a first field effect transistor (FET) having a source terminal connected to a second bit line (BLC), a gate terminal connected to a word line (WL), and a drain terminal connected to the second terminal of the first magnetic tunnel junction device, and a second memory cell comprising, a second magnetic tunnel junction device having a first terminal connected to a third bit line (BLT0) and a second terminal, and a second field effect transistor (FET) having a source terminal connected to the second bit line (BLC), a gate terminal connected to the word line (WL), and a drain terminal connected to the second terminal of the second magnetic tunnel junction device.
摘要翻译：一种存储器阵列器件，包括第一存储器单元，该第一存储器单元包括具有连接到第一位线（BLTE）的第一端子和第二端子的第一磁性隧道结器件，以及具有与源极端子连接的第一场效应晶体管第二位线（BLC），连接到字线（WL）的栅极端子和连接到第一磁性隧道结装置的第二端子的漏极端子，以及第二存储单元，其包括：第二磁性隧道结装置，连接到第三位线（BLT0）和第二端子的第一端子和具有连接到第二位线（BLC）的源极端子的第二场效应晶体管（FET），连接到字线（WL）的栅极端子）和连接到第二磁性隧道结装置的第二端子的漏极端子。

18. 发明授权

US07514271B2 Method of forming high density planar magnetic domain wall memory 有权
标题翻译：形成高密度平面磁畴壁记忆的方法
公开(公告)号：US07514271B2
公开(公告)日：2009-04-07
申请号：US11694183
申请日：2007-03-30
申请人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L. C. Hsu , Carl Radens , Keith Kwong-Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L. C. Hsu , Carl Radens , Keith Kwong-Hon Wong , Chih-Chao Yang
IPC分类号： H01L21/00 , G11C5/12 , G11C11/14
CPC分类号： G11C19/0841 , B82Y10/00 , G11C5/02 , G11C11/161 , G11C11/1675 , Y10T29/53165
摘要： A method of forming a magnetic domain wall memory apparatus with write/read capability includes forming a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location: forming a magnetic read element associated with each of the shift register structures: and forming a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of one of the plurality of discontinuities in the associated shift register structure.
摘要翻译：形成具有写入/读取能力的磁畴壁存储装置的方法包括形成多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个其中的不连续性以便于域壁位置：形成与每个移位寄存器结构相关联的磁读取元件;以及形成与每个移位寄存器结构相关联的磁写元件，所述磁写入元件还包括具有收缩的写入线其中，所述收缩部位于与相关联的移位寄存器结构中的所述多个不连续之一的位置相对应的点处。

19. 发明申请

US20090086534A1 APPARATUS AND METHOD FOR IMPLEMENTING PRECISE SENSING OF PCRAM DEVICES 失效
标题翻译：用于实施PCRAM设备精密感测的装置和方法
公开(公告)号：US20090086534A1
公开(公告)日：2009-04-02
申请号：US11865134
申请日：2007-10-01
申请人： John K. DeBrosse , Thomas M. Maffitt , Mark C.H. Lamorey
发明人： John K. DeBrosse , Thomas M. Maffitt , Mark C.H. Lamorey
IPC分类号： G11C11/00 , G11C7/00 , G11C7/10
CPC分类号： G11C29/02 , G11C7/062 , G11C7/067 , G11C13/0004 , G11C13/004 , G11C29/026 , G11C29/028 , G11C2013/0054
摘要： A precision sense amplifier apparatus includes a current source configured to introduce an adjustable reference current through a reference leg; a current mirror configured to mirror the reference current to a data leg, the data leg selectively coupled to a programmable resistance memory element; an active clamping device coupled to the data leg, and configured to clamp a fixed voltage across the memory element, thereby establishing a fixed current sinking capability thereof; and a differential sense amplifier having a first input thereof coupled to the data leg and a second input thereof coupled to the reference leg; wherein an output of the differential sense amplifier assumes a first logic state whenever the reference current is less than the fixed current sinking capability of the memory element, and assumes a second logic state whenever the reference current exceeds the fixed current sinking capability.
摘要翻译：精密读出放大器装置包括：电流源，被配置为通过参考支路引入可调参考电流; 配置为将参考电流镜像到数据支路的电流镜，所述数据支路选择性地耦合到可编程电阻存储元件; 耦合到所述数据支脚的有源钳位装置，并且被配置为在所述存储元件上钳位固定电压，由此建立其固定的电流吸收能力; 以及差分读出放大器，其具有耦合到所述数据支路的第一输入端和耦合到所述基准支路的第二输入端; 其中每当所述参考电流小于所述存储元件的固定电流吸收能力时，所述差分读出放大器的输出呈现第一逻辑状态，并且每当所述参考电流超过所述固定电流吸收能力时，所述差分读出放大器的输出呈现第二逻辑状态。

20. 发明授权

US06351019B1 Planarized and fill biased integrated circuit chip 有权
标题翻译：平面化和补偿偏置集成电路芯片
公开(公告)号：US06351019B1
公开(公告)日：2002-02-26
申请号：US09585503
申请日：2000-06-01
申请人： John K. DeBrosse , Matthew R. Wordeman
发明人： John K. DeBrosse , Matthew R. Wordeman
IPC分类号： H01L2900
CPC分类号： H01L21/76224 , H01L21/82 , H01L27/0629
摘要： An isolation and gate planarization method for an integrated circuit chip and chips designed by the method. The method comprises generating a dummy gate conductor (GC) shape and biasing it to the underlying well. The method may further comprise generating an active area (AA) dummy shape underlying the GC dummy shape. Biasing may be to the same voltage as the underlying well, or may be to a different voltage to create a decoupling capacitor. The biasing may be accomplished by implanting a well contact on an active area shape, the contact being N+ over an N-well or P+ over a P-well.
摘要翻译：一种用于集成电路芯片和芯片设计的隔离栅极平面化方法。该方法包括产生虚拟栅极导体（GC）形状并将其偏压到下面的阱。该方法还可以包括生成下面的GC虚拟形状的有源区（AA）虚拟形状。偏置可能与下面的阱具有相同的电压，或者可以是不同的电压以产生去耦电容器。偏置可以通过在有源区域形状上注入阱接触来实现，该触点是通过P阱的N阱或P +上的N +。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式