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11. 发明授权

US07029925B2 FeRAM capacitor stack etch 有权
标题翻译： FeRAM电容堆栈蚀刻
公开(公告)号：US07029925B2
公开(公告)日：2006-04-18
申请号：US10968721
申请日：2004-10-19
申请人： Francis G. Celii , Scott R. Summerfelt , Mahesh Thakre
发明人： Francis G. Celii , Scott R. Summerfelt , Mahesh Thakre
IPC分类号： H01L21/00 , H01L21/8242
CPC分类号： H01L27/11502 , H01L21/31122 , H01L21/31691 , H01L21/32139 , H01L27/11507 , H01L28/55
摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3 etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF3 to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.
摘要翻译：本发明涉及形成FeRAM集成电路的方法，其包括执行电容器堆叠蚀刻以限定FeRAM电容器。该方法包括用提供相对于硬掩模的实质选择性的高温BCl 3 N 3蚀刻来蚀刻PZT铁电层。或者，PZT铁电层是使用诸如CHF 3 N 3的低温氟成分蚀刻化学品进行蚀刻，以提供非垂直PZT侧壁轮廓。这种轮廓防止与随后的底部电极层蚀刻相关联的导电材料沉积在PZT侧壁上，从而防止所得FeRAM电容器的泄漏或“短路”。

12. 发明授权

US06506616B1 Photolithographic method for fabricating organic light-emitting diodes 有权
标题翻译：用于制造有机发光二极管的光刻方法
公开(公告)号：US06506616B1
公开(公告)日：2003-01-14
申请号：US09714472
申请日：2000-11-16
申请人： Tae S. Kim , Francis G. Celii , Simon J. Jacobs
发明人： Tae S. Kim , Francis G. Celii , Simon J. Jacobs
IPC分类号： H01L2100
CPC分类号： H01L51/56 , H01L51/0018 , H01L51/5253
摘要： A method of photolithographically patterning an organic semiconductor device, comprising the steps of protecting the organic layer of the device by depositing a metal layer thereon, depositing and patterning a photoresist layer on said metal layer, and selectively etching the exposed areas to pattern said metal layer and said organic layer. Specifically, the disclosed method provides the photolithographic fabrication of organic light emitting diodes (OLEDs) and organic lasers diodes (OLDs).
摘要翻译：一种光刻图案化有机半导体器件的方法，包括以下步骤：通过在其上沉积金属层来保护器件的有机层，在所述金属层上沉积和图案化光致抗蚀剂层，并且选择性地蚀刻暴露的区域以图案化所述金属层并说有机层。具体地，所公开的方法提供有机发光二极管（OLED）和有机激光二极管（OLD）的光刻制造。

13. 发明授权

US07572698B2 Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean 有权
标题翻译：通过等离子体蚀刻清洁减轻铁电存储器件中的边缘退化
公开(公告)号：US07572698B2
公开(公告)日：2009-08-11
申请号：US11442810
申请日：2006-05-30
申请人： Kezhakkedath R. Udayakumar , Lindsey H. Hall , Francis G. Celii , Scott R. Summerfelt
发明人： Kezhakkedath R. Udayakumar , Lindsey H. Hall , Francis G. Celii , Scott R. Summerfelt
IPC分类号： H01L21/336
CPC分类号： H01L21/31122 , H01L21/0206 , H01L21/02071 , H01L21/32136 , H01L27/11502 , H01L28/55 , H01L28/65
摘要： A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.
摘要翻译：制造铁电存储器件，同时减轻边缘退化。在一个或多个半导体层上形成底部电极。在底部电极上形成铁电层。顶部电极形成在铁电层上。上电极，铁电层和底电极被图案化或蚀刻。进行干洗以减轻边缘退化。然后进行湿蚀刻/清洁。

14. 发明授权

US06713342B2 FeRAM sidewall diffusion barrier etch 有权
标题翻译： FeRAM侧壁扩散阻挡蚀刻
公开(公告)号：US06713342B2
公开(公告)日：2004-03-30
申请号：US10282759
申请日：2002-10-29
申请人： Francis G. Celii , Scott R. Summerfelt , Tomoyuki Sakoda , Chiu Chi
发明人： Francis G. Celii , Scott R. Summerfelt , Tomoyuki Sakoda , Chiu Chi
IPC分类号： H01L218242
CPC分类号： H01L21/31122 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/75
摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a sidewall diffusion barrier prior to etching the bottom electrode diffusion barrier layer. The sidewall diffusion barrier layer is then etched prior to the bottom electrode diffusion barrier layer. In patterning an AlOx sidewall diffusion barrier layer prior to etching the underlying bottom electrode diffusion barrier layer, the etch chemistry comprises BCl3+Ar. The BCl3 is effective in etching the AlOx with a good selectivity to the underlying nitride hard mask on top of the capacitor stack (e.g., TiAlN) and nitride bottom electrode diffusion barrier (e.g., TiAlON with small oxygen content) between the neighboring capacitor stacks. The Ar may be added to the etch chemistry because the resulting surface (of a top portion of the hard mask and the bottom electrode diffusion barrier) is smoother.
摘要翻译：本发明涉及一种形成FeRAM集成电路的方法，其包括在蚀刻底部电极扩散阻挡层之前形成侧壁扩散阻挡层。然后在底部电极扩散阻挡层之前蚀刻侧壁扩散阻挡层。在蚀刻下面的底部电极扩散阻挡层之前，在构图AlOx侧壁扩散阻挡层之前，蚀刻化学性质包括BCl 3 + Ar。 BCl3在相邻的电容器堆叠之间的电容器堆叠（例如TiAlN）和氮化物底部电极扩散阻挡层（例如，具有小的氧含量的TiAlON）的顶部上对下面的氮化物硬掩模具有良好的选择性是有效的。可以将Ar添加到蚀刻化学品中，因为所得到的表面（硬掩模和底部电极扩散屏障的顶部）更平滑。

15. 发明授权

US06605482B2 Process for monitoring the thickness of layers in a microelectronic device 有权
公开(公告)号：US06605482B2
公开(公告)日：2003-08-12
申请号：US09975637
申请日：2001-10-11
申请人： Francis G. Celii , Maureen A. Hanratty , Katherine E. Violette , Rick L. Wise
发明人： Francis G. Celii , Maureen A. Hanratty , Katherine E. Violette , Rick L. Wise
IPC分类号： H01L2166
CPC分类号： G01N21/55
摘要： A method of determining the thickness of a thickness of a first layer of material in a semiconductor device using a reflectometer, the first layer of material being disposed outwardly from a second layer of material, the first and second layer of material both including silicon. The method includes generating at least one predicted behavior curve associated with a depth profile of an interface between the first and second layer of material, the predicted behavior curve including at least one expected optical measurement, the depth profile associated with the interface being present at a particular theoretical depth. The method also includes emitting light onto a surface of the semiconductor device. The method further includes collecting at least one optical measurement from portions of the emitted light that are reflected by the semiconductor device. The method additionally includes comparing the at least one optical measurement to the predicted behavior curve and determining the approximate actual depth of the interface in response to the compared optical measurement.

16. 发明授权

US06521042B1 Semiconductor growth method 失效
标题翻译：半导体生长法
公开(公告)号：US06521042B1
公开(公告)日：2003-02-18
申请号：US08667660
申请日：1996-06-21
申请人： Francis G. Celii , Alan J. Katz , Yung-Chung Kao , Theodore S. Moise
发明人： Francis G. Celii , Alan J. Katz , Yung-Chung Kao , Theodore S. Moise
IPC分类号： C30B2516
CPC分类号： H01L29/882 , B82Y10/00 , B82Y15/00 , C30B23/002 , C30B29/40 , H01L21/02392 , H01L21/02463 , H01L21/02546 , H01L21/02631 , Y10T117/1004 , Y10T117/1008
摘要： Molecular beam epitaxy (202) with growing layer thickness control (206) by feedback of mass spectrometer (204) signals based on a process model. Examples include III-V compound structures with multiple AlAs, InGaAs, and InAs layers as used in resonant tunneling diodes.
摘要翻译：基于过程模型，通过质谱仪（204）反馈信号生长层厚度控制（206）的分子束外延（202）。实例包括具有多个AlAs，InGaAs和InAs层的III-V族化合物结构，如共振隧道二极管所用。

17. 发明授权

US5985025A Semiconductor growth method 失效
公开(公告)号：US5985025A
公开(公告)日：1999-11-16
申请号：US382324
申请日：1995-02-01
申请人： Francis G. Celii , Alan J. Katz , Yung-Chung Kao , Theodore S. Moise
发明人： Francis G. Celii , Alan J. Katz , Yung-Chung Kao , Theodore S. Moise
IPC分类号： C30B23/08 , C30B23/02 , C30B29/68 , H01L21/203 , H01L21/338 , H01L29/812 , H01L29/88 , C30B25/16
CPC分类号： H01L29/882 , B82Y10/00 , B82Y15/00 , C30B23/002 , C30B29/40 , H01L21/02392 , H01L21/02463 , H01L21/02546 , H01L21/02631 , Y10T117/1004 , Y10T117/1008
摘要： Molecular beam epitaxy (202) with growing layer thickness control (206) by feedback of mass spectrometer (204) signals based on a process model. Examples include III-V compound structures with multiple AlAs, InGaAs, and InAs layers as used in resonant tunneling diodes.

18. 发明授权

US5501637A Temperature sensor and method 失效
标题翻译：温度传感器和方法
公开(公告)号：US5501637A
公开(公告)日：1996-03-26
申请号：US309347
申请日：1994-09-20
申请人： Walter M. Duncan , Francis G. Celii , Steven A. Henck , Ajit P. Paranjpe , Douglas L. Mahlum , Larry A. Taylor
发明人： Walter M. Duncan , Francis G. Celii , Steven A. Henck , Ajit P. Paranjpe , Douglas L. Mahlum , Larry A. Taylor
IPC分类号： G01J5/00 , G01N21/21 , G01J5/10 , G01J4/04 , G01J5/58 , G02F1/01
CPC分类号： G01J5/0003 , G01J5/0007 , G01J5/0846 , G01J5/58 , G01N21/211
摘要： A direct, noncontact temperature sensor includes an ellipsometer (104-106) to determine absorptance for layered structures and a pyrometer (102) to determine emissive power and combines the two measurements to determine temperature.
摘要翻译：直接非接触式温度传感器包括用于确定分层结构的吸收率的椭偏仪（104-106）和用于确定发射功率的高温计（102）并组合两个测量值以确定温度。

19. 发明授权

US5399521A Method of semiconductor layer growth by MBE 失效
标题翻译：通过MBE生长半导体层的方法
公开(公告)号：US5399521A
公开(公告)日：1995-03-21
申请号：US133699
申请日：1993-10-08
申请人： Francis G. Celii , Yung-Chung Kao , Andrew J. Purdes
发明人： Francis G. Celii , Yung-Chung Kao , Andrew J. Purdes
IPC分类号： C30B25/02 , C23C14/22 , C30B23/02 , C30B23/08 , H01L21/203 , H01L21/331 , H01L21/66 , H01L29/205 , H01L29/73 , H01L29/737
CPC分类号： H01L22/26 , B24B37/013 , B82Y10/00 , B82Y15/00 , C30B23/002 , C30B29/40
摘要： Molecular beam epitaxy (202) with growing layer thickness control (206) by feedback of integrated mass spectormeter (204) signals. Examples include III-V compound structures with multiple AlAs, InGaAs, and InAs layers as used in resonant tunneling diodes.
摘要翻译：分子束外延（202）通过集成质谱仪（204）信号的反馈而增长层厚度控制（206）。实例包括具有多个AlAs，InGaAs和InAs层的III-V族化合物结构，如共振隧道二极管所用。

20. 发明授权

US08053252B2 Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean 有权
标题翻译：通过等离子体蚀刻清洁减轻铁电存储器件中的边缘退化
公开(公告)号：US08053252B2
公开(公告)日：2011-11-08
申请号：US12502571
申请日：2009-07-14
申请人： Kezhakkedath R. Udayakumar , Lindsey H. Hall , Francis G. Celii , Scott R. Summerfelt
发明人： Kezhakkedath R. Udayakumar , Lindsey H. Hall , Francis G. Celii , Scott R. Summerfelt
IPC分类号： H01L47/00
CPC分类号： H01L21/31122 , H01L21/0206 , H01L21/02071 , H01L21/32136 , H01L27/11502 , H01L28/55 , H01L28/65
摘要： A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.
摘要翻译：制造铁电存储器件，同时减轻边缘退化。在一个或多个半导体层上形成底部电极。在底部电极上形成铁电层。顶部电极形成在铁电层上。上电极，铁电层和底电极被图案化或蚀刻。进行干洗以减轻边缘退化。然后进行湿蚀刻/清洁。

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