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11. 外观设计

USD651248S1 Pen holder 有权
公开(公告)号：USD651248S1
公开(公告)日：2011-12-27
申请号：US29382409
申请日：2011-01-03
申请人： Fang Yuan
设计人： Fang Yuan

12. 外观设计

USD651243S1 Pen 有权
公开(公告)号：USD651243S1
公开(公告)日：2011-12-27
申请号：US29383937
申请日：2011-01-24
申请人： Fang Yuan
设计人： Fang Yuan

13. 外观设计

USD647567S1 Clip holder 有权
标题翻译：夹持器
公开(公告)号：USD647567S1
公开(公告)日：2011-10-25
申请号：US29382411
申请日：2011-01-03
申请人： Fang Yuan
设计人： Fang Yuan

14. 外观设计

USD647566S1 Tape dispenser 有权
公开(公告)号：USD647566S1
公开(公告)日：2011-10-25
申请号：US29391219
申请日：2011-05-04
申请人： Fang Yuan
设计人： Fang Yuan

15. 外观设计

USD647377S1 Stapler 有权
公开(公告)号：USD647377S1
公开(公告)日：2011-10-25
申请号：US29391216
申请日：2011-05-04
申请人： Fang Yuan
设计人： Fang Yuan

16. 发明申请

US20070079046A1 Multiprocessor system 审中-公开
标题翻译：多处理器系统
公开(公告)号：US20070079046A1
公开(公告)日：2007-04-05
申请号：US11346312
申请日：2006-02-03
申请人： Shan-Kai Yang , Shi-Jun Ni , Jian Shen , Lei Ding , Hai-Ming Ding , Fang Yuan
发明人： Shan-Kai Yang , Shi-Jun Ni , Jian Shen , Lei Ding , Hai-Ming Ding , Fang Yuan
IPC分类号： G06F13/00
CPC分类号： G06F15/17337
摘要： A multiprocessor system is disclosed, which comprises a plurality of processor unit, such as eight processor units, and a plurality of interconnection bus that may be a dual unidirectional point-to-point bus. Every interconnection bus connects predetermined two of the processor units. Particularly, at least two of the interconnection buses are crossed to each other.
摘要翻译：公开了一种多处理器系统，其包括多个处理器单元，例如八个处理器单元，以及可以是双向单向点对点总线的多个互连总线。每个互连总线连接预定的两个处理器单元。特别地，至少两个互连总线彼此交叉。

17. 发明申请

US20060069483A1 Collision determining apparatus for a vehicle 失效
标题翻译：用于车辆的碰撞确定装置
公开(公告)号：US20060069483A1
公开(公告)日：2006-03-30
申请号：US11230469
申请日：2005-09-21
申请人： Masatoshi Hayasaka , Fang Yuan , Tatsuji Oosaki
发明人： Masatoshi Hayasaka , Fang Yuan , Tatsuji Oosaki
IPC分类号： B60R22/00 , G06F17/00
CPC分类号： B60R21/0132 , B60R21/0133 , B60R21/01336 , B60R21/01542 , B60R2021/01315 , B60R2021/01322
摘要： A collision determining apparatus for a vehicle includes: a first acceleration measuring device; a second acceleration measuring device; a movement amount calculating device; a change in movement speed calculating device; a first collision determining threshold value setting device which sets a collision determining threshold value for a correlation between the amount of movement of the occupant and the change in movement speed of the occupant based on the acceleration which is measured by the first acceleration measuring device; a first collision determining device which determines whether or not the correlation exceeds the collision determining threshold value; and a control signal generating device which generates a control signal which controls operations of an occupant protection apparatus, in accordance with a result of a determination by the first collision determining device.
摘要翻译：一种用于车辆的碰撞确定装置包括：第一加速度测量装置; 第二加速度测量装置; 移动量计算装置; 移动速度计算装置的变化; 第一碰撞判定阈值设定装置，其基于由所述第一加速度测量装置测量的加速度，设定所述乘员的移动量与所述乘员的移动速度的相关性的冲突判定阈值; 确定相关性是否超过冲突判定阈值的第一冲突判定装置; 以及控制信号生成装置，其根据第一碰撞判定装置的判定结果生成控制乘员保护装置的动作的控制信号。

18. 发明公开

US20230246756A1 DOWNLINK SCHEMES FOR A COOPERATIVE USER EQUIPMENT WITH JOINT BASEBAND PROCESSING 审中-公开
公开(公告)号：US20230246756A1
公开(公告)日：2023-08-03
申请号：US18001376
申请日：2020-08-24
申请人： Mostafa Khoshnevisan , Aleksandar Damnjanovic , Xiaoxia Zhang , Tao Luo , Jing Sun , Fang Yuan , Yitao Chen , Juan Montojo , Rajat Prakash , QUALCOMM Incorporated
发明人： Mostafa Khoshnevisan , Aleksandar Damnjanovic , Xiaoxia Zhang , Tao Luo , Jing Sun , Fang Yuan , Yitao Chen , Juan Montojo , Rajat Prakash
IPC分类号： H04L5/00 , H04W8/22
CPC分类号： H04L5/0035 , H04W8/22 , H04L5/0091
摘要： Downlink schemes are disclosed for a cooperative user equipment (UE) with joint baseband processing. UEs may establish a cooperative UE unit with one or more neighboring UEs, where one of the UEs operates as the primary UE. The participating UEs of the cooperative UE unit determine a downlink transmission scheme for the cooperative transmissions from a serving base station and receive cooperative transmissions of one or more transport blocks from the serving base station according to the downlink transmission scheme. The secondary UEs of the cooperative UE unit generate and transmit cooperative process data to the primary UE, where the cooperative process data is based on the receipt of the cooperative transmissions by the secondary UEs. The primary UE processes its received cooperative transmission along with the cooperative process data to decode the one or more transport blocks. Other aspects and features are also claimed and described.

19. 发明申请

US20140252254A1 VALVE CORE ASSEMBLY AND VALVE ADOPTING THE VALVE CORE ASSEMBLY 有权
标题翻译：阀芯组件和阀门采用阀芯组件
公开(公告)号：US20140252254A1
公开(公告)日：2014-09-11
申请号：US14342874
申请日：2012-07-13
申请人： Fang Yuan , Zuocheng Qian , Kai Gong , Qingxin Liao
发明人： Fang Yuan , Zuocheng Qian , Kai Gong , Qingxin Liao
IPC分类号： F16K5/06 , F16K5/20
CPC分类号： F16K5/0647 , F16K5/20 , F16K5/204
摘要： A valve core assembly and a valve adopting the valve core assembly. The valve core assembly comprises a valve core (4) and a transmission member (7) having a common axis, and a sliding ejector pin (6) arranged along an axis perpendicular to the common axis. The valve core assembly is disposed inside a valve body (1) and is rotatable about the common axis upon engaging with the valve body (1). The valve core (4) has one concave portion, and the transmission member (7) is at least partially placed inside the concave portion. A radial inwardly-convex profile (9) is formed at the circumferential wall inside the concave portion, the transmission member (7) is formed with a radial outwardly-convex profile (72), and when a valve rod (2) drives the sliding ejector pin (6) and the transmission member (7) to rotate, the radial inwardly-convex profile (9) in the concave portion of the valve core (4) engages with the sliding ejector pin (6) and the radial outwardly-convex profile (72) of the transmission member (7) to switch the valve core among an open state, a pre-closed state and a fully-closed state. The valve core assembly has a simple structure and a high space utilization, so as to minimize the size of the valve, and the opening torque is small and the sealing performance is desirable.
摘要翻译：阀芯组件和采用阀芯组件的阀。阀芯组件包括阀芯（4）和具有共同轴线的传动构件（7）和沿着垂直于公共轴线的轴线布置的滑动推杆（6）。阀芯组件设置在阀体（1）的内部，并且在与阀体（1）接合时能够围绕公共轴线旋转。阀芯（4）具有一个凹部，传递部件（7）至少部分地设置在凹部内。径向向内凸出的轮廓（9）形成在凹部内部的圆周壁上，传动构件（7）形成有径向向外凸出的轮廓（72），当阀杆（2）驱动滑动推杆（6）和传动构件（7）旋转，阀芯（4）的凹入部分中的径向向内凸出的轮廓（9）与滑动推杆（6）接合，径向向外凸出（7）的轮廓（72），以将阀芯切换到打开状态，预关闭状态和完全关闭状态。阀芯组件具有简单的结构和高空间利用率，从而使阀的尺寸最小化，开启扭矩小，密封性能优良。

20. 发明授权

US08748934B2 Vertical selection transistor, memory cell, and three-dimensional memory array structure and method for fabricating the same 有权
标题翻译：垂直选择晶体管，存储单元和三维存储器阵列结构及其制造方法
公开(公告)号：US08748934B2
公开(公告)日：2014-06-10
申请号：US13520166
申请日：2012-03-12
申请人： Liyang Pan , Fang Yuan
发明人： Liyang Pan , Fang Yuan
IPC分类号： H01L29/08 , H01L27/24 , H01L21/70 , H01L29/78
CPC分类号： H01L27/24 , H01L21/70 , H01L27/2445 , H01L27/2481 , H01L29/04 , H01L29/66348 , H01L29/7394 , H01L29/7397 , H01L29/7827 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/145 , H01L45/146 , H01L45/1675
摘要： The present disclosure discloses a vertical selection transistor, a memory cell having the vertical selection transistor, a three-dimensional memory array structure and a method for fabricating the three-dimensional memory array structure. The vertical selection transistor comprises: an upper electrode; a lower electrode; a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer vertically stacked between the lower electrode and the upper electrode; and a gate stack formed on a side of the second semiconductor layer, in which the first semiconductor layer and the third semiconductor layer are first type doped layers, the second semiconductor layer and the fourth semiconductor layer are second type doped layers, and a doping concentration of the second semiconductor layer is lower than that of the first semiconductor layer or that of the third semiconductor layer respectively.
摘要翻译：本公开公开了一种垂直选择晶体管，具有垂直选择晶体管的存储单元，三维存储器阵列结构和用于制造三维存储器阵列结构的方法。垂直选择晶体管包括：上电极; 下电极第一半导体层，第二半导体层，第三半导体层和垂直堆叠在下电极和上电极之间的第四半导体层; 以及形成在所述第二半导体层的一侧的栅堆叠，其中所述第一半导体层和所述第三半导体层是第一掺杂层，所述第二半导体层和所述第四半导体层是第二掺杂层，并且掺杂浓度分别低于第一半导体层或第三半导体层的厚度。

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