专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07968435B1 Method and device for growing pseudomorphic AlInAsSb on InAs 失效
标题翻译：用于在InAs上生长伪晶AlInAsSb的方法和装置
公开(公告)号：US07968435B1
公开(公告)日：2011-06-28
申请号：US12491004
申请日：2009-06-24
申请人： Peter Deelman , Ken Elliott , David Chow
发明人： Peter Deelman , Ken Elliott , David Chow
IPC分类号： H01L21/20
CPC分类号： H01L21/02395 , H01L21/02463 , H01L21/02466 , H01L21/02507 , H01L21/02546 , H01L21/02549 , H01L21/02631
摘要： A semiconductor device and method are being disclosed. The semiconductor device discloses an InAs layer, a plurality of group III-V ternary layers supported by the InAs layer, and a plurality of group III-V quarternary layers supported by the InAs layer, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer. The method discloses providing an InAs layer, growing a plurality of group III-V ternary layers, and growing a plurality of group III-V quarternary layers, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer and are supported by the InAs layer.
摘要翻译：正在公开半导体器件和方法。半导体器件公开了InAs层，由InAs层支撑的多个III-V族三元层和由InAs层支撑的多个III-V族第三层，其中III-V族三元层与彼此由一个III-V组单独的三层组成。该方法公开了提供InAs层，生长多个III-V族三元层，并生长多个III-V族第三层，其中III-V族三元层通过单组III- V第三层，并由InAs层支持。

12. 发明授权

US07598158B1 Method and device for growing pseudomorphic AlInAsSb on InAs 失效
标题翻译：用于在InAs上生长伪晶AlInAsSb的方法和装置
公开(公告)号：US07598158B1
公开(公告)日：2009-10-06
申请号：US11447338
申请日：2006-06-05
申请人： Peter Deelman , Ken Elliott , David Chow
发明人： Peter Deelman , Ken Elliott , David Chow
IPC分类号： H01L21/20
CPC分类号： H01L21/02395 , H01L21/02463 , H01L21/02466 , H01L21/02507 , H01L21/02546 , H01L21/02549 , H01L21/02631
摘要： A semiconductor device and method are being disclosed. The semiconductor device discloses an InAs layer, a plurality of group III-V ternary layers supported by the InAs layer, and a plurality of group III-V quarternary layers supported by the InAs layer, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer. The method discloses providing an InAs layer, growing a plurality of group III-V ternary layers, and growing a plurality of group III-V quarternary layers, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer and are supported by the InAs layer.
摘要翻译：正在公开半导体器件和方法。半导体器件公开了InAs层，由InAs层支撑的多个III-V族三元层和由InAs层支撑的多个III-V族第三层，其中III-V族三元层与彼此由一个III-V组单独的三层组成。该方法公开了提供InAs层，生长多个III-V族三元层，并生长多个III-V族第三层，其中III-V族三元层通过单组III- V第三层，并由InAs层支持。

13. 发明申请

US20080065788A1 System and method for producing high volume flash memory cards 审中-公开
标题翻译：用于生产大容量闪存卡的系统和方法
公开(公告)号：US20080065788A1
公开(公告)日：2008-03-13
申请号：US11979102
申请日：2007-10-31
申请人： David Chow , Sidney Young , Frank Yu , Abraham Ma , Ming-Shiang Shen
发明人： David Chow , Sidney Young , Frank Yu , Abraham Ma , Ming-Shiang Shen
IPC分类号： G06F13/10
CPC分类号： G06F12/1416 , G06F21/32 , G06F21/78 , G07C9/00087 , G07C2009/00095 , H01R13/629
摘要： A system for producing high volume flash memory cards includes a processing unit, a PC interface for connecting to an external PC, a PC drive circuit connected to the PC interface and the processing unit, a card interface for connecting to an external flash memory card, and a card drive circuit connected to the card interface and the processing unit. The PC drive circuit realizes communication between the PC and the processing unit. The card drive circuit realizes communication between the flash memory card and the processing unit. The processing unit receives command or data from the PC interface, and sends card re-initialization command or data to the flash memory card via the card interface.
摘要翻译：一种用于生产大容量闪存卡的系统包括处理单元，用于连接到外部PC的PC接口，连接到PC接口的PC驱动电路和处理单元，用于连接到外部闪存卡的卡接口，以及连接到卡接口和处理单元的卡驱动电路。 PC驱动电路实现PC与处理单元之间的通信。卡驱动电路实现闪存卡和处理单元之间的通信。处理单元从PC接口接收命令或数据，并通过卡接口将卡重新初始化命令或数据发送到闪存卡。

14. 发明申请

US20080034154A1 Multi-Channel Flash Module with Plane-Interleaved Sequential ECC Writes and Background Recycling to Restricted-Write Flash Chips 有权
标题翻译：具有平面交错顺序ECC的多通道闪存模块写入和背景回收限制写入闪存芯片
公开(公告)号：US20080034154A1
公开(公告)日：2008-02-07
申请号：US11871627
申请日：2007-10-12
申请人： Charles Lee , Abraham Ma , Frank Yu , David Chow , Ming-Shiang Shen
发明人： Charles Lee , Abraham Ma , Frank Yu , David Chow , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F12/0607 , G06F12/0246 , G06F2212/7201 , G06F2212/7203 , G06F2212/7205 , G06F2212/7208 , G11C16/0408 , G11C2211/5649
摘要： A RAM mapping table is restored from flash memory using plane, block, and page addresses generated by a physical sequential address counter. The RAM mapping table is restored following a plane-interleaved sequence generated by the physical sequential address counter using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. The physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. Background recycling and ECC writes are also performed.
摘要翻译：使用由物理顺序地址计数器生成的平面，块和页面地址从闪存中恢复RAM映射表。 RAM映射表在使用从逻辑块索引的最低位提取的交错比特的物理顺序地址计数器产生的平面交织序列之后恢复。这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。物理顺序地址计数器通过在中间物理块位之前递增平面交织比特，然后将MSB重定位到中间物理块比特之上来生成物理块号。这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。还执行后台回收和ECC写入。

15. 发明申请

US20080034153A1 Flash Module with Plane-Interleaved Sequential Writes to Restricted-Write Flash Chips 有权
标题翻译：闪存模块与平面交错顺序写入限制写入闪存芯片
公开(公告)号：US20080034153A1
公开(公告)日：2008-02-07
申请号：US11871011
申请日：2007-10-11
申请人： Charles Lee , Frank Yu , Abraham Ma , David Chow , Ming-Shiang Shen
发明人： Charles Lee , Frank Yu , Abraham Ma , David Chow , Ming-Shiang Shen
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F12/0607 , G06F2212/7201 , G06F2212/7208 , G11C11/5621 , G11C16/0408
摘要： A flash memory controller on a PCIE bus controls flash-memory modules on a flash bus. The flash-memory modules are plane-interleaved using interleaved bits extracted from the lowest bits of the logical block index. These plane-interleave bits are split into a LSB and a MSB, with middle physical block bits between the LSB and MSB. A physical sequential address counter generates a physical block number by incrementing the plane-interleave bits before the middle physical block bits, and then relocating the MSB to above the middle physical block bits. This causes blocks to be accessed in a low-high sequence of 0, 1, 4096, 4097, 2, 3, 4098, 4099, etc. in the four planes of flash memory. A RAM physical page valid table tracks valid pages in the four planes, while a RAM mapping table stores the plane, block, and page addresses for logical sectors generated by the physical sequential address counter.
摘要翻译： PCIE总线上的闪存控制器控制闪存总线上的闪存模块。闪存模块使用从逻辑块索引的最低位提取的交错比特进行平面交织。这些平面交织位分为LSB和MSB，LSB与MSB之间的中间物理块位。物理顺序地址计数器通过在中间物理块比特之前递增平面交织比特，然后将MSB重新定位到中间物理块比特之上来生成物理块号。这导致在闪存的四个平面中以0,1,4096,4097,2,3,40,40,4099等的低高序列访问块。 RAM物理页有效表跟踪四个平面中的有效页面，而RAM映射表存储由物理顺序地址计数器生成的逻辑扇区的平面，块和页面地址。

16. 发明申请

US20080016269A1 Flash / Phase-Change Memory in Multi-Ring Topology Using Serial-Link Packet Interface 失效
标题翻译：使用串行链路分组接口的多环拓扑中的闪存/相变存储器
公开(公告)号：US20080016269A1
公开(公告)日：2008-01-17
申请号：US11773827
申请日：2007-07-05
申请人： David Chow , Charles Lee , Frank Yu
发明人： David Chow , Charles Lee , Frank Yu
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G11C13/0004 , G11C16/102 , G11C2216/30
摘要： A multi-ring memory controller sends request packets to multiple rings of serial flash-memory chips. Each of the multiple rings has serial flash-memory chips with serial links in a uni-directional ring. Each serial flash-memory chip has a bypassing transceiver with a device ID checker that bypasses serial packets to a clock re-synchronizer and bypass logic for retransmission to the next device in the ring, or extracts the serial packet to the local device when an ID match occurs. Serial packets pass through all devices in the ring during one round-trip transaction from the controller. The average latency of one round is constant for all devices on the ring, reducing data-dependent performance, since the same packet latency occurs regardless of the data location on the ring. The serial links can be a Peripheral Component Interconnect (PCI) Express bus. Packets have modified-PCI-Express headers that define the packet type and data-payload length.
摘要翻译：多环存储器控制器将请求数据包发送到串行闪存芯片的多个环。多个环中的每个环都具有串行闪存芯片，其具有单向环中的串行链路。每个串行闪存芯片都具有一个旁路收发器，其中设备ID检查器将串行数据包绕过时钟重新同步器，并且旁路逻辑用于重传到环中的下一个设备，或者当ID为ID时将串行数据包提取给本地设备匹配发生。在来自控制器的一次往返事务期间，串行数据包通过环中的所有设备。由于相同的数据包延迟发生，环路上的所有设备的平均延迟都是恒定的，从而降低了数据相关性能，无论环的数据位置如何。串行链路可以是外围组件互连（PCI）Express总线。数据包已经修改了PCI-Express头，定义了数据包类型和数据有效负载长度。

17. 发明申请

US20070276988A1 Page and Block Management Algorithm for NAND Flash 有权
标题翻译： NAND Flash的页面和块管理算法
公开(公告)号：US20070276988A1
公开(公告)日：2007-11-29
申请号：US11779804
申请日：2007-07-18
申请人： Jianjun Luo , Chris Tsu , Charles Lee , David Chow
发明人： Jianjun Luo , Chris Tsu , Charles Lee , David Chow
IPC分类号： G06F13/28
CPC分类号： G06F12/0246 , G06F12/0292 , G06F13/28 , G06F2212/1036 , G06F2212/7211
摘要： A flash controller is adapted to communicate with a host and the flash memory and including volatile memory configured to store a page-block table of logical addresses addressable by the physical addresses. The logical addresses are used by the controller to identify the blocks. The table has an address mapping table and a property value table, the property value table includes property values, each of the property values being increased in value every time a block is written up to a maximum value and being associated with a block of a predetermined group of blocks and indicative of the number of times a block has been written, the property values corresponding to the logical addresses of the address mapping table, wherein the maximum number the property values of the predetermined group of blocks take on is adjustably different than the maximum number the property values of another group of blocks.
摘要翻译：闪存控制器适于与主机和闪存进行通信，并且包括被配置为存储可通过物理地址寻址的逻辑地址的页块表的易失性存储器。逻辑地址由控制器用于识别块。该表具有地址映射表和属性值表，属性值表包括属性值，每当一个块写入最大值并且与预定的块相关联时，每个属性值都被增加，指示块的写入次数的一组块，对应于地址映射表的逻辑地址的属性值，其中预定块组的属性值的最大数量可以与最大数量的另一组块的属性值。

18. 发明申请

US20050168686A1 Lenses 失效
标题翻译：镜片
公开(公告)号：US20050168686A1
公开(公告)日：2005-08-04
申请号：US11050331
申请日：2005-02-02
申请人： David Chow , Ngai Shing Chan
发明人： David Chow , Ngai Shing Chan
IPC分类号： B24B7/00 , B24B9/14 , B29C65/00 , B29C65/48 , B29C65/52 , B29D11/00 , C03C19/00 , C03C27/10 , C08G59/50 , C09D123/22 , C09D163/00 , C09D163/02 , C09J5/06 , G02B3/00 , G02C7/02
CPC分类号： B32B7/12 , B29C65/483 , B29C65/524 , B29C66/0222 , B29C66/02245 , B29C66/452 , B29C66/545 , B29C66/91431 , B29C66/919 , B29C66/9534 , B29D11/00932 , B29L2009/00 , B29L2011/0016 , B32B2551/00 , C03C19/00 , C03C27/10 , C09J5/06 , C09J2400/143 , C09J2400/146 , C09J2400/226 , C09J2400/228 , C09J2461/00 , C09J2463/00
摘要： A method of sealing lenses includes the steps of grinding the edges of at least two lenses, cleansing the lenses, positioning the lenses next to one another, applying an adhesive to the ground edges of the lenses and placing the lenses in an oven to cure the adhesive to produce a laminated, hermetically-sealed, lens.
摘要翻译：密封透镜的方法包括以下步骤：研磨至少两个透镜的边缘，清洁透镜，将透镜彼此相邻定位，将粘合剂施加到透镜的接地边缘并将透镜放置在烘箱中以固化粘合剂以产生层压密封的透镜。

19. 发明申请

US20130053149A1 NOTIFYING USERS OF OPTIONS TO PARTICIPATE IN META GAMES 有权
标题翻译：通知使用者参加META游戏
公开(公告)号：US20130053149A1
公开(公告)日：2013-02-28
申请号：US13244818
申请日：2011-09-26
申请人： Justin Rouse , Kevin Holme , Daniel Hurd , Jason Tomlinson , Grant Yang , Shawn Lohstroh , Jessica Oyhenart , David Chow
发明人： Justin Rouse , Kevin Holme , Daniel Hurd , Jason Tomlinson , Grant Yang , Shawn Lohstroh , Jessica Oyhenart , David Chow
IPC分类号： A63F9/24
CPC分类号： A63F13/216 , A63F13/12 , A63F13/46 , A63F13/795 , A63F13/798 , A63F2300/513 , A63F2300/556 , A63F2300/5566 , A63F2300/5573 , A63F2300/558 , A63F2300/61 , G06F3/048 , H04L67/18 , H04L67/38 , H04W4/02 , H04W4/21
摘要： In a method of notifying a user of an option to participate in a meta game, a presence of a player of a computer-implemented game at a location is detected. An association between a computer-implemented meta-game and the location is identified. The player of the computer-implemented game is presented with an option to participate in the computer-implemented meta-game. An indication of an acceptance of the option to participate in the computer-implemented meta game is received from the player of the computer-implemented game. A performance of an action within the computer-implemented game by the player of the computer-implemented game is reflected within the computer-implemented meta game.
摘要翻译：在通知用户参与元游戏的选项的方法中，检测在某个位置处的计算机实现的游戏的玩家的存在。识别计算机实现的元游戏与位置之间的关联。计算机实现游戏的播放器具有参与计算机实现的元游戏的选项。从计算机实现的游戏的玩家接收到接受参与计算机实现的元游戏的选项的指示。由计算机实现的游戏的玩家在计算机实现的游戏中的动作的表现反映在计算机实现的元游戏中。

20. 发明授权

US08368119B1 Integrated structure with transistors and schottky diodes and process for fabricating the same 有权
标题翻译：具有晶体管和肖特基二极管的集成结构及其制造方法
公开(公告)号：US08368119B1
公开(公告)日：2013-02-05
申请号：US13111771
申请日：2011-05-19
申请人： Louis Luh , Keh-Chung Wang , Wah S. Wong , Miroslav Micovic , David Chow , Don Hitko
发明人： Louis Luh , Keh-Chung Wang , Wah S. Wong , Miroslav Micovic , David Chow , Don Hitko
IPC分类号： H01L29/66
CPC分类号： H01L29/7787 , H01L21/8252 , H01L27/0605 , H01L27/0629 , H01L29/08 , H01L29/872
摘要： A process for fabricating an integrated group III nitride structure comprising high electron mobility transistors (HEMTs) and Schottky diodes, and the resulting structure, are disclosed. Integration of vertical junction Schottky diodes is enabled, and the parasitic capacitance and resistance as well as the physical size of the diode are minimized. A process for fabricating an integrated group III nitride structure comprising double-heterostructure field effect transistors (DHFETs) and Schottky diodes and the resulting structure are also disclosed.
摘要翻译：公开了一种用于制造包括高电子迁移率晶体管（HEMT）和肖特基二极管的集成III族氮化物结构的方法及其结果。使得垂直结肖特基二极管的集成成为可能，并且寄生电容和电阻以及二极管的物理尺寸最小化。还公开了一种制造包括双异质结构场效应晶体管（DHFET）和肖特基二极管的集成III族氮化物结构的方法及其结果。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式