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11. 发明授权

US08856434B2 Memory system and method 有权
标题翻译：内存系统和方法
公开(公告)号：US08856434B2
公开(公告)日：2014-10-07
申请号：US12819794
申请日：2010-06-21
申请人： Jun Li , Gabriel Li
发明人： Jun Li , Gabriel Li
IPC分类号： G06F12/00 , G06F13/16 , G06F13/28
CPC分类号： G06F13/28 , G06F13/1684
摘要： In an embodiment, an apparatus includes a memory controller configured to control a plurality of daisy chained memory components connected over a daisy chained bus. The daisy chained bus includes a direct connection from the transmit interface of the memory controller to a receive interface of an initial memory component, and a daisy chain connection from a transmit interface of the initial memory component to a receive interface of a next memory component. A bus extends from a transmit interface of a last memory component directly to a receive interface of the memory controller.
摘要翻译：在一个实施例中，一种装置包括存储器控制器，其被配置为控制通过菊花链式总线连接的多个菊花链连接的存储器组件。菊花链式总线包括从存储器控制器的发送接口到初始存储器组件的接收接口的直接连接以及从初始存储器组件的发送接口到下一个存储器组件的接收接口的菊花链连接。总线从最后存储器组件的发送接口直接延伸到存储器控制器的接收接口。

12. 发明授权

US07899145B2 Circuit, system, and method for multiplexing signals with reduced jitter 有权
标题翻译：具有减少抖动的信号复用的电路，系统和方法
公开(公告)号：US07899145B2
公开(公告)日：2011-03-01
申请号：US12577477
申请日：2009-10-12
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： H03D3/24
CPC分类号： H04J3/047 , H03K17/002 , H03K19/1737
摘要： An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.
摘要翻译：一种具有多个电源域和多个逻辑部件的装置。多个逻辑组件中的每一个驻留在多个电源域中的不同的一个中。所述多个逻辑部件中的每一个被配置为与所述多个电源域中的相应一个中的对应的时钟信号一起操作。

13. 发明授权

US07609799B2 Circuit, system, and method for multiplexing signals with reduced jitter 有权
标题翻译：具有减少抖动的信号复用的电路，系统和方法
公开(公告)号：US07609799B2
公开(公告)日：2009-10-27
申请号：US11468195
申请日：2006-08-29
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： H03D3/24
CPC分类号： H04J3/047 , H03K17/002 , H03K19/1737
摘要： A multiplexer circuit, system and method is provided herein for multiplexing signals with reduced jitter by eliminating all crosstalk and power supply noise injection within the multiplexer circuit. For example, crosstalk and supply noise injection may be eliminated by: (i) separating the multiplexing function into three separate logic gates and (ii) allowing only one switching input per logic gate. In some cases, jitter may be further reduced by distributing the logic gates across three distinct power domains. In other words, the logic gate inputs may be further isolated by gating each signal in its own power domain. In addition, the multiplexer circuit provides built in delay matching by utilizing three substantially identical logic gates.
摘要翻译：本文提供了一种多路复用器电路，系统和方法，用于通过消除多路复用器电路内的所有串扰和电源噪声注入来复用具有减小的抖动的信号。例如，可以通过以下步骤来消除串扰和电源噪声注入：（i）将复用功能分离成三个单独的逻辑门，并且（ii）每个逻辑门只允许一个开关输入。在某些情况下，可以通过在三个不同的电源域分配逻辑门来进一步降低抖动。换句话说，逻辑门输入可以通过门控其自身功率域中的每个信号来进一步隔离。此外，多路复用器电路通过利用三个基本相同的逻辑门来提供内置的延迟匹配。

14. 发明申请

US20080025383A1 Test Circuit, System, and Method for Testing One or More Circuit Components Arranged upon a Common Printed Circuit Board 有权
标题翻译：用于测试在普通印刷电路板上布置的一个或多个电路元件的测试电路，系统和方法
公开(公告)号：US20080025383A1
公开(公告)日：2008-01-31
申请号：US11460444
申请日：2006-07-27
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： H04B3/46
CPC分类号： G01R31/31922 , G01R31/31709 , G01R31/31937
摘要： A test circuit, system, and method are provided herein for testing one or more circuit components arranged upon a monolithic substrate. According to one embodiment, the system may include a test circuit and one or more circuit components, all of which are arranged upon the same monolithic substrate. In general, the test circuit may be configured for: (i) receiving an input signal at an input frequency, (ii) generating a test signal by modulating a phase of the input signal in accordance with a periodic signal, and (iii) supplying either the input signal or the test signal to the one or more integrated circuits, based on a control signal supplied to the test circuit. More specifically, the test circuit may be used to determine the jitter and/or duty cycle distortion (DCD) tolerance of any system component without changing the frequency of the clock signal supplied to the component or injecting noise into the clock recovery system.
摘要翻译：本文提供了测试电路，系统和方法来测试布置在单片基板上的一个或多个电路组件。根据一个实施例，系统可以包括测试电路和一个或多个电路部件，所有电路部件都布置在相同的单片基板上。通常，测试电路可以被配置为：（i）以输入频率接收输入信号，（ii）通过根据周期信号调制输入信号的相位来产生测试信号，以及（iii）提供基于提供给测试电路的控制信号，将输入信号或测试信号传送到一个或多个集成电路。更具体地，测试电路可用于确定任何系统组件的抖动和/或占空比失真（DCD）容限，而不改变提供给组件的时钟信号的频率或将噪声注入到时钟恢复系统中。

15. 发明授权

US06594325B1 Circuitry, architecture and method(s) for synchronizing data 有权
标题翻译：用于同步数据的电路，架构和方法
公开(公告)号：US06594325B1
公开(公告)日：2003-07-15
申请号：US09392042
申请日：1999-09-08
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： H04L700
CPC分类号： H04L25/14 , G06F5/10 , H04L7/005 , H04L7/02 , H04L7/04 , H04L25/4908
摘要： An apparatus comprising a first programmable circuit configured to present (i) a first parallel data signal and (ii) a first control signal in response to one or more serial data signals and a second programmable circuit configured to generate a second parallel data signal in response to (i) the first parallel data signal, (ii) the first control signal and (iii) a second control signal.
摘要翻译：一种装置，包括第一可编程电路，其被配置为响应于一个或多个串行数据信号呈现（i）第一并行数据信号和（ii）第一控制信号，以及第二可编程电路，其被配置为响应于产生第二并行数据信号（i）第一并行数据信号，（ii）第一控制信号和（iii）第二控制信号。

16. 发明授权

US06222871B1 Vertical optical cavities produced with selective area epitaxy 失效
标题翻译：用选择性面积外延生产的垂直光学腔
公开(公告)号：US06222871B1
公开(公告)日：2001-04-24
申请号：US09337790
申请日：1999-06-22
申请人： Constance Chang-Hasnain , Gabriel Li , Wupen Yuen
发明人： Constance Chang-Hasnain , Gabriel Li , Wupen Yuen
IPC分类号： H01S5183
CPC分类号： H01S5/18358 , H01S5/1057 , H01S5/106 , H01S5/18388 , H01S5/2077 , H01S5/4087 , H01S5/423 , H01S2301/18
摘要： A monolithic vertical optical cavity device built up along a vertical direction. The device has a bottom Distributed Bragg Reflector (DBR), a Quantum Well (QW) region consisting of least one active layer grown on top of the bottom DBR by using a Selective Area Epitaxy (SAE) mask such that the active layer or layers exhibit a variation in at least one physical parameter in a horizontal plane perpendicular to the vertical direction and a top DBR deposited on top of the QW region. A spacer is deposited with or without SAE adjacent the QW region. The device has a variable Fabry-Perot distance defined along the vertical direction between the bottom DBR and the top DBR and a variable physical parameter of the active layer. The varying physical parameter of the active layers is either their surface curvature and/or the band gap and both of these parameters are regulated by SAE. The monolithic vertical cavity device can be used as a Vertical Cavity Surface Emitting Laser (VCSEL) or a Vertical Cavity Detector (VCDET).
摘要翻译：沿垂直方向建立的单片垂直光学腔装置。该器件具有底部分布布拉格反射器（DBR），量子阱（QW）区域，其由通过选择区域外延（SAE）掩模在底部DBR顶部生长的至少一个活性层组成，使得活性层或层显示垂直于垂直方向的水平面中的至少一个物理参数的变化和沉积在QW区域顶部的顶部DBR。隔离层沉积有或没有与邻近QW区域的SAE。该装置具有沿底部DBR和顶部DBR之间的垂直方向限定的可变法布里 - 珀罗距离以及有源层的可变物理参数。活性层的变化的物理参数是它们的表面曲率和/或带隙，并且这些参数都由SAE调节。单片垂直腔装置可用作垂直腔面发射激光器（VCSEL）或垂直腔探测器（VCDET）。

17. 发明授权

US08290109B2 Circuit, system and method for multiplexing signals with reduced jitter 有权
标题翻译：具有减少抖动的信号复用的电路，系统和方法
公开(公告)号：US08290109B2
公开(公告)日：2012-10-16
申请号：US13038028
申请日：2011-03-01
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： H03D3/24
CPC分类号： H04J3/047 , H03K17/002 , H03K19/1737
摘要： An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.
摘要翻译：一种具有多个电源域和多个逻辑部件的装置。多个逻辑组件中的每一个驻留在多个电源域中的不同的一个中。所述多个逻辑部件中的每一个被配置为与所述多个电源域中的相应一个中的对应的时钟信号一起操作。

18. 发明授权

US07330078B1 Apparatus and method for limiting the overshoot and undershoot when turning on the spread spectrum of a reference signal 失效
标题翻译：当开启参考信号的扩展频谱时，限制过冲和下冲的装置和方法
公开(公告)号：US07330078B1
公开(公告)日：2008-02-12
申请号：US11300718
申请日：2005-12-13
申请人： Gabriel Li , Dusan Vecera
发明人： Gabriel Li , Dusan Vecera
IPC分类号： H03L7/06
CPC分类号： H03L7/18
摘要： Disclosed is a circuit, comprising an input spread spectrum enable signal, a crystal oscillator, a first, second and third sampling flip-flop clocked by the crystal oscillator, configured to sample the input spread spectrum enable signal, and a plurality of control output signals derived from or provided directly from the sampling flip-flops. A method of operating the circuit is further described.
摘要翻译：公开了一种电路，包括输入扩频使能信号，晶体振荡器，由晶体振荡器定时的第一，第二和第三采样触发器，被配置为对输入扩频使能信号进行采样，以及多个控制输出信号来自或直接从采样触发器提供。进一步描述操作电路的方法。

19. 发明申请

US20060224910A1 Circuit and method for monitoring the status of a clock signal 有权
标题翻译：用于监视时钟信号状态的电路和方法
公开(公告)号：US20060224910A1
公开(公告)日：2006-10-05
申请号：US11097527
申请日：2005-03-31
申请人： Gabriel Li , Greg Richmond , Sangeeta Raman
发明人： Gabriel Li , Greg Richmond , Sangeeta Raman
IPC分类号： G06F1/00
CPC分类号： H03K5/26 , G01R23/005 , G06F1/12 , H03K5/19
摘要： A circuit and method are provided herein for monitoring the status of a clock signal. In general, the method may include supplying a pair of clock signals to a clock monitor circuit, which is configured for monitoring a status of one clock signal relative to the other. The status indicates whether the frequency of the one clock signal is faster, slower or substantially equal to the frequency of the other clock signal. Once determined, the status may be stored as a bit pattern within a status register, which is operatively coupled to the clock monitor circuit. This enables the status to be read by detecting a logic state of one or more bits within the status register.
摘要翻译：本文提供了一种用于监视时钟信号的状态的电路和方法。通常，该方法可以包括将一对时钟信号提供给时钟监控电路，时钟监视电路被配置为监视相对于另一个时钟信号的一个时钟信号的状态。该状态指示一个时钟信号的频率是否比其他时钟信号的频率更快，更慢或基本上等于其他时钟信号的频率。一旦确定，状态可以作为位模式存储在状态寄存器内，状态寄存器可操作地耦合到时钟监视器电路。这样可以通过检测状态寄存器中的一个或多个位的逻辑状态来读取状态。

20. 发明授权

US06369636B1 Method, architecture and circuit for selecting, calibrating and monitoring circuits 失效
标题翻译：选择，校准和监控电路的方法，架构和电路
公开(公告)号：US06369636B1
公开(公告)日：2002-04-09
申请号：US09468171
申请日：1999-12-21
申请人： Gabriel Li
发明人： Gabriel Li
IPC分类号： H03K1776
CPC分类号： G01R31/31853 , G01R31/318525 , G11C2029/5002
摘要： A circuit including a plurality of first calibration circuits, a second circuit and a third circuit. The plurality of calibration circuits may each be configured to present a calibration signal. The second circuit may be configured to select one of the calibration signals in response to a plurality of configuration signals. The third circuit may be configured to generate a control signal in response to (i) a reference signal and (ii) the selected calibration signal.
摘要翻译：一种包括多个第一校准电路，第二电路和第三电路的电路。多个校准电路可以各自被配置为呈现校准信号。第二电路可以被配置为响应于多个配置信号来选择一个校准信号。第三电路可以被配置为响应于（i）参考信号和（ii）所选择的校准信号而产生控制信号。

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