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11. 发明授权

US08139069B1 Method and system for improving data coherency in a parallel rendering system 有权
标题翻译：用于提高并行渲染系统中数据一致性的方法和系统
公开(公告)号：US08139069B1
公开(公告)日：2012-03-20
申请号：US11556660
申请日：2006-11-03
申请人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
发明人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
IPC分类号： G06F15/80
CPC分类号： G06T15/005 , G06F9/522 , G06T2210/52
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method for managing a plurality of independently processed texture streams in a parallel rendering system that includes the steps of maintaining a time stamp for a group of tiles of work that are associated with each of the plurality of the texture streams and are associated with a specified area in screen space, and utilizing the time stamps to counter divergences in the independent processing of the plurality of texture streams.
摘要翻译：公开了一种用于提高并行渲染系统中数据一致性的方法和系统。具体地，本发明的一个实施例阐述了一种用于在并行渲染系统中管理多个独立处理的纹理流的方法，该方法包括以下步骤：维护与多个相关联的工作的一组瓦片的时间戳的纹理流并且与屏幕空间中的指定区域相关联，并且利用时间戳来反复在多个纹理流的独立处理中的分歧。

12. 发明申请

US20120026171A1 PARALLEL ARRAY ARCHITECTURE FOR A GRAPHICS PROCESSOR 有权
标题翻译：图形处理器的并行阵列架构
公开(公告)号：US20120026171A1
公开(公告)日：2012-02-02
申请号：US13269462
申请日：2011-10-07
申请人： John M. Danskin , John S. Montrym , John Erik Lindholm , Steven E. Molnar , Mark French
发明人： John M. Danskin , John S. Montrym , John Erik Lindholm , Steven E. Molnar , Mark French
IPC分类号： G06T15/50
CPC分类号： G06T15/005 , G06T2210/52 , G09G5/363 , G09G5/393 , G09G2360/06 , G09G2360/122
摘要： A parallel array architecture for a graphics processor includes a multithreaded core array including a plurality of processing clusters, each processing cluster including at least one processing core operable to execute a pixel shader program that generates pixel data from coverage data; a rasterizer configured to generate coverage data for each of a plurality of pixels; and pixel distribution logic configured to deliver the coverage data from the rasterizer to one of the processing clusters in the multithreaded core array. A crossbar coupled to each of the processing clusters is configured to deliver pixel data from the processing clusters to a frame buffer having a plurality of partitions.
摘要翻译：用于图形处理器的并行阵列架构包括包括多个处理簇的多线程核心阵列，每个处理簇包括至少一个可操作以执行从覆盖数据生成像素数据的像素着色器程序的处理核心; 光栅化器，被配置为生成多个像素中的每一个的覆盖数据; 以及像素分布逻辑，被配置为将覆盖数据从光栅化器传送到多线程核心阵列中的处理集群之一。耦合到每个处理集群的交叉开关被配置为将像素数据从处理集群传送到具有多个分区的帧缓冲器。

13. 发明授权

US08040349B1 System and method for structuring an A-buffer 有权
标题翻译：用于构建A缓冲区的系统和方法
公开(公告)号：US08040349B1
公开(公告)日：2011-10-18
申请号：US11950355
申请日：2007-12-04
申请人： John M. Danskin
发明人： John M. Danskin
IPC分类号： G06T15/00
CPC分类号： G06T15/005 , G06T11/40 , G06T15/503
摘要： One embodiment of the present invention sets forth a technique for efficiently creating and accessing an A-Buffer with a GPU. The A-Buffer is organized in arrays of uniformly-sized tiles. Each array represents a group of pixels, and each tile within an array includes the set of fragments at a specific depth complexity that are associated with the pixels in the pixel group represented by the array. The size of the tiles may be selected to be the minimum necessary for efficient memory access. The GPU determines the number of tiles in each array by calculating the maximum of the depth complexity associated with the pixels in the pixel group represented by the array and creates a corresponding prefix sum image to allow the GPU to efficiently locate the array associated with a given pixel group in the A-Buffer for addressing purposes. Advantageously, structuring the A-Buffer by both pixel proximity and depth complexity improves memory locality, thereby improving the overall rendering performance of the graphics pipeline.
摘要翻译：本发明的一个实施例提出了一种用于有效地创建和访问具有GPU的A缓冲器的技术。 A缓冲区以均匀尺寸的瓦片阵列组织。每个阵列表示一组像素，并且阵列中的每个片段包括与由阵列表示的像素组中的像素相关联的特定深度复杂度的片段集合。可以将瓦片的尺寸选择为有效存储器访问所需的最小值。 GPU通过计算与由阵列表示的像素组中的像素相关联的深度复杂度的最大值来确定每个阵列中的瓦片的数量，并且创建相应的前缀和图像以允许GPU有效地定位与给定的相关联的阵列 A缓冲区中的像素组用于寻址目的。有利地，通过像素接近度和深度复杂度来构造A缓冲器改善了存储器位置，从而提高了图形管线的整体渲染性能。

14. 发明授权

US07979683B1 Multiple simultaneous context architecture 有权
标题翻译：多个同时上下文体系结构
公开(公告)号：US07979683B1
公开(公告)日：2011-07-12
申请号：US11696928
申请日：2007-04-05
申请人： John M. Danskin , John Erik Lindholm
发明人： John M. Danskin , John Erik Lindholm
IPC分类号： G06F9/40
CPC分类号： G06F9/461 , G06T1/00
摘要： Graphics processing elements are capable of processing multiple contexts simultaneously, reducing the need to perform time consuming context switches compared with processing a single context at a time. Processing elements of a graphics processing pipeline may be configured to support all of the multiple contexts or only a portion of the multiple contexts. Each processing element may be allocated to process a particular context or a portion of the multiple contexts in order to simultaneously process more than one context. The allocation of processing elements to the multiple contexts may be determined dynamically in order to improve graphics processing throughput.
摘要翻译：与一次处理单个上下文相比，图形处理元件能够同时处理多个上下文，减少了执行耗时的上下文切换的需要。图形处理流水线的处理元件可以被配置为支持多个上下文中的所有或上述多个上下文的一部分。可以分配每个处理元件以处理特定上下文或多个上下文的一部分，以便同时处理多于一个上下文。可以动态地确定处理元件到多个上下文的分配，以便提高图形处理吞吐量。

15. 发明申请

US20070268298A1 Delayed frame buffer merging with compression 审中-公开
标题翻译：延迟帧缓冲区与压缩合并
公开(公告)号：US20070268298A1
公开(公告)日：2007-11-22
申请号：US11804025
申请日：2007-05-15
申请人： Jonah M. Alben , John M. Danskin , Henry P. Moreton
发明人： Jonah M. Alben , John M. Danskin , Henry P. Moreton
IPC分类号： G06T1/60
CPC分类号： G06T1/60 , G06T15/005
摘要： A method for delayed frame buffer merging. The method includes accessing a polygon that relates to a group of pixels stored at a memory location, wherein each of the pixels has an existing color. A determination is made as to which of the pixels are covered by the polygon, wherein each pixel includes a plurality of samples. A coverage mask is generated corresponding the samples that are covered by the polygon. The group of pixels is updated by storing the coverage mask and a color of the polygon in the memory location. At a subsequent time, the group of pixels is merged into a frame buffer.
摘要翻译：一种用于延迟帧缓冲区合并的方法。该方法包括访问与存储在存储器位置处的一组像素相关的多边形，其中每个像素具有现有颜色。确定哪个像素被多边形覆盖，其中每个像素包括多个样本。生成对应于多边形所覆盖的样本的覆盖掩码。通过将覆盖掩码和多边形的颜色存储在存储器位置中来更新像素组。在随后的时间，像素组被合并成帧缓冲器。

16. 发明授权

US06980208B1 System and method for enhancing depth value processing in a graphics pipeline 有权
标题翻译：用于在图形管线中增强深度值处理的系统和方法
公开(公告)号：US06980208B1
公开(公告)日：2005-12-27
申请号：US10234977
申请日：2002-09-03
申请人： John Montrym , Jonah M. Alben , Sean Treichler , John M. Danskin , Gary Tarolli
发明人： John Montrym , Jonah M. Alben , Sean Treichler , John M. Danskin , Gary Tarolli
IPC分类号： G06T15/00
CPC分类号： G06T15/005
摘要： A system, method and computer program product are provided for performing depth testing and blending operations in a first mode and a second mode. In the first mode, a circuit processes a first number (m) of first pixels per clock cycle, each of the first pixels including both color values and depth values. In the second mode, the circuit processes a second number (n) of second pixels per clock cycle. Each of the second pixels includes the depth values and not the color values. Further, the second number (n) is greater than the first number (m).
摘要翻译：提供了一种用于在第一模式和第二模式下执行深度测试和混合操作的系统，方法和计算机程序产品。在第一模式中，电路处理每个时钟周期的第一数量（m）的第一像素，每个第一像素包括颜色值和深度值。在第二模式中，电路处理每个时钟周期的第二数量（n）个第二像素。每个第二像素包括深度值而不是颜色值。此外，第二数（n）大于第一数（m）。

17. 发明授权

US08553041B1 System and method for structuring an A-buffer to support multi-sample anti-aliasing 有权
标题翻译：用于构造A缓冲区以支持多样本抗锯齿的系统和方法
公开(公告)号：US08553041B1
公开(公告)日：2013-10-08
申请号：US12208211
申请日：2008-09-10
申请人： John M. Danskin
发明人： John M. Danskin
IPC分类号： G06T1/60
CPC分类号： G06T9/00 , G06T15/005 , G06T2210/08
摘要： One embodiment of the present invention sets forth a technique for efficiently creating and accessing an A-Buffer that supports multi-sample compression techniques. The A-Buffer is organized in stacks of uniformly-sized tiles, wherein the tile size is selected to facilitate compression techniques. Each stack represents the samples included in a group of pixels. Each tile within a stack represents the set of sample data at a specific per-sample rendering order index that are associated with the group of pixels represented by the stack. Advantageously, each tile includes tile compression bits that enable the tile to maintain data using existing compression formats. As the A-Buffer is created, a corresponding stack compression buffer is also created. For each stack, the stack compression buffer includes a bit that indicates whether all of the tiles in the stack are similarly compressed and, consequently, whether the GPU may operate on the stack at an efficient per pixel granularity.
摘要翻译：本发明的一个实施例提出了一种用于有效地创建和访问支持多样本压缩技术的A缓冲器的技术。 A缓冲器以均匀尺寸的瓦片的堆叠组织，其中选择瓦片尺寸以便于压缩技术。每个堆栈表示包含在一组像素中的样本。堆栈中的每个瓦片表示与由堆栈表示的像素组相关联的特定每样本渲染顺序索引处的采样数据集合。有利地，每个瓦片包括瓦片压缩比特，使得瓦片能够使用现有的压缩格式来维护数据。当创建A缓冲区时，也会创建相应的堆栈压缩缓冲区。对于每个堆栈，堆栈压缩缓冲器包括指示堆栈中的所有瓦片是否被类似地压缩的位，并且因此，GPU是否可以以每像素粒度有效地在堆栈上操作。

18. 发明申请

US20120147027A1 METHOD AND SYSTEM FOR IMPROVING DATA COHERENCY IN A PARALLEL RENDERING SYSTEM 有权
标题翻译：用于提高并行渲染系统中的数据相关性的方法和系统
公开(公告)号：US20120147027A1
公开(公告)日：2012-06-14
申请号：US13399458
申请日：2012-02-17
申请人： Steven E. MOLNAR , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
发明人： Steven E. MOLNAR , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G06F9/522 , G06T2210/52
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method for managing a plurality of independently processed texture streams in a parallel rendering system that includes the steps of maintaining a time stamp for a group of tiles of work that are associated with each of the plurality of the texture streams and are associated with a specified area in screen space, and utilizing the time stamps to counter divergences in the independent processing of the plurality of texture streams.
摘要翻译：公开了一种用于提高并行渲染系统中数据一致性的方法和系统。具体地，本发明的一个实施例阐述了一种用于在并行渲染系统中管理多个独立处理的纹理流的方法，该方法包括以下步骤：维护与多个相关联的工作的一组瓦片的时间戳的纹理流并且与屏幕空间中的指定区域相关联，并且利用时间戳来反复在多个纹理流的独立处理中的分歧。

19. 发明授权

US08085272B1 Method and system for improving data coherency in a parallel rendering system 有权
标题翻译：用于提高并行渲染系统中数据一致性的方法和系统
公开(公告)号：US08085272B1
公开(公告)日：2011-12-27
申请号：US11556657
申请日：2006-11-03
申请人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin , Adam Clark Weitkemper , Mark J. French
发明人： Steven E. Molnar , Cass W. Everitt , Roger L. Allen , Gary M. Tarolli , John M. Danskin , Adam Clark Weitkemper , Mark J. French
IPC分类号： G06F15/80
CPC分类号： G06T15/005
摘要： A method and system for improving data coherency in a parallel rendering system is disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of receiving a common input stream, tracking a periodic event associated with the common input stream, generating a plurality of fragment streams from the common input stream, inserting a marker based on an occurrence of the periodic event in a first fragment stream in the multiple fragment streams, and utilizing the marker to influence the processing of the first fragment stream so that a plurality of raster operation (ROP) request streams maintains substantially the same coherence as the common input stream. Each fragment stream is independently processed and corresponds to one of the ROP request streams.
摘要翻译：公开了一种用于提高并行渲染系统中数据一致性的方法和系统。具体地，本发明的一个实施例阐述了一种方法，其包括以下步骤：接收公共输入流，跟踪与公共输入流相关联的周期性事件，从公共输入流生成多个片段流，插入标记基于所述多个片段流中的第一片段流中的所述周期性事件的发生，并且利用所述标记来影响所述第一片段流的处理，使得多个光栅操作（ROP）请求流保持基本相同的一致性公共输入流。每个片段流被独立地处理并对应于其中一个ROP请求流。

20. 发明授权

US07965895B1 Screen compression 有权
标题翻译：屏幕压缩
公开(公告)号：US07965895B1
公开(公告)日：2011-06-21
申请号：US11837336
申请日：2007-08-10
申请人： John M. Danskin , Ziyad S. Hakura , Edward L. Riegelsberger , Jason M. Musicer , Stephen D. Lew
发明人： John M. Danskin , Ziyad S. Hakura , Edward L. Riegelsberger , Jason M. Musicer , Stephen D. Lew
IPC分类号： G06K9/36 , G06K9/46
CPC分类号： G09G5/397 , G09G5/393 , G09G2340/02 , G09G2340/12 , G09G2360/122 , H04N19/428 , H04N19/593
摘要： Methods, circuits, and apparatus for reducing memory bandwidth used by a graphics processor. Uncompressed tiles are read from a display buffer portion of a graphics memory and received by an encoder. The uncompressed tiles are compressed and written back to the graphics memory. When a tile is needed again before it has been modified, the compressed version is read from memory, uncompressed, and displayed. To reduce the number of unnecessary writes of compressed tiles to memory, a tile is only written to memory if it has remained static for some number of refresh cycles. Also, to prevent a large number of compressed tiles being written to the display buffer in one refresh cycle, the encoder can be throttled after a number of tiles have been written. Validity information can be stored for use by a CRTC. If a tile is updated, the validity information is updated such that invalid compressed data is not read from memory and displayed.
摘要翻译：用于减少由图形处理器使用的存储器带宽的方法，电路和装置。未压缩的瓦片从图形存储器的显示缓冲器部分读取并由编码器接收。未压缩的瓦片被压缩并写回图形存储器。在修改瓦片之前，再次需要一个瓦片时，从内存中读取压缩版本，解压缩并显示。为了将压缩瓦片的不必要的写入数量减少到存储器，如果在一些刷新周期内保持静态，则瓦片仅写入存储器。此外，为了防止在一个刷新周期中将大量的压缩瓦片写入显示缓冲器，编码器可以在写入多个瓦片之后被节流。有效信息可以存储供CRTC使用。如果更新瓦片，则更新有效性信息，使得无法从存储器读取无效的压缩数据并显示。

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