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    • 13. 发明申请
    • Gain adjust for SAR ADC
    • 增益调整为SAR ADC
    • US20070001890A1
    • 2007-01-04
    • US11170591
    • 2005-06-29
    • Douglas PiaseckiMichael Odland
    • Douglas PiaseckiMichael Odland
    • H03M1/38
    • H03M1/186H03M1/403
    • A SAR analog-to-digital Converter (ADC) is disclosed with variable gain having a SAR capacitor array with a plurality of switched capacitors therein with varying weights and a SAR controller for sampling an input voltage thereon in a sampling phase, and redistributing the charge stored thereon in a conversion phase in accordance with a SAR conversion algorithm. A gain adjust register is provided for defining an amount of charge to be added or subtracted from the capacitor array prior to the conversion phase relative to a predetermined amount of charge. A charge control device varies the amount of charge stored in the array prior to the conversion phase in accordance with the contents of the gain adjust register such that the amount of charge redistributed during the conversion phase is adjusted.
    • 公开了具有可变增益的SAR模数转换器(ADC),其具有其中具有变化权重的多个开关电容器的SAR电容器阵列和用于在采样阶段对其上的输入电压进行采样的SAR控制器,并且重新分配电荷 根据SAR转换算法在转换阶段存储。 提供增益调整寄存器,用于定义在相对于预定量的电荷的转换阶段之前要从电容器阵列加或减去的电荷量。 充电控制装置根据增益调整寄存器的内容改变在转换阶段之前存储在阵列中的电荷量,使得在转换阶段期间重新分配的电荷量被调整。
    • 14. 发明申请
    • MIXED SIGNAL PROCESSOR WITH NOISE MANAGEMENT
    • 具有噪声管理的混合信号处理器
    • US20050219086A1
    • 2005-10-06
    • US10816262
    • 2004-03-31
    • Douglas PiaseckiKa Leung
    • Douglas PiaseckiKa Leung
    • H03M1/00H03M1/06H03M1/08
    • H03M1/0872
    • Mixed signal processor with noise management. A method for noise management in a mixed signal processor integrated circuit having a digital processing section and an analog section The digital processing section is clocked at a first clock rate to process digital data. When a conversion operation is to be carried out by the analog section, the clocking of the digital processing section is inhibited during at least a portion of the data conversion operation by the analog section to prevent noise from clock transitions in the digital processing section from being injected into the analog section during the at least a portion of th data conversion operation.
    • 具有噪声管理的混合信号处理器。 一种具有数字处理部分和模拟部分的混合信号处理器集成电路中的噪声管理方法数字处理部分以第一时钟速率被计时以处理数字数据。 当要由模拟部分执行转换操作时,数字处理部分的时钟在模拟部分的数据转换操作的至少一部分期间被禁止,以防止数字处理部分中的时钟转换的噪声成为 在数据转换操作的至少一部分期间注入模拟部分。
    • 17. 发明授权
    • Precision oscillator having linbus capabilities
    • 具有linbus功能的精密振荡器
    • US07504902B2
    • 2009-03-17
    • US11618581
    • 2006-12-29
    • Douglas PiaseckiDouglas Holberg
    • Douglas PiaseckiDouglas Holberg
    • H03L1/04G06F1/00
    • H03K3/0231H03K3/356113H03K5/2481
    • The integrated system on a chip with LINBUS network communication capabilities includes processing circuitry for performing predefined digital processing functionalities on the chip. A free running clock circuit generates a temperature compensated clock that does not require a synch signal from external to the chip. A LINBUS network communications interface digitally communicates with off-chip LINBUS devices. Communication between said on-chip LINBUS communications interface and the off-chip LINBUS devices is affected without clock recovery. The LINBUS network communication interface has a time base derived from the temperature compensated clock which is independent of any timing information in the input data received during a receive operation. The temperature compensated clock further provides an on-chip time reference for both the processing circuitry and the LINBUS network communications interface.
    • 具有LINBUS网络通信能力的芯片上的集成系统包括用于在芯片上执行预定义的数字处理功能的处理电路。 自由运行的时钟电路产生温度补偿时钟,不需要来自芯片外部的同步信号。 LINBUS网络通信接口与片外LINBUS设备进行数字通信。 所述片上LINBUS通信接口和片外LINBUS器件之间的通信不受时钟恢复的影响。 LINBUS网络通信接口具有从温度补偿时钟导出的时基,其独立于在接收操作期间接收的输入数据中的任何定时信息。 温度补偿时钟还为处理电路和LINBUS网络通信接口提供片上时间参考。
    • 20. 发明授权
    • Method for search and matching of capacitors for a digital to analog converter of an SAR analog to digital converter
    • SAR模数转换器的数模转换器的电容搜索和匹配方法
    • US07199746B1
    • 2007-04-03
    • US11311508
    • 2005-12-19
    • Golam R. ChowdhuryDouglas Piasecki
    • Golam R. ChowdhuryDouglas Piasecki
    • H03M1/12
    • H03M1/468H03M1/0673H03M1/682
    • The method is described for selecting capacitors from a capacitor array for each bit of a SAR ADC. The process involves selecting a group of capacitors from the capacitor array and determining a weight of the selected group of capacitors. A determination is made if the weights of the selected group of capacitors are substantially equal to their desired values. If the weights are substantially equal to their desired values, the selected group of capacitors is associated with each bit of the SAR ADC. If the weights are not substantially equal to their desired values, a next group of capacitors from the capacitor array is selected for the bits. This process of selecting a group of capacitors and determining their weights is repeated until determined weight for a group of capacitors equals or is closest to the desired values.
    • 描述了用于从SAR ADC的每个位的电容器阵列中选择电容器的方法。 该过程涉及从电容器阵列中选择一组电容器并确定所选择的电容器组的重量。 如果所选择的电容组的权重基本上等于其所需的值,则确定。 如果权重基本上等于其所需值,则所选择的电容组与SAR ADC的每个位相关联。 如果权重基本上不等于其所需值,则选择来自电容器阵列的下一组电容器用于该位。 重复选择一组电容器并确定它们的权重的该过程,直到一组电容器的确定的重量等于或最接近所需值。