专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US06673635B1 Method for alignment mark formation for a shallow trench isolation process 有权
标题翻译：浅沟槽隔离工艺的对准标记形成方法
公开(公告)号：US06673635B1
公开(公告)日：2004-01-06
申请号：US10185780
申请日：2002-06-28
申请人： Kay Hellig , Douglas J. Bonser , Srikanteswara Dakshina-Murthy
发明人： Kay Hellig , Douglas J. Bonser , Srikanteswara Dakshina-Murthy
IPC分类号： H01L2100
CPC分类号： H01L23/544 , H01L21/30604 , H01L21/3083 , H01L21/31116 , H01L21/31144 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Methods are presented for fabrication of alignment features of a desired depth, and shallow trench isolation (STI) features in Silicon-On-Insulator (SOI) material. Specific embodiments require no more than two lithography and etch processes, which represents an improvement over current methodology requiring three lithography and etch processes in order to produce the desired features during manufacture of a semiconductor device.
摘要翻译：提出了用于制造所需深度的对准特征以及绝缘体上硅（SOI）材料中的浅沟槽隔离（STI）特征的方法。具体实施方案要求不超过两个光刻和蚀刻工艺，其代表了需要三次光刻和蚀刻工艺的电流方法的改进，以便在制造半导体器件期间产生期望的特征。

12. 发明授权

US07223698B1 Method of forming a semiconductor arrangement with reduced field-to active step height 失效
标题翻译：形成具有减小的场到活动台阶高度的半导体装置的方法
公开(公告)号：US07223698B1
公开(公告)日：2007-05-29
申请号：US11053910
申请日：2005-02-10
申请人： Douglas J. Bonser , Srikanteswara Dakshina-Murthy , Mark C. Kelling , John G. Pellerin , Johannes F. Groschopf , Edward Asuka Nomura
发明人： Douglas J. Bonser , Srikanteswara Dakshina-Murthy , Mark C. Kelling , John G. Pellerin , Johannes F. Groschopf , Edward Asuka Nomura
IPC分类号： H01L21/311
CPC分类号： H01L21/76232
摘要： A method of forming a shallow trench isolation (STI) region in a silicon substrate creates an STI region that extends above a top surface of the silicon substrate. A planarizing dielectric layer is formed on the substrate and extends above the field oxide regions. The planarizing dielectric layer is removed by chemical mechanical polishing or blanket etch back, for example, as well as those portions of the field oxide regions that extend above the top surface of the substrate and the active regions. The step height is thereby eliminated or significantly reduced.
摘要翻译：在硅衬底中形成浅沟槽隔离（STI）区域的方法产生在硅衬底的顶表面上方延伸的STI区域。在基板上形成平坦化介质层，并在场氧化物区域上方延伸。平面化电介质层通过化学机械抛光或覆盖层回蚀除去，例如，以及在衬底的顶表面和活性区上延伸的场氧化物区域的那些部分。从而消除或显着降低台阶高度。

13. 发明授权

US07091106B2 Method of reducing STI divot formation during semiconductor device fabrication 有权
标题翻译：在半导体器件制造期间减少STI纹路形成的方法
公开(公告)号：US07091106B2
公开(公告)日：2006-08-15
申请号：US10791759
申请日：2004-03-04
申请人： Douglas J. Bonser , Johannes F. Groschopf , Srikanteswara Dakshina-Murthy , John G. Pellerin , Jon D. Cheek
发明人： Douglas J. Bonser , Johannes F. Groschopf , Srikanteswara Dakshina-Murthy , John G. Pellerin , Jon D. Cheek
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer, e.g., no thicker than 400 Å. The very thin nitride polish stop layer is retained in place during subsequent masking, implanting and cleaning steps to form dopant regions, and is removed prior to gate oxide and gate electrode formation.
摘要翻译：通过使用非常薄的氮化物抛光停止层（例如不厚于400）来消除或显着降低STI形成。非常薄的氮化物抛光停止层在随后的掩模，注入和清洁步骤中保持就位以形成掺杂剂区域，并且在栅极氧化物和栅电极形成之前被去除。

14. 发明授权

US06979651B1 Method for forming alignment features and back-side contacts with fewer lithography and etch steps 有权
标题翻译：用较少光刻和蚀刻步骤形成对准特征和背面接触的方法
公开(公告)号：US06979651B1
公开(公告)日：2005-12-27
申请号：US10207653
申请日：2002-07-29
申请人： Kay Hellig , Douglas J. Bonser , Srikanteswara Dakshina-Murthy
发明人： Kay Hellig , Douglas J. Bonser , Srikanteswara Dakshina-Murthy
IPC分类号： H01L21/308 , H01L21/311 , H01L21/762 , H01L23/544
CPC分类号： H01L21/76264 , H01L21/3081 , H01L21/31144 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： The method performs a first photolithography and etch to form shallow trench isolation features and alignment mark features into the top SOI layer. The shallow trenches are then filled with a dielectric material to form the isolation. A second lithography and etch step is then applied to etch the window locations for back-side contacts, and to transfer the alignment marks down into the SOI lower substrate. After this first lithography and etch step, the alignment marks in the top silicon may be used for alignment of the second lithography mask and etch. This is made possible by leaving the polish stop layer on the wafer, which serves to increase the optically effective thickness of the alignment mark pattern. The polish stop layer is removed after the second etch process. The teachings can be applied to any Semiconductor-On-Insulator-type wafer/technology where the top semiconductor layer is not thicker than the optimum alignment mark depth.
摘要翻译：该方法执行第一次光刻和蚀刻，以将浅沟槽隔离特征和对准标记特征形成到顶部SOI层中。然后用介电材料填充浅沟槽以形成隔离。然后施加第二光刻和蚀刻步骤以蚀刻用于背面接触的窗口位置，并将对准标记向下转移到SOI下基板中。在该第一光刻和蚀刻步骤之后，顶部硅中的对准标记可用于对准第二光刻掩模和蚀刻。这可以通过将抛光停止层留在晶片上来实现，其用于增加对准标记图案的光学有效厚度。在第二次蚀刻工艺之后去除抛光停止层。该教导可以应用于任何半导体绝缘体型晶片/技术，其中顶部半导体层不比最佳对准标记深度厚。

15. 发明授权

US06812077B1 Method for patterning narrow gate lines 失效
标题翻译：窄栅极线图案的制作方法
公开(公告)号：US06812077B1
公开(公告)日：2004-11-02
申请号：US10299433
申请日：2002-11-19
申请人： Darin Chan , Douglas J. Bonser , Mark S. Chang
发明人： Darin Chan , Douglas J. Bonser , Mark S. Chang
IPC分类号： H01L2100
CPC分类号： H01L21/32105 , H01L21/28088 , H01L21/28123
摘要： Patterning of a gate line is terminated prior to etching completely through the conductive layer from which it is patterned. Surfaces of the conductive layer are then reacted in a reactive atmosphere, and the reacted surfaces are removed, creating a narrow gate line. The protection provided by the remaining portion of the conductive layer during reaction protects the lower corners of the patterned feature from undercutting growth of reacted material. Alternatively, a gate line is patterned from a multi-layered conductive structure that includes a lower conductive layer and an upper conductive layer that exhibits higher reactivity in a reactive atmosphere than the lower layer. The upper layer is patterned and then the structure is reacted in the reactive atmosphere. Reacted portions of the upper layer are then removed and the lower layer is patterned in a self-aligned manner to complete the formation of a gate line and gate insulator.
摘要翻译：在蚀刻完全通过图案化的导电层之前终止栅极线的图案化。然后在反应性气氛中使导电层的表面反应，除去反应的表面，产生窄的栅极线。在反应期间由导电层的剩余部分提供的保护保护图案化特征的下角部不被反应材料的底切生长。或者，栅极线从包括下导电层和上导电层的多层导电结构图案化，反应性气氛中的反应性比下层高。上层被图案化，然后结构在反应性气氛中反应。然后去除上层的反应部分，并且以自对准方式图案化下层，以完成栅极线和栅极绝缘体的形成。

16. 发明授权

US06555397B1 Dry isotropic removal of inorganic anti-reflective coating after poly gate etching 有权
标题翻译：多栅极蚀刻后无机抗反射涂层的干均匀去除
公开(公告)号：US06555397B1
公开(公告)日：2003-04-29
申请号：US09660723
申请日：2000-09-13
申请人： Douglas J. Bonser , Matthew Purdy , James H. Hussey, Jr.
发明人： Douglas J. Bonser , Matthew Purdy , James H. Hussey, Jr.
IPC分类号： H01L2128
CPC分类号： H01L21/28123 , Y10S438/952
摘要： Various methods of fabricating a conductor structure are provided. In one aspect, a method of fabricating a conductor structure on a first workpiece is provided. A silicon film is formed on the first workpiece. An anti-reflective coating is formed on the silicon film. A mask is formed on a first portion of the anti-reflective coating, while a second portion thereof is left unmasked. The second portion of the anti-reflective coating and the silicon film are etched. The mask is removed, and the anti-reflective coating is removed by isotropic plasma etching. Use of isotropic etching for anti-reflective coating removal eliminates thermal shock associated with heated acid bath anti-reflective coating removal.
摘要翻译：提供制造导体结构的各种方法。一方面，提供了在第一工件上制造导体结构的方法。在第一工件上形成硅膜。在硅膜上形成抗反射涂层。掩模形成在防反射涂层的第一部分上，而其第二部分未被掩蔽。抗反射涂层和硅膜的第二部分被蚀刻。除去掩模，并通过各向同性等离子体蚀刻除去抗反射涂层。使用各向同性蚀刻进行抗反射涂层去除消除了与加热的酸浴反射涂层去除相关的热冲击。

17. 发明授权

US06734088B1 Control of two-step gate etch process 失效
标题翻译：控制两步栅蚀刻工艺
公开(公告)号：US06734088B1
公开(公告)日：2004-05-11
申请号：US09661536
申请日：2000-09-14
申请人： Matthew Purdy , Scott G. Bushman , James H. Hussey, Jr. , Douglas J. Bonser
发明人： Matthew Purdy , Scott G. Bushman , James H. Hussey, Jr. , Douglas J. Bonser
IPC分类号： H01L213205
CPC分类号： H01L22/20 , H01L21/28035
摘要： The present invention is directed to a method of controlling an etching process used to form a gate electrode on a semiconductor device. In one embodiment, the method comprises forming a layer of silicon dioxide above a semiconducting substrate, and forming a layer of polysilicon above the layer of silicon dioxide. The method further comprises sensing a thickness of the layer of polysilicon and adjusting, based upon the sensed thickness of said layer of polysilicon, at least one parameter of an etching process to be performed on said layer of polysilicon to define a gate electrode of a transistor, said etching process comprised of at least a timed etch process and an endpoint etch process.
摘要翻译：本发明涉及一种控制用于在半导体器件上形成栅电极的蚀刻工艺的方法。在一个实施例中，该方法包括在半导体衬底上形成二氧化硅层，并在二氧化硅层之上形成多晶硅层。该方法还包括感测多晶硅层的厚度，并且基于感测到的所述多晶硅层的厚度调整要在所述多晶硅层上执行的蚀刻工艺的至少一个参数，以限定晶体管的栅电极所述蚀刻工艺至少包括定时蚀刻工艺和端蚀刻工艺。

18. 发明授权

US5504328A Endpoint detection utilizing ultraviolet mass spectrometry 失效
标题翻译：使用紫外线质谱法进行端点检测
公开(公告)号：US5504328A
公开(公告)日：1996-04-02
申请号：US352579
申请日：1994-12-09
申请人： Douglas J. Bonser
发明人： Douglas J. Bonser
IPC分类号： H01J49/16 , H01J49/00
CPC分类号： H01J49/16
摘要： An apparatus and method for detecting the endpoint of an etch during semiconductor fabrication is provided. The endpoint detection system utilizes a mass spectrometer having an energy source located outside the vacuum chamber of the endpoint detection system, thus providing an easily replaceable energy source. The energy source may be a light source to provide photo-ionization. The energy source may be selected based upon the gas species of the etch of which an endpoint as being detected. The energy is directed into an ionization chamber of the endpoint detection system through a transparent window.
摘要翻译：提供了一种用于在半导体制造期间检测蚀刻的端点的装置和方法。端点检测系统利用具有位于端点检测系统的真空室外部的能量源的质谱仪，从而提供容易替换的能量源。能量源可以是提供光电离的光源。能量源可以基于被检测到的端点的蚀刻的气体种类来选择。能量通过透明窗口引导到端点检测系统的电离室。

19. 发明申请

US20100267237A1 METHODS FOR FABRICATING FINFET SEMICONDUCTOR DEVICES USING ASHABLE SACRIFICIAL MANDRELS 审中-公开
标题翻译：使用可靠的SACRIFICIC MANDRELS制造FINFET半导体器件的方法
公开(公告)号：US20100267237A1
公开(公告)日：2010-10-21
申请号：US12426824
申请日：2009-04-20
申请人： Douglas J. Bonser , Frank S. Johnson , Catherine B. Labelle
发明人： Douglas J. Bonser , Frank S. Johnson , Catherine B. Labelle
IPC分类号： H01L21/308
CPC分类号： H01L21/3086 , H01L29/66795
摘要： Methods are provided for fabricating a semiconductor device on and in a semiconductor substrate. In accordance with an exemplary embodiment of the invention, one method comprises forming a sacrificial mandrel overlying the substrate, the sacrificial mandrel having sidewalls. Sidewall spacers are formed adjacent the sidewalls of the sacrificial mandrel. The sacrificial mandrel is removed using an ashing process, and the substrate is etched using the sidewall spacers as an etch mask after removal of the sacrificial mandrel.
摘要翻译：提供了用于在半导体衬底上和半导体衬底中制造半导体器件的方法。根据本发明的示例性实施例，一种方法包括形成覆盖在基底上的牺牲心轴，牺牲心轴具有侧壁。侧壁间隔件邻近牺牲心轴的侧壁形成。使用灰化处理去除牺牲心轴，并且在去除牺牲心轴之后，使用侧壁间隔物作为蚀刻掩模蚀刻衬底。

20. 发明授权

US06309947B1 Method of manufacturing a semiconductor device with improved isolation region to active region topography 失效
标题翻译：制造具有改善的隔离区域到有源区域形貌的半导体器件的方法
公开(公告)号：US06309947B1
公开(公告)日：2001-10-30
申请号：US08944314
申请日：1997-10-06
申请人： Basab Bandyopadhyay , Douglas J. Bonser
发明人： Basab Bandyopadhyay , Douglas J. Bonser
IPC分类号： H01L21762
CPC分类号： H01L21/76224
摘要： A method of making a semiconductor device with improved isolation region to active region topography includes forming a masking layer on a surface of a substrate. A portion of the masking layer is removed to define one or more field regions and at least one trench is formed in the one or more field regions. An oxide layer is formed which substantially fills the trench and then a portion of the oxide layer is removed to leave the oxide layer with a relatively planar surface that is recessed with respect to the masking layer. The masking layer is then removed to expose the substrate. There may be a height differential between the substrate surface and the relatively planer surface of the oxide layer, however, the height differential is substantially less than the thickness of the masking layer.
摘要翻译：制造具有改善的隔离区域到有源区域形貌的半导体器件的方法包括在衬底的表面上形成掩模层。去除掩模层的一部分以限定一个或多个场区域，并且在一个或多个场区域中形成至少一个沟槽。形成氧化物层，其基本上填充沟槽，然后去除氧化物层的一部分以使氧化物层具有相对于掩模层凹陷的相对平坦的表面。然后去除掩模层以露出衬底。在衬底表面和氧化物层的相对平坦的表面之间可能存在高度差，然而，高差大大小于掩模层的厚度。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式