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11. 发明申请

US20180076310A1 ASYMMETRICAL BLOCKING BIDIRECTIONAL GALLIUM NITRIDE SWITCH 审中-公开
公开(公告)号：US20180076310A1
公开(公告)日：2018-03-15
申请号：US15244819
申请日：2016-08-23
申请人： David Sheridan
发明人： David Sheridan
IPC分类号： H01L29/778 , H01L29/40 , H01L29/20 , H01L29/205 , H01L29/423 , H01L29/49
CPC分类号： H01L29/7787 , H01L29/1066 , H01L29/2003 , H01L29/205 , H01L29/402 , H01L29/404 , H01L29/42356 , H01L29/4236 , H01L29/4966 , H01L29/66462 , H01L29/7786
摘要： A high electron mobility transistor (HEMT)gallium nitride (GaN) bidirectional blocking device includes a hetero-j unction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2 DEG) layer. The HEMT GaN bidirectional blocking device further includes a first source/drain electrode and a second source/drain electrode disposed on two opposite sides of a gate electrode disposed on top of said hetero-junction structure for controlling a current flow between the first and second source/drain electrodes in the 2 DEG layer wherein the gate electrode is disposed at a first distance from the first source/drain electrode and a second distance from the second source/drain electrode and the first distance is different from the second distance.

12. 发明授权

US09021409B2 Integration of data mining and static analysis for hardware design verification 有权
标题翻译：数据挖掘和静态分析的集成用于硬件设计验证
公开(公告)号：US09021409B2
公开(公告)日：2015-04-28
申请号：US13433909
申请日：2012-03-29
申请人： Shobha Vasudevan , David Sheridan , Lingyi Liu
发明人： Shobha Vasudevan , David Sheridan , Lingyi Liu
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/5022
摘要： A method of generating assertions for verification of a hardware design expressed at a register transfer level (RTL) includes running simulation traces through the design to generate simulation data; extract domain-specific information about the design for variables of interest; execute a data mining algorithm with the simulation data and the domain-specific information, to generate a set of candidate assertions for variable(s) of interest through machine learning with respect to the domain-specific information, the candidate assertions being likely invariants; conduct formal verification on the design with respect to each candidate assertion by outputting as invariants the candidate assertions that pass verification; iteratively feed back into the algorithm a counterexample trace generated by each failed candidate assertion, each counterexample trace including at least one additional variable in the design not previously input into the data mining algorithm, to thus increase coverage of a state space of the design.
摘要翻译：生成用于验证在寄存器传送级（RTL）表示的硬件设计的断言的方法包括通过设计运行模拟迹线以产生仿真数据; 提取关于感兴趣的变量的设计的领域特定信息; 使用模拟数据和域特定信息执行数据挖掘算法，通过机器学习针对域特定信息生成一组感兴趣的变量的候选断言，候选断言可能是不变的; 通过输出通过验证的候选断言作为不变量，对每个候选断言进行设计的形式验证; 迭代地将由每个故障候选者断言产生的反例跟踪反馈给算法，每个反例行轨迹包括设计中至少有一个附加变量，以前没有输入到数据挖掘算法中，从而增加设计状态空间的覆盖。

13. 发明申请

US20060172543A1 Graded junction termination extensions for electronic devices 失效
公开(公告)号：US20060172543A1
公开(公告)日：2006-08-03
申请号：US11201066
申请日：2005-08-09
申请人： J. Merrett , Tamara Isaacs-Smith , David Sheridan , John Williams
发明人： J. Merrett , Tamara Isaacs-Smith , David Sheridan , John Williams
IPC分类号： H01L21/302
CPC分类号： H01L29/0615 , H01L21/0465 , H01L29/1608 , Y10S438/931
摘要： A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.

14. 发明申请

US20070215978A1 TUNEABLE SEMICONDUCTOR DEVICE 失效
标题翻译：可调谐半导体器件
公开(公告)号：US20070215978A1
公开(公告)日：2007-09-20
申请号：US11568156
申请日：2004-04-22
申请人： Andreas Stricker , David Sheridan , Jae-Sung Rieh , Greg Freeman , Steven Voldman , Stephen Onge
发明人： Andreas Stricker , David Sheridan , Jae-Sung Rieh , Greg Freeman , Steven Voldman , Stephen Onge
IPC分类号： H01L29/66
CPC分类号： H01L29/66363 , H01L29/0821 , H01L29/0834 , H01L29/66242 , H01L29/7378 , H01L29/74 , H01L29/861 , H01L29/872 , H01L29/93
摘要： Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between the discontinuous portions of the discontinuous sub-collector tunes the performance characteristics of the semiconductor structure. The performance characteristics that are tunable include breakdown voltage, unity current gain cutoff frequency, unity power gain cutoff frequency, transit frequency, current density, capacitance range, noise injection, minority carrier injection and trigger and holding voltage.
摘要翻译：公开了一种形成半导体结构的方法，该半导体结构包括具有与下面的衬底不同的极性的不连续的非平面子集电极。此外，该结构包括在副集电极上方的有源区（集电极），有源区上方的基极和基极上方的发射极。不连续子集电极的不连续部分之间的距离调节了半导体结构的性能特性。可调谐的性能特点包括击穿电压，单位电流增益截止频率，单位功率增益截止频率，传输频率，电流密度，电容范围，噪声注入，少数载流子注入以及触发和保持电压。

15. 发明申请

US20070151232A1 Devices and methods for reduction of NOx emissions from lean burn engines 有权
公开(公告)号：US20070151232A1
公开(公告)日：2007-07-05
申请号：US11715854
申请日：2007-03-08
申请人： Ralph Dalla Betta , Joel Cizeron , David Sheridan
发明人： Ralph Dalla Betta , Joel Cizeron , David Sheridan
IPC分类号： F01N3/00 , F01N3/10
CPC分类号： F01N3/0871 , F01N3/0814 , F01N3/0842 , F01N3/2053 , F01N3/2066 , F01N13/009 , F01N13/0093 , F01N2240/20 , F01N2240/30 , F01N2610/03 , F01N2610/04 , Y02A50/2325 , Y02T10/24
摘要： The invention provides devices and methods for generating H2 and CO in an O2 containing gas stream. The invention also provides devices and methods for removal of NOX from an O2 containing gas stream, particularly the oxygen-rich exhaust stream from a lean-burning engine, such as a diesel engine. The invention includes a fuel processor that efficiently converts added hydrocarbon fuel to a reducing mixture of H2 and CO. The added fuel may be a portion of the onboard fuel on a vehicle. The H2 and CO are incorporated into the exhaust stream and reacted over a selective lean NOX catalyst to convert NOX to N2. thereby providing an efficient means of NOX emission control.

16. 发明授权

US08884270B2 Vertical junction field effect transistors with improved thermal characteristics and methods of making 有权
标题翻译：具有改进的热特性和制造方法的垂直结型场效应晶体管
公开(公告)号：US08884270B2
公开(公告)日：2014-11-11
申请号：US13436159
申请日：2012-03-30
申请人： Janna Casady , Jeffrey Casady , Kiran Chatty , David Sheridan , Andrew Ritenour
发明人： Janna Casady , Jeffrey Casady , Kiran Chatty , David Sheridan , Andrew Ritenour
IPC分类号： H01L29/06 , H01L29/808 , H01L29/40 , H01L29/66
CPC分类号： H01L29/8083 , H01L29/1608 , H01L29/402 , H01L29/66909
摘要： Vertical junction field effect transistors (VJFETs) having improved heat dissipation at high current flow while maintaining the desirable specific on-resistance and normalized saturated drain current properties characteristic of devices having small pitch lengths are described. The VJFETs comprise one or more electrically active source regions in electrical contact with the source metal of the device and one or more electrically inactive source regions not in electrical contact with the source metal of the device. The electrically inactive source regions dissipate heat generated by the electrically active source regions during current flow.
摘要翻译：描述了在高电流下具有改进的散热的垂直结型场效应晶体管（VJFET），同时保持了具有小间距长度的器件所需的特定导通电阻和归一化饱和漏极电流特性。 VJFET包括与器件的源极金属电接触的一个或多个电活性源极区域和不与器件的源极金属电接触的一个或多个不活跃电源区域。电流不稳定的源区域在电流流动期间耗散由电活性源区域产生的热量。

17. 发明授权

US07709930B2 Tuneable semiconductor device with discontinuous portions in the sub-collector 失效
标题翻译：在子集电极中具有不连续部分的可调谐半导体器件
公开(公告)号：US07709930B2
公开(公告)日：2010-05-04
申请号：US11568156
申请日：2004-04-22
申请人： Andreas Stricker , David Sheridan , Jae-Sung Rieh , Gregory Freeman , Steven Voldman , Stephen A. St. Onge
发明人： Andreas Stricker , David Sheridan , Jae-Sung Rieh , Gregory Freeman , Steven Voldman , Stephen A. St. Onge
IPC分类号： H01L29/66
CPC分类号： H01L29/66363 , H01L29/0821 , H01L29/0834 , H01L29/66242 , H01L29/7378 , H01L29/74 , H01L29/861 , H01L29/872 , H01L29/93
摘要： Disclosed is a method of forming a semiconductor structure that includes a discontinuous non-planar sub-collector having a different polarity than the underlying substrate. In addition, this structure includes an active area (collector) above the sub-collector, a base above the active area, and an emitter above the base. The distance between the discontinuous portions of the discontinuous sub-collector tunes the performance characteristics of the semiconductor structure. The performance characteristics that are tunable include breakdown voltage, unity current gain cutoff frequency, unity power gain cutoff frequency, transit frequency, current density, capacitance range, noise injection, minority carrier injection and trigger and holding voltage.
摘要翻译：公开了一种形成半导体结构的方法，该半导体结构包括具有与下面的衬底不同的极性的不连续的非平面子集电极。此外，该结构包括在副集电极上方的有源区（集电极），有源区上方的基极和基极上方的发射极。不连续子集电极的不连续部分之间的距离调节了半导体结构的性能特性。可调谐的性能特点包括击穿电压，单位电流增益截止频率，单位功率增益截止频率，传输频率，电流密度，电容范围，噪声注入，少数载流子注入以及触发和保持电压。

18. 发明申请

US20060234484A1 METHOD AND STRUCTURE FOR ION IMPLANTATION BY ION SCATTERING 审中-公开
标题翻译：离子散射的离子注入方法和结构
公开(公告)号：US20060234484A1
公开(公告)日：2006-10-19
申请号：US10907752
申请日：2005-04-14
申请人： Louis Lanzerotti , David Sheridan , Steven Voldman
发明人： Louis Lanzerotti , David Sheridan , Steven Voldman
IPC分类号： H01L21/22 , H01L21/38
CPC分类号： H01L21/266 , H01L27/0259 , H01L29/66242 , H01L29/7378
摘要： A scatter-implant process and device is provided where a bi-level doping pattern is achieved in a single doping step. Additionally, devices having different breakdown voltages can be produced in a single implant process. The scatter-implant is fabricated by scattering implant ions off the edge of a mask, thereby reducing the ion energy causing the ions to doping shallower regions than the non-scattered ions which dope a lower region. By adjusting various parameters of the doping process such as, for example, ion type, ion energy, mask type and geometry, in a position of scattering edge relative to other structure of the device, the scatter-implant can be tuned to achieve certain properties of the semiconductor device. Additionally, circuits can be made using the scatter-implant process where pre-selected portion of the circuit incorporate the scatter-implant region and other portions of the circuit do not rely on the scatter region.
摘要翻译：提供散射注入工艺和器件，其中在单个掺杂步骤中实现双电平掺杂图案。另外，具有不同击穿电压的器件可以在单个注入工艺中产生。散射注入是通过将注入离子从掩模的边缘散射而制造的，从而减少了离子掺杂比掺杂较低区域的非散射离子更浅的区域的离子能。通过调整掺杂过程的各种参数，例如离子类型，离子能量，掩模类型和几何形状，在相对于器件的其他结构的散射边缘的位置，可以调整散射植入物以实现某些特性的半导体器件。另外，可以使用散射注入工艺制造电路，其中电路的预选部分包含散射注入区域，并且电路的其它部分不依赖于散射区域。

19. 发明申请

US20130019216A1 INTEGRATION OF DATA MINING AND STATIC ANALYSIS FOR HARDWARE DESIGN VERIFICATION 有权
标题翻译：数据采集与硬件设计验证的静态分析综合
公开(公告)号：US20130019216A1
公开(公告)日：2013-01-17
申请号：US13433909
申请日：2012-03-29
申请人： Shobha Vasudevan , David Sheridan , Lingyi Liu , Hyung Sul Kim
发明人： Shobha Vasudevan , David Sheridan , Lingyi Liu , Hyung Sul Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/504 , G06F17/5022
摘要： A method of generating assertions for verification of a hardware design expressed at a register transfer level (RTL) includes running simulation traces through the design to generate simulation data; extract domain-specific information about the design for variables of interest; execute a data mining algorithm with the simulation data and the domain-specific information, to generate a set of candidate assertions for variable(s) of interest through machine learning with respect to the domain-specific information, the candidate assertions being likely invariants; conduct formal verification on the design with respect to each candidate assertion by outputting as invariants the candidate assertions that pass verification; iteratively feed back into the algorithm a counterexample trace generated by each failed candidate assertion, each counterexample trace including at least one additional variable in the design not previously input into the data mining algorithm, to thus increase coverage of a state space of the design.
摘要翻译：生成用于验证在寄存器传送级（RTL）表示的硬件设计的断言的方法包括通过设计运行模拟迹线以产生仿真数据; 提取关于感兴趣的变量的设计的领域特定信息; 使用模拟数据和域特定信息执行数据挖掘算法，通过机器学习针对域特定信息生成一组感兴趣的变量的候选断言，候选断言可能是不变的; 通过输出通过验证的候选断言作为不变量，对每个候选断言进行设计的形式验证; 迭代地将由每个故障候选者断言产生的反例跟踪反馈给算法，每个反例行轨迹包括设计中至少有一个附加变量，以前没有输入到数据挖掘算法中，从而增加设计状态空间的覆盖。

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