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11. 发明授权

US6153518A Method of making chip size package substrate 有权
标题翻译：制造芯片尺寸封装基板的方法
公开(公告)号：US6153518A
公开(公告)日：2000-11-28
申请号：US301533
申请日：1999-04-28
申请人： Donald C. Abbott , David W. West
发明人： Donald C. Abbott , David W. West
IPC分类号： H01L23/12 , H01L21/48 , H05K3/06 , H05K3/40 , H01L21/44
CPC分类号： H05K3/4038 , H01L21/4853 , H01L21/486 , H05K2201/09563 , H05K2203/1189 , H05K3/06
摘要： A method of fabricating an electrically conductive via in a substrate which includes providing an electrically insulating substrate having first and second opposing surfaces and forming a first layer of electrically conductive material on the first of the opposing surfaces and forming a second layer of electrically conductive material on the second of the opposing surface. In accordance with one embodiment, the second layer has a thickness greater than the electrically insulating layer and no greater than the sum of the thicknesses of the electrically insulating layer and the first layer. In accordance with a second embodiment, the second layer has a thickness greater than the electrically insulating layer and no greater than the sum of the thicknesses of the electrically insulating layer and the first layer. A hole is formed in the first layer having sidewalls. A stud is formed in the second layer aligned with the hole in the first layer. The stud is forced through the substrate and into contact with the sidewalls of the hole. The stud preferably has a cross section to provide a friction fit with the sidewalls of the hole. In accordance with the second embodiment, the stud will extend beyond the bottom side of the polyimide layer to provide the effect of a ball from a ball grid array. The substrate can be heated to a thermoplastic state prior to forcing the stud through the substrate, if necessary. The substrate is preferably a polyimide and the electrically conductive material is preferably taken from the class consisting of copper and copper-based materials.
摘要翻译：一种在衬底中制造导电通孔的方法，其包括提供具有第一和第二相对表面的电绝缘衬底，并且在第一相对表面上形成第一导电材料层，并在第二层导电材料上形成第二层导电材料对面的第二个表面。根据一个实施例，第二层具有大于电绝缘层的厚度，不大于电绝缘层和第一层的厚度之和。根据第二实施例，第二层的厚度大于电绝缘层，不大于电绝缘层和第一层的厚度之和。在具有侧壁的第一层中形成有孔。在与第一层中的孔对准的第二层中形成螺柱。螺柱被迫穿过基板并与孔的侧壁接触。螺柱优选地具有横截面以提供与孔的侧壁的摩擦配合。根据第二实施例，螺柱将延伸超出聚酰亚胺层的底侧，以提供来自球栅阵列的球的作用。如果需要，可以在将螺柱穿过基底之前将基底加热至热塑性状态。基板优选为聚酰亚胺，导电材料优选为由铜和铜基材料构成的类型。

12. 发明授权

US5989935A Column grid array for semiconductor packaging and method 失效
标题翻译：用于半导体封装的列栅阵列和方法
公开(公告)号：US5989935A
公开(公告)日：1999-11-23
申请号：US961783
申请日：1997-10-31
申请人： Donald C. Abbott
发明人： Donald C. Abbott
IPC分类号： H01L23/12 , H01L21/48 , H01L23/31 , H01L23/498 , H01L23/50 , H05K3/34 , H05K3/40 , H05K3/42 , H01L21/44 , H01L21/50
CPC分类号： H01L23/49816 , H01L21/4853 , H01L21/486 , H01L23/3128 , H05K3/4007 , H01L2224/48091 , H01L2224/48227 , H01L24/48 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H05K2201/0347 , H05K2201/0355 , H05K2201/0367 , H05K2201/09481 , H05K2201/09563 , H05K2203/0554 , H05K2203/1394 , H05K3/3436 , H05K3/423
摘要： A method for manufacturing a column grid array semiconductor package (10, 210) may include the steps of providing a substrate material (14, 114, 214) having a first side (16, 116) and a second side (18), forming a plurality of holes (36, 136, 236) in the substrate (14, 114, 214), forming contacts (24, 124,) on the first surface (16, 116) of the substrate (14, 114, 214), filling the plurality of holes (36, 136, 236) with a conductive material (32, 132, 232) to an extent that an extension portion (28, 128, 228) is formed on the second side (18) of the substrate (14, 114, 214) to which an electrical contact may be made. The extension portion (28, 128, 228) may be coated with a capping material (40, 140, 240). The holes (36, 136, 236) may be filled with the conductive material (32, 132, 232) by placing a material (146, 246) over the hole (36, 136, 236) on the first side (16, 116) of the substrate (14, 114, 214) and filling the holes (36, 136, 236) with the conductive material (32, 132, 232). The resist (146, 246) may then be removed.
摘要翻译：一种用于制造列栅阵列半导体封装（10,210）的方法可以包括以下步骤：提供具有第一侧面（16,116）和第二侧面（18）的衬底材料（14,114,214），形成在衬底（14,114,214）中的多个孔（36,136,236），在衬底（14,114,214）的第一表面（16,116）上形成接触（24,124），填充所述多个孔（36,136,236）具有导电材料（32,132,232），其延伸部分（28,128,228）形成在所述基底（14）的第二侧（18）上，114,214），可以进行电接触。延伸部分（28,128,228）可以涂覆有覆盖材料（40,140,240）。通过将第一侧（16,116）上的孔（36,136,236）上的材料（146,246）放置在孔（36,136,236）上，可以用导电材料（32,132,232）填充孔），并且用导电材料（32,132,232）填充孔（36,136,236）。然后可以去除抗蚀剂（146,246）。

13. 发明授权

US5935719A Lead-free, nickel-free and cyanide-free plating finish for semiconductor leadframes 有权
标题翻译：半导体引线框架的无铅，无镍和无氰镀层
公开(公告)号：US5935719A
公开(公告)日：1999-08-10
申请号：US141856
申请日：1998-08-28
申请人： Donald C. Abbott
发明人： Donald C. Abbott
IPC分类号： B32B15/01
CPC分类号： B32B15/018 , Y10T428/12868
摘要： A leadframe and method of fabrication of the leadframe. A leadframe is formed from one of copper or copper-based material and a coating of palladium is formed over the leadframe. Optionally, a layer of from about 10 to about 95 percent copper by weight and the remainder palladium is deposited between the leadframe and the coating of palladium. The coating of palladium is from about 3 to about 10 microinches and preferably about 3 microinches. The palladium/copper layer is from about 5 to about 40 microinches and preferably about 10 microinches. A semiconductor device is fabricated by providing a copper or copper-based lead frame and forming a layer of palladium over the leadframe. Optionally, a layer of palladium and copper is formed between the leadframe and the layer of palladium.
摘要翻译：引线框架和引线框架的制造方法。引线框架由铜或铜基材料之一形成，并且在引线框架上形成钯涂层。任选地，在引线框架和钯涂层之间沉积约10至约95重量％的铜和剩余的钯的层。钯的涂层为约3至约10微英寸，优选约3微英寸。钯/铜层为约5至约40微英寸，优选约10微英寸。通过提供铜或铜基引线框架并在引线框架上形成钯层来制造半导体器件。任选地，在引线框架和钯层之间形成一层钯和铜。

14. 发明授权

US08587099B1 Leadframe having selective planishing 有权
标题翻译：引线框架具有选择性平整
公开(公告)号：US08587099B1
公开(公告)日：2013-11-19
申请号：US13462574
申请日：2012-05-02
申请人： Donald C. Abbott
发明人： Donald C. Abbott
IPC分类号： H01L23/495
CPC分类号： H01L21/4842 , H01L21/4821 , H01L21/561 , H01L21/64 , H01L23/49503 , H01L23/49541 , H01L23/49548 , H01L23/49565 , H01L23/49575 , H01L24/85 , H01L24/97 , H01L2224/05599 , H01L2224/85 , H01L2924/00014 , H01L2924/0002 , H01L2924/181 , H01L2924/2064 , Y10T29/49121 , H01L2924/00 , H01L2224/45099
摘要： A metal leadframe strip (500) for semiconductor devices is described. The leadframe strip has a plurality of sites (510) for assembling semiconductor chips. The sites alternate with zones (520) for connecting the leadframe to molding compound runners. The sites (510) have mechanically rough and optically matte surfaces (511, 512). The zones (520) have at least portions with mechanically flattened and optically shiny metal surfaces (521, 522). The flattened surface portions transition into the rough surface portions by a step.
摘要翻译：描述了用于半导体器件的金属引线框带（500）。引线框带具有用于组装半导体芯片的多个部位（510）。这些场地与用于将引线框架连接到模制复合浇道的区域（520）交替。位置（510）具有机械粗糙和光学磨砂表面（511,512）。区域（520）具有至少具有机械平坦化和光学发光的金属表面（521,522）的部分。平坦的表面部分通过台阶转变成粗糙表面部分。

15. 发明申请

US20130292811A1 LEADFRAME HAVING SELECTIVE PLANISHING 有权
标题翻译：具有选择性布置的LEADFRAME
公开(公告)号：US20130292811A1
公开(公告)日：2013-11-07
申请号：US13462574
申请日：2012-05-02
申请人： Donald C. Abbott
发明人： Donald C. Abbott
IPC分类号： H01L23/495 , H01L21/64 , H05K7/18
CPC分类号： H01L21/4842 , H01L21/4821 , H01L21/561 , H01L21/64 , H01L23/49503 , H01L23/49541 , H01L23/49548 , H01L23/49565 , H01L23/49575 , H01L24/85 , H01L24/97 , H01L2224/05599 , H01L2224/85 , H01L2924/00014 , H01L2924/0002 , H01L2924/181 , H01L2924/2064 , Y10T29/49121 , H01L2924/00 , H01L2224/45099
摘要： A metal leadframe strip (500) for semiconductor devices is described. The leadframe strip has a plurality of sites (510) for assembling semiconductor chips. The sites alternate with zones (520) for connecting the leadframe to molding compound runners. The sites (510) have mechanically rough and optically matte surfaces (511, 512). The zones (520) have at least portions with mechanically flattened and optically shiny metal surfaces (521, 522). The flattened surface portions transition into the rough surface portions by a step.
摘要翻译：描述了用于半导体器件的金属引线框带（500）。引线框带具有用于组装半导体芯片的多个部位（510）。这些场地与用于将引线框架连接到模制复合浇道的区域（520）交替。位置（510）具有机械粗糙和光学磨砂表面（511,512）。区域（520）具有至少具有机械平坦化和光学发光的金属表面（521,522）的部分。平坦的表面部分通过台阶转变成粗糙表面部分。

16. 发明授权

US08227295B2 IC die having TSV and wafer level underfill and stacked IC devices comprising a workpiece solder connected to the TSV 有权
标题翻译：具有TSV和晶片级底部填充的IC芯片和包括连接到TSV的工件焊料的堆叠IC器件
公开(公告)号：US08227295B2
公开(公告)日：2012-07-24
申请号：US12416694
申请日：2009-04-01
申请人： Margaret R. Simmons-Matthews , Donald C. Abbott
发明人： Margaret R. Simmons-Matthews , Donald C. Abbott
IPC分类号： H01L21/00
CPC分类号： H01L23/5384 , H01L21/76898 , H01L23/481 , H01L24/11 , H01L24/12 , H01L24/16 , H01L25/0657 , H01L25/50 , H01L2224/0401 , H01L2224/0557 , H01L2224/05571 , H01L2224/114 , H01L2224/1147 , H01L2224/1148 , H01L2224/116 , H01L2224/13021 , H01L2224/13025 , H01L2224/13099 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/1461 , H01L2924/30107 , H01L2924/00012 , H01L2924/00 , H01L2224/05552
摘要： A method of forming integrated circuit (IC) die configured for attachment to another die or a package substrate, and stacked IC devices therefrom. At least one IC die having a top semiconductor surface and a bottom surface and at least one through substrate via (TSV) including a tip protruding beyond the bottom surface to a tip length is provided. The tip has an outer dielectric tip liner, and an electrically conductive portion within the outer dielectric tip liner. A compliant layer is applied to the bottom surface of the IC die. The dielectric tip liner is removed from a distal portion of the tip to expose an electrically conductive tip portion. A solder material is deposited on the exposed distal portion of the tip. The solder material is reflowed and coalesced to form a solder bump on the distal portion of the tip.
摘要翻译：一种形成集成电路（IC）管芯的方法，其被配置为附接到另一个管芯或封装衬底，并且由此堆叠IC器件。提供具有顶部半导体表面和底部表面的至少一个IC管芯以及至少一个穿过衬底通孔（TSV）的至少一个IC管芯，该贯通衬底通孔（TSV）包括突出超过底部表面至尖端长度的尖端。尖端具有外部电介质末端衬里和在外部电介质末端衬里内的导电部分。将柔性层施加到IC芯片的底表面。电介质尖端衬垫从尖端的远端部分移除以暴露导电尖端部分。焊料材料沉积在尖端的暴露的远端部分上。焊料材料被回流并聚结以在尖端的远端部分上形成焊料凸块。

17. 发明授权

US07851928B2 Semiconductor device having substrate with differentially plated copper and selective solder 有权
标题翻译：具有带有差分镀铜和选择性焊料的衬底的半导体器件
公开(公告)号：US07851928B2
公开(公告)日：2010-12-14
申请号：US12136231
申请日：2008-06-10
申请人： Bernardo Gallegos , Donald C. Abbott
发明人： Bernardo Gallegos , Donald C. Abbott
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/49811 , H01L23/3128 , H01L23/49827 , H01L24/11 , H01L24/12 , H01L24/16 , H01L24/81 , H01L2224/05571 , H01L2224/05573 , H01L2224/1134 , H01L2224/13099 , H01L2224/13144 , H01L2224/13147 , H01L2224/16225 , H01L2224/16238 , H01L2224/73204 , H01L2224/81193 , H01L2224/81801 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/3025 , H05K3/108 , H05K3/3452 , H05K3/3473 , H05K3/386 , H05K3/423 , H05K2201/0355 , H05K2201/0394 , H05K2201/09481 , H05K2201/10674 , H05K2203/063 , H05K2203/0733 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： A semiconductor device having an insulating substrate with differentially plated metal and selective solder. Chip 221 with contact studs 223 is attached onto the traces 203 on tape 101. The traces, which are unprotected by soldermask 110, have solder on the top surface, but not on the sidewalls. The sidewalls of the traces are at right angles to the trace top, giving the trace a rectangular cross section. Consequently, the area for attaching stud 223 is maximized. At the same time, the differential plating method of trace metal 203 and through-hole metal 206 allows different metal thicknesses and provides independent control of the trace aspect ratio for low electrical resistance and trace fatigue.
摘要翻译：具有绝缘基板的半导体器件，具有差分镀金属和选择性焊料。具有接触柱223的芯片221附着在磁带101上的迹线203上。未被焊接掩模110保护的迹线在顶表面上具有焊料，但不在侧壁上。迹线的侧壁与轨迹顶部成直角，给出轨迹为矩形截面。因此，用于安装螺柱223的区域最大化。同时，痕量金属203和通孔金属206的差分电镀方法允许不同的金属厚度，并且对于低电阻和痕量疲劳提供独立的痕量纵横比的控制。

18. 发明授权

US07507605B2 Low cost lead-free preplated leadframe having improved adhesion and solderability 有权
标题翻译：低成本的无铅预镀引线框具有改进的附着力和可焊性
公开(公告)号：US07507605B2
公开(公告)日：2009-03-24
申请号：US11026841
申请日：2004-12-30
申请人： Donald C. Abbott
发明人： Donald C. Abbott
IPC分类号： H01L21/00
CPC分类号： H01L23/49582 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48664 , H01L2224/73265 , H01L2224/85464 , H01L2224/97 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/01322 , H01L2924/014 , H01L2924/10329 , H01L2924/14 , H01L2924/181 , Y10T428/1259 , H01L2924/00014 , H01L2224/83 , H01L2224/85 , H01L2924/00012 , H01L2924/00
摘要： A leadframe with a structure made of a base metal (105), wherein the structure has a plurality of surfaces. On each of these surfaces are metal layers in a stack adherent to the base metal. The stack comprises a nickel layer (201) in contact with the base metal, a palladium layer (202) in contact with the nickel layer, and an outermost tin layer (203) in contact with the palladium layer. In terms of preferred layer thicknesses, the nickel layer is between about 0.5 and 2.0 μm thick, the palladium layer between about 5 and 150 nm thick, and the tin layer less than about 5 nm thick, preferably about 3 nm. At this thinness, the tin has no capability of forming whiskers, but offers superb adhesion to polymeric encapsulation materials, improved characteristics for reliable stitch bonding as well as affinity to reflow metals (solders).
摘要翻译：一种具有由贱金属（105）制成的结构的引线框，其中所述结构具有多个表面。在这些表面中的每个表面上是与基底金属粘附的叠层中的金属层。叠层包括与基底金属接触的镍层（201），与镍层接触的钯层（202）和与钯层接触的最外层锡层（203）。在优选的层厚度方面，镍层的厚度在0.5至2.0μm之间，钯层的厚度在5至150nm之间，锡层小于约5nm厚，优选约3nm。在这种薄度下，锡不具有形成晶须的能力，而且对聚合物封装材料具有极好的粘附性，可靠的针脚粘合以及对回流金属（焊料）的亲和力的改进特性。

19. 发明授权

US07179738B2 Semiconductor assembly having substrate with electroplated contact pads 有权
标题翻译：半导体组件，其具有带有电镀接触焊盘的衬底
公开(公告)号：US07179738B2
公开(公告)日：2007-02-20
申请号：US10985757
申请日：2004-11-09
申请人： Donald C. Abbott
发明人： Donald C. Abbott
IPC分类号： H01L21/445
CPC分类号： H05K3/244 , H01L23/498 , H01L23/49816 , H01L23/49827 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/16 , H01L24/81 , H01L2224/0345 , H01L2224/03462 , H01L2224/03464 , H01L2224/0347 , H01L2224/039 , H01L2224/0401 , H01L2224/05083 , H01L2224/05147 , H01L2224/05155 , H01L2224/05573 , H01L2224/05644 , H01L2224/05664 , H01L2224/08501 , H01L2224/13109 , H01L2224/13111 , H01L2224/13144 , H01L2224/81192 , H01L2224/81444 , H01L2224/81464 , H01L2224/81815 , H01L2924/01005 , H01L2924/01006 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/14 , H05K1/113 , H05K3/3463 , Y10S438/928 , H01L2924/00
摘要： An apparatus comprising an insulating substrate (101) having first and second surfaces (101a, 101b) and a plurality of metal-filled vias (102) extending from the first to the second surface. The first and second surfaces have contact pads (103, 104), each one comprising a connector stack to at least one of the vias. The stack comprises a seed metal layer (110, copper) in contact with the via metal capable of providing an adhesive and conductive layer for electroplating on its surface, a first electroplated support layer (111a, copper) secured to the seed metal layer, a second electroplated support layer (111b, nickel), and at least one reflow metal bonding layer (112, palladium, gold) on the second support layer. The electrolytic plating process produces support layers substantially pure (at least 99.0%), free of unwanted additives such as phosphorus or boron, and exhibiting closely controlled grain sizes. Reflow metal connectors (220, 230) provide attachment to chip contact pads and external parts.
摘要翻译：一种包括具有第一和第二表面（101a，101b）的绝缘基板（101）和从第一表面延伸到第二表面的多个金属填充的通孔（102）的装置。第一和第二表面具有接触焊盘（103,104），每个接触焊盘包括至少一个通孔的连接器叠层。堆叠包括与通孔金属接触的种子金属层（110，铜），其能够提供用于在其表面上电镀的粘合剂和导电层，固定到种子金属层的第一电镀支撑层（111a，铜）第二电镀支撑层（111b，镍）和在第二支撑层上的至少一个回流金属结合层（112，钯，金）。电解电镀工艺产生基本上纯的（至少99.0％）的支撑层，没有不需要的添加剂如磷或硼，并且表现出紧密控制的晶粒尺寸。回流金属连接器（220,230）提供与芯片接触焊盘和外部部件的连接。

20. 发明授权

US07064008B2 Semiconductor leadframes plated with thick nickel, minimum palladium, and pure tin 有权
标题翻译：半导体引线框镀镍，最小钯和纯锡
公开(公告)号：US07064008B2
公开(公告)日：2006-06-20
申请号：US10762122
申请日：2004-01-20
申请人： Donald C. Abbott , Douglas W. Romm
发明人： Donald C. Abbott , Douglas W. Romm
IPC分类号： H01L21/50
CPC分类号： H05K3/3426 , H01L23/49582 , H01L24/45 , H01L24/48 , H01L24/73 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48599 , H01L2224/48639 , H01L2224/48664 , H01L2224/48699 , H01L2224/48739 , H01L2224/48764 , H01L2224/48839 , H01L2224/48864 , H01L2224/73265 , H01L2224/85439 , H01L2224/85464 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/14 , H01L2924/15747 , H01L2924/181 , Y02P70/613 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
摘要： A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering the base metal; a plated layer of pure tin on the nickel layer, selectively covering areas of the leadframe intended for attachment to other parts; and a plated layer of palladium on said nickel layer, selectively covering areas of said Leadframe intended for bonding wire attachment.
摘要翻译：一种用于集成电路芯片的引线框架，其包括具有完全覆盖所述母材的镍镀层的母材; 在镍层上镀有纯锡的镀层，选择性地覆盖用于附接到其它部件的引线框架的区域; 以及在所述镍层上的镀钯层，选择性地覆盖用于粘合电线附件的所述引线框架的区域。

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