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11. 发明授权

US08552764B2 Clock glitch detection circuit 有权
公开(公告)号：US08552764B2
公开(公告)日：2013-10-08
申请号：US13131349
申请日：2009-01-05
申请人： Michael Rohleder , Thomas Koch , Vladimir Litovtchenko , Thomas Luedeke
发明人： Michael Rohleder , Thomas Koch , Vladimir Litovtchenko , Thomas Luedeke
IPC分类号： H03K5/19 , H03K9/06
CPC分类号： G06F1/04 , H03K5/1252
摘要： In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.

12. 发明申请

US20110083041A1 MEMORY SYSTEM WITH REDUNDANT DATA STORAGE AND ERROR CORRECTION 有权
标题翻译：具有冗余数据存储和错误校正的存储器系统
公开(公告)号：US20110083041A1
公开(公告)日：2011-04-07
申请号：US12995297
申请日：2008-06-20
申请人： Michael Rohleder , Gary Hay , Stephan Mueller , Manfred Thanner
发明人： Michael Rohleder , Gary Hay , Stephan Mueller , Manfred Thanner
IPC分类号： G06F11/14
CPC分类号： G06F11/167 , G11C29/74 , G11C2029/0411
摘要： A system comprises at least two random access memory (RAM) elements arranged to store data redundantly. The system further comprises RAM routing logic comprising comparison logic operably coupled to the at least two RAM elements and arranged to compare redundant data read from the at least two RAM elements, and check and validation logic, independent of the RAM routing logic, operably coupled to the at least two RAM elements and arranged to additionally detect an error in the redundant data read from the at least two RAM elements and provide an error indication signal to the RAM routing logic in response thereto. The RAM routing logic further comprises selection logic arranged to dynamically select redundant data from one of the at least two RAM elements based on the comparison of the redundant data and the error indication signal.
摘要翻译：系统包括被布置为冗余地存储数据的至少两个随机存取存储器（RAM）元件。所述系统还包括RAM路由逻辑，其包括可操作地耦合到所述至少两个RAM元件的比较逻辑，并且被布置为比较从所述至少两个RAM元素读取的冗余数据，以及独立于所述RAM路由逻辑的检查和验证逻辑，其可操作地耦合到所述至少两个RAM元件并且被布置为附加地检测从所述至少两个RAM元素读取的冗余数据中的错误，并且响应于此向RAM路由逻辑提供错误指示信号。 RAM路由逻辑还包括选择逻辑，其被布置为基于冗余数据和错误指示信号的比较来动态地从至少两个RAM元素中的一个RAM元素中选择冗余数据。

13. 发明申请

US20060059278A1 Information communication controller interface apparatus and method 有权
标题翻译：信息通信控制器接口设备及方法
公开(公告)号：US20060059278A1
公开(公告)日：2006-03-16
申请号：US10507157
申请日：2002-11-11
申请人： John Doyle , John Logan , Michael Rohleder , Stephen Pickering
发明人： John Doyle , John Logan , Michael Rohleder , Stephen Pickering
IPC分类号： G06F3/00
CPC分类号： H04L29/06 , H04L45/742 , H04L69/18
摘要： An apparatus and method for communicating information within a network having one or more communication buses (5, 6, 7, 8), consisting of one or more elements (20, 30, 40) to maximise throughput and minimise CPU involvement by executing the following. Compare incoming message identifiers (14) against a set of predetermined identifiers (22). Transpose data sets (12) within the incoming message data frame and where necessary, save and/or transmit new frames as defined by operations dependent upon the incoming identifier. By utilising an optimal set of operands the memory requirement is satisfied by a minimal size of standard type.
摘要翻译：一种用于在具有由一个或多个元件（20,30,40）组成的一个或多个通信总线（5,6,7,8）的网络内传送信息的装置和方法，以通过执行以下操作来最大化吞吐量并最小化CPU占用。将输入消息标识符（14）与一组预定标识符（22）进行比较。在进入的消息数据帧内转移数据集（12），并且在必要时保存和/或发送由依赖于传入标识符的操作定义的新帧。通过利用最佳操作数集合，通过标准类型的最小尺寸来满足存储器需求。

14. 发明申请

US20140006841A1 CLOCK GLITCH DETECTION CIRCUIT 有权
标题翻译：时钟检测电路
公开(公告)号：US20140006841A1
公开(公告)日：2014-01-02
申请号：US14015519
申请日：2013-08-30
申请人： Michael Rohleder , Thomas Koch , Vladimir Litovtchenko , Thomas Luedeke
发明人： Michael Rohleder , Thomas Koch , Vladimir Litovtchenko , Thomas Luedeke
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , H03K5/1252
摘要： In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.
摘要翻译：在用于检测时钟信号中的时钟毛刺的第一电路中，主计数器由时钟信号计时，并存储主计数。增量器将主计数递增一个增量。从计数器由时钟信号计时，并存储从计数。从计数相对于主计数延迟至少一定数量的时钟沿。比较器确定主计数和从计数之间的差是否至少是递增器的值乘以特定数量的时钟边沿。

15. 发明授权

US08589737B2 Memory system with redundant data storage and error correction 有权
标题翻译：具有冗余数据存储和纠错的存储系统
公开(公告)号：US08589737B2
公开(公告)日：2013-11-19
申请号：US12995297
申请日：2008-06-20
申请人： Michael Rohleder , Gary Hay , Stephan Mueller , Manfred Thanner
发明人： Michael Rohleder , Gary Hay , Stephan Mueller , Manfred Thanner
IPC分类号： G06F11/00
CPC分类号： G06F11/167 , G11C29/74 , G11C2029/0411
摘要： A system comprises at least two random access memory (RAM) elements arranged to store data redundantly. The system further comprises RAM routing logic comprising comparison logic operably coupled to the at least two RAM elements and arranged to compare redundant data read from the at least two RAM elements, and check and validation logic, independent of the RAM routing logic, operably coupled to the at least two RAM elements and arranged to additionally detect an error in the redundant data read from the at least two RAM elements and provide an error indication signal to the RAM routing logic in response thereto. The RAM routing logic further comprises selection logic arranged to dynamically select redundant data from one of the at least two RAM elements based on the comparison of the redundant data and the error indication signal.
摘要翻译：系统包括被布置为冗余地存储数据的至少两个随机存取存储器（RAM）元件。所述系统还包括RAM路由逻辑，其包括可操作地耦合到所述至少两个RAM元件的比较逻辑，并且被布置为比较从所述至少两个RAM元素读取的冗余数据，以及独立于所述RAM路由逻辑的检查和验证逻辑，其可操作地耦合到所述至少两个RAM元件并且被布置为附加地检测从所述至少两个RAM元素读取的冗余数据中的错误，并且响应于此向RAM路由逻辑提供错误指示信号。 RAM路由逻辑还包括选择逻辑，其被布置为基于冗余数据和错误指示信号的比较来动态地从至少两个RAM元素中的一个RAM元素中选择冗余数据。

16. 发明申请

US20120304024A1 DATA PROCESSING METHOD, DATA PROCESSOR AND APPARATUS INCLUDING A DATA PROCESSOR 有权
标题翻译：数据处理方法，数据处理器和包括数据处理器的设备
公开(公告)号：US20120304024A1
公开(公告)日：2012-11-29
申请号：US13577072
申请日：2010-02-16
申请人： Michael Rohleder , Joachim Fader , Frank Lenke , Markus Baumeister
发明人： Michael Rohleder , Joachim Fader , Frank Lenke , Markus Baumeister
IPC分类号： G06F11/07
CPC分类号： G06F9/28 , G06F9/38 , G06F11/1645 , G06F11/1695 , G06F2201/845
摘要： A method of processing data in a data processor comprising at least two data processing units. The method comprises performing different data processing steps in the data processing units concurrently during a parallel operation, and replicating performances of selected identical data processing steps in the data processing units during a non-synchronised redundant operation. The non-synchronised redundant operation comprises an initial performance of the selected identical data processing steps in one of the data processing units and a replicate performance of the data processing steps starting later than the initial performance, preferably in another of the data processing units. Initial result data representative of results from the initial performance are registered, and compared with replicate result data representative of results from the replicate performance, and an error signal is produced in case of discrepancy.
摘要翻译：一种在包括至少两个数据处理单元的数据处理器中处理数据的方法。该方法包括在并行操作期间同时在数据处理单元中执行不同的数据处理步骤，以及在非同步冗余操作期间在数据处理单元中复制所选择的相同数据处理步骤的性能。非同步冗余操作包括在数据处理单元之一中所选择的相同数据处理步骤的初始性能以及优先于另一个数据处理单元中的初始性能开始的数据处理步骤的复制性能。记录表示来自初始性能的结果的初始结果数据，并与代表复制性能的结果的复制结果数据进行比较，并且在差异的情况下产生错误信号。

17. 发明授权

US07954431B2 Method for determining operating parameters of a printing press 有权
标题翻译：确定印刷机工作参数的方法
公开(公告)号：US07954431B2
公开(公告)日：2011-06-07
申请号：US11811432
申请日：2007-06-08
申请人： Jochen Jung , Rolf Müller , Michael Rohleder , Matthias Niedernhuber
发明人： Jochen Jung , Rolf Müller , Michael Rohleder , Matthias Niedernhuber
IPC分类号： B41F33/00
CPC分类号： B41F23/00 , B41F23/0426 , B41F23/044 , F26B21/06 , F26B25/004 , F26B25/22
摘要： A printing press, in particular a sheet-fed offset printing press, includes at least one control device, a plurality of printing units, one or more varnishing units, and one or more dryers. Variables determining a dryness of the printing material are determined and used to optimize the drying process. For that purpose, the important material streams influencing the drying process are determined at least for the region of the printing press that contains the drying device(s).
摘要翻译：印刷机，特别是单张胶版印刷机包括至少一个控制装置，多个印刷单元，一个或多个上光单元和一个或多个干燥器。测定确定印刷材料干燥度的变量并用于优化干燥过程。为此，至少对于包含干燥装置的印刷机的区域来确定影响干燥过程的重要材料流。

18. 发明申请

US20100287443A1 PROCESSOR BASED SYSTEM HAVING ECC BASED CHECK AND ACCESS VALIDATION INFORMATION MEANS 有权
标题翻译：基于ECC的基于处理器的系统检查和访问验证信息手段
公开(公告)号：US20100287443A1
公开(公告)日：2010-11-11
申请号：US12811454
申请日：2008-01-16
申请人： Michael Rohleder , Gary Hay , Stephan Mueller , Manfred Thanner
发明人： Michael Rohleder , Gary Hay , Stephan Mueller , Manfred Thanner
IPC分类号： H03M13/09 , G06F13/40
CPC分类号： G06F11/1645 , G06F11/10 , G06F11/1654 , G06F2201/845
摘要： A system comprises a first master element; and at least one shared communication element arranged to operably couple the first master element to at least one slave element. The system further comprises at least one validation element located on at least one further validation path located between the first master element and the at least one slave element, wherein the at least one validation element is arranged to validate at least one of: at least one access request by the first master element; and a response to an access request from the at least one slave element.
摘要翻译：一种系统包括第一主元件; 以及布置成将第一主元件可操作地耦合到至少一个从属元件的至少一个共享通信元件。所述系统还包括位于位于所述第一主元件和所述至少一个从属元件之间的至少一个另外的验证路径上的至少一个验证元件，其中所述至少一个验证元件被布置成验证以下至少一个：至少一个由第一个主元素访问请求; 以及对来自所述至少一个从属单元的访问请求的响应。

19. 发明授权

US09904802B2 System on chip 有权
公开(公告)号：US09904802B2
公开(公告)日：2018-02-27
申请号：US14647089
申请日：2012-11-23
申请人： Michael Rohleder , Stefan Singer , Manfred Thanner
发明人： Michael Rohleder , Stefan Singer , Manfred Thanner
IPC分类号： G06F21/71 , H04L29/06 , G06F21/78 , G06F21/74 , G06F21/62
CPC分类号： G06F21/71 , G06F21/6218 , G06F21/74 , G06F21/78 , G06F2217/66 , H04L63/105
摘要： A system on chip having two or more responder units and two or more protection units is provided. Each of the responder units comprises a set of responder elements. Each of the protection units is associated with and protects one of the responder units and is arranged to provide a group mapping. The group mapping assigns one or more group identifiers to each of the responder elements of the respective responder unit.

20. 发明授权

US09336411B2 System on chip 有权
标题翻译：片上系统
公开(公告)号：US09336411B2
公开(公告)日：2016-05-10
申请号：US14442241
申请日：2012-11-23
申请人： Michael Rohleder , Stefan Singer , Manfred Thanner
发明人： Michael Rohleder , Stefan Singer , Manfred Thanner
IPC分类号： G06F21/71 , G06F21/74 , G06F21/78 , G06F21/80
CPC分类号： G06F21/71 , G06F21/74 , G06F21/78 , G06F21/805 , G06F2213/0038
摘要： In a system on chip responder units comprise one or more responder elements and is associated with one or more protection units. A request analysis unit is arranged to receive from a requesting requestor unit a request for access to one or more target responder elements among responder elements within a target responder unit among the responder units. The request analysis unit determines relevant protection data based on the request and an authorization list, which comprises one or more entries For each entry of the authorization list: taking access requirements specified by the respective entry into account if one or more of the target responder elements are part of the group of responder elements specified by the respective entry. The request analysis unit provides the relevant protection data to one or more target protection unit(s) associated with the responder unit(s), and located in a hierarchical path between the requesting requestor unit requestor unit and the target responder unit. The target protection unit(s) are arranged to perform a protective action for the target responder elements based on relevant protection data.
摘要翻译：在系统片上响应器单元包括一个或多个应答器元件并与一个或多个保护单元相关联。请求分析单元被配置为从请求请求者单元接收对应答单元中的目标响应器单元内的响应者元素中的一个或多个目标响应者元素的访问请求。所述请求分析单元基于所述请求和授权列表来确定相关的保护数据，所述授权列表包括一个或多个条目对于授权列表的每个条目：如果一个或多个目标响应者元素考虑到由相应条目指定的访问要求是由相应条目指定的响应者元素组的一部分。请求分析单元将相关保护数据提供给与应答单元相关联的一个或多个目标保护单元，并且位于请求请求单元请求单元与目标应答单元之间的分层路径中。目标保护单元被设置为基于相关保护数据对目标响应者元素执行保护动作。

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