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11. 发明授权

US07205673B1 Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processing 有权
标题翻译：在Cu / Low-k BEOL处理过程中，通过掺杂在焊盘中使用的铝来减少或消除后引线键合模具中的IMC裂纹
公开(公告)号：US07205673B1
公开(公告)日：2007-04-17
申请号：US11283044
申请日：2005-11-18
申请人： Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Sey-Shing Sun , Hong Ying , Chiyi Kao
发明人： Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Sey-Shing Sun , Hong Ying , Chiyi Kao
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/53219 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05147 , H01L2224/05624 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/48507 , H01L2224/48624 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/04953 , H01L2924/181 , H01L2924/351 , H01L2924/00014 , H01L2924/00
摘要： A bond pad structure which includes an aluminum bond pad which include one or more dopants that effectively control the growth of IMC to a nominal level in spite of high tensile stresses in the wafer. For example, aluminum can be doped with 1–2 atomic % of Mg. Alternatively, Pd or Si can be used, or elements like Cu or Si can be used as the dopant in order to reduce the overall tensile stresses in the wafer. This can control the abnormal growth of IMC, thus arresting the IMC crack formation. A combination of dopants can be used to both control the tensile stresses and also slightly alter the gold-Aluminum interface thus enabling a uniform and thin IMC formation. This tends to reduce or eliminate any voiding or cracking which would otherwise occur at the wire bond transfer.
摘要翻译：一种接合焊盘结构，其包括铝接合焊盘，其包括一个或多个掺杂剂，其有效地将IMC的生长控制到标称电平，尽管晶片中存在高拉伸应力。例如，铝可以掺杂1-2原子％的Mg。或者，可以使用Pd或Si，或者可以使用诸如Cu或Si的元素作为掺杂剂，以便降低晶片中的整体拉伸应力。这可以控制IMC的异常生长，从而阻止IMC裂纹形成。可以使用掺杂剂的组合来控制拉伸应力并且还稍微改变金 - 铝界面，从而实现均匀和薄的IMC形成。这倾向于减少或消除否则在引线键合转移时会发生的任何空隙或裂纹。

12. 发明申请

US20060063338A1 Shallow trench isolation depth extension using oxygen implantation 审中-公开
标题翻译：浅沟槽隔离深度延长使用氧气注入
公开(公告)号：US20060063338A1
公开(公告)日：2006-03-23
申请号：US10946030
申请日：2004-09-20
申请人： Santosh Menon , Hemanshu Bhatt
发明人： Santosh Menon , Hemanshu Bhatt
IPC分类号： H01L21/336
CPC分类号： H01L21/26533 , H01L21/02118 , H01L21/02137 , H01L21/02164 , H01L21/3122 , H01L21/3124 , H01L21/76224 , H01L21/76237 , H01L21/76283 , H01L29/78609
摘要： The present invention is directed to structures and fabrication methods used to construct an improved shallow trench isolation structure are disclosed. The method involves providing a semiconductor substrate having a shallow isolation trench. The trench is implanted with oxygen to form an implanted region at the bottom of the trench. The trench is filled with dielectric materials. The substrate is planarized and then annealed to complete formation of the isolation structure. A structure having an improved isolation structure is also disclosed. The structure comprises a substrate configured to include a shallow trench that is filled with dielectric material. An insulating extension is formed by oxygen implantation of the regions underlying the shallow trench.
摘要翻译：本发明涉及用于构造改进的浅沟槽隔离结构的结构和制造方法。该方法包括提供具有浅隔离沟槽的半导体衬底。沟槽被注入氧气以在沟槽的底部形成注入区域。沟槽填充介电材料。将基材平面化，然后退火以完成隔离结构的形成。还公开了具有改进的隔离结构的结构。该结构包括被配置为包括填充有电介质材料的浅沟槽的衬底。通过浅沟槽下面的区域的氧注入形成绝缘延伸。

13. 发明申请

US20120019072A1 POWER CONVERSION FOR DISTRIBUTED DC SOURCE ARRAY 有权
标题翻译：用于分布式直流电源阵列的功率转换
公开(公告)号：US20120019072A1
公开(公告)日：2012-01-26
申请号：US12840130
申请日：2010-07-20
申请人： Sunit Tyagi , Hemanshu Bhatt
发明人： Sunit Tyagi , Hemanshu Bhatt
IPC分类号： H02J1/10
CPC分类号： H02M7/537 , H02J3/383 , H02M7/493 , H02M2007/4815 , Y02B70/1441 , Y02E10/563 , Y10T307/50 , Y10T307/658 , Y10T307/713
摘要： Embodiments related to the conversion of DC power to AC power are disclosed. For example, one disclosed embodiment provides a power conversion system, comprising a plurality of direct current (DC) power sources, a plurality of power output circuits connected to one another in a parallel arrangement, each power output circuit being connected to a corresponding DC power source to receive power from the corresponding DC power source and to selectively discharge power received from the corresponding DC power source, a power combiner configured to combine power received from the plurality of power output circuits to form a combined power signal, an output stage configured to convert the combined power signal into an AC signal or a DC signal, and a controller in electrical communication with each power outlet circuit and the power combiner to control the output of power by the power converter.
摘要翻译：公开了将直流电转换为交流电力的实施例。例如，一个公开的实施例提供了一种功率转换系统，其包括多个直流（DC）电源，多个以并联装置彼此连接的功率输出电路，每个功率输出电路连接到相应的直流电力源极，用于从相应的直流电源接收电力并选择性地放电从相应的直流电源接收的功率;功率组合器，被配置为组合从多个功率输出电路接收的功率以形成组合的功率信号;输出级，被配置为将组合的功率信号转换为AC信号或DC信号，以及与每个电源插座电路和功率组合器电连接的控制器，以通过功率转换器来控制功率的输出。

14. 发明申请

US20070114667A1 Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing 有权
标题翻译：在Cu / Low-K BEOL处理期间，替代焊盘结构/钝化整合方案以减少或消除后引线键合模具中的IMC裂纹
公开(公告)号：US20070114667A1
公开(公告)日：2007-05-24
申请号：US11283219
申请日：2005-11-18
申请人： Hemanshu Bhatt , Dilip Vijay , Jayanthi Pallinti , Sey-Shing Sun , Hong Ying , Chiyi Kao
发明人： Hemanshu Bhatt , Dilip Vijay , Jayanthi Pallinti , Sey-Shing Sun , Hong Ying , Chiyi Kao
IPC分类号： H01L23/52
CPC分类号： H05K1/0271 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05009 , H01L2224/05073 , H01L2224/05553 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/05647 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/48507 , H01L2224/48624 , H01L2224/48647 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/04953 , H01L2924/05042 , H01L2924/181 , H01L2924/351 , H05K3/107 , Y10T428/12396 , H01L2924/00014 , H01L2924/00
摘要： Passivation integration schemes and pad structures to reduce the stress gradients and/or improve the contact surface existing between the Al in the pad and the gold wire bond. One of the pad structures provides a plurality of recessed pad areas which are formed in a single aluminum pad. An oxide mesa can be provided under the aluminum pad. Another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a copper pad and a plurality of trench/via pads. Still another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a portion of a copper pad, such that the aluminum pad and the copper pad are staggered relative to each other.
摘要翻译：钝化整合方案和焊盘结构以减少应力梯度和/或改善焊盘中的Al和金线键之间存在的接触表面。垫结构之一提供了形成在单个铝垫中的多个凹陷区域。可以在铝垫下方设置氧化物台面。另一个垫结构提供形成在单个铝垫中的单个凹陷区域，并且铝垫设置在铜焊盘和多个沟槽/通孔焊盘之上。另一个衬垫结构提供形成在单个铝垫中的单个凹陷区域，并且铝垫设置在铜垫的一部分上方，使得铝垫和铜垫相对于彼此交错。

15. 发明申请

US20060281256A1 Self-aligned cell integration scheme 失效
标题翻译：自对准单元集成方案
公开(公告)号：US20060281256A1
公开(公告)日：2006-12-14
申请号：US11312849
申请日：2005-12-20
申请人： Richard Carter , Hemanshu Bhatt , Shiqun Gu , Peter Burke , James Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
发明人： Richard Carter , Hemanshu Bhatt , Shiqun Gu , Peter Burke , James Elmer , Sey-Shing Sun , Byung-Sung Kwak , Verne Hornback
IPC分类号： H01L21/336
CPC分类号： H01L51/0018 , B82Y10/00 , H01L27/283 , H01L51/0048 , H01L51/0545 , Y10S977/742
摘要： A method of forming a self-aligned logic cell. A nanotube layer is formed over the bottom electrode. A clamp layer is formed over the nanotube layer. The clamp layer covers the nanotube layer, thereby protecting the nanotube layer. A dielectric layer is formed over the clamp layer. The dielectric layer is etched. The clamp layer provides an etch stop and protects the nanotube layer. The clamp layer is etched with an isotropic etchant that etches the clamp layer underneath the dielectric layer, creating an overlap of the dielectric layer, and causing a self-alignment between the clamp layer and the dielectric layer. A spacer layer is formed over the nanotube layer. The spacer layer is etched except for a ring portion around the edge of the dielectric layer. The nanotube layer is etched except for portions that are underlying at least one of the clamp layer, the dielectric layer, and the spacer layer, thereby causing a self-alignment between the clamp layer, the overlap to the dielectric layer, the spacer layer, and the nanotube layer.
摘要翻译：一种形成自对准逻辑单元的方法。在底部电极上形成纳米管层。在纳米管层上形成夹层。夹层覆盖纳米管层，从而保护纳米管层。在钳位层上形成电介质层。蚀刻介电层。钳位层提供蚀刻停止并保护纳米管层。用各向同性蚀刻剂蚀刻钳夹层，蚀刻介质层下方的夹层，产生电介质层的重叠，并引起钳位层和电介质层之间的自对准。在纳米管层上形成间隔层。除了围绕电介质层的边缘的环形部分之外，蚀刻间隔层。除了夹持层，电介质层和间隔层中的至少一个的部分以外，蚀刻纳米管层，从而导致夹紧层之间的自对准，与电介质层的重叠，间隔层，和纳米管层。

16. 发明授权

US08552560B2 Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processing 有权
标题翻译：在Cu / Low-K BEOL处理期间，替代焊盘结构/钝化整合方案以减少或消除后引线键合模具中的IMC裂纹
公开(公告)号：US08552560B2
公开(公告)日：2013-10-08
申请号：US11283219
申请日：2005-11-18
申请人： Hemanshu Bhatt , Dilip Vijay , Jayanthi Pallinti , Sey-Shing Sun , Hong Ying , Chiyi Kao
发明人： Hemanshu Bhatt , Dilip Vijay , Jayanthi Pallinti , Sey-Shing Sun , Hong Ying , Chiyi Kao
IPC分类号： H01L21/31
CPC分类号： H05K1/0271 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05009 , H01L2224/05073 , H01L2224/05553 , H01L2224/05556 , H01L2224/05558 , H01L2224/05624 , H01L2224/05647 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/48507 , H01L2224/48624 , H01L2224/48647 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/04953 , H01L2924/05042 , H01L2924/181 , H01L2924/351 , H05K3/107 , Y10T428/12396 , H01L2924/00014 , H01L2924/00
摘要： Passivation integration schemes and pad structures to reduce the stress gradients and/or improve the contact surface existing between the Al in the pad and the gold wire bond. One of the pad structures provides a plurality of recessed pad areas which are formed in a single aluminum pad. An oxide mesa can be provided under the aluminum pad. Another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a copper pad and a plurality of trench/via pads. Still another pad structure provides a single recessed pad area which is formed in a single aluminum pad, and the aluminum pad is disposed above a portion of a copper pad, such that the aluminum pad and the copper pad are staggered relative to each other.
摘要翻译：钝化整合方案和焊盘结构以减少应力梯度和/或改善焊盘中的Al和金线键之间存在的接触表面。垫结构之一提供了形成在单个铝垫中的多个凹陷区域。可以在铝垫下方设置氧化物台面。另一个垫结构提供形成在单个铝垫中的单个凹陷区域，并且铝垫设置在铜焊盘和多个沟槽/通孔焊盘之上。另一个衬垫结构提供形成在单个铝垫中的单个凹陷区域，并且铝垫设置在铜垫的一部分上方，使得铝垫和铜垫相对于彼此交错。

17. 发明授权

US08076779B2 Reduction of macro level stresses in copper/low-K wafers 有权
标题翻译：降低铜/低K晶片的宏观水平应力
公开(公告)号：US08076779B2
公开(公告)日：2011-12-13
申请号：US11269275
申请日：2005-11-08
申请人： Sey-Shing Sun , Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Hong Ying , Chiyi Kao , Peter Burke
发明人： Sey-Shing Sun , Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Hong Ying , Chiyi Kao , Peter Burke
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/04042 , H01L2224/05124 , H01L2224/05147 , H01L2224/05624 , H01L2224/05644 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48453 , H01L2224/48463 , H01L2224/48507 , H01L2224/48624 , H01L2224/48644 , H01L2224/48699 , H01L2224/48724 , H01L2224/48744 , H01L2224/48824 , H01L2224/48844 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/04953 , H01L2924/14 , H01L2924/181 , H01L2924/351 , H01L2924/00014 , H01L2924/00 , H01L2924/00015
摘要： A pad structure and passivation scheme which reduces or eliminates IMC cracking in post wire bonded dies during Cu/Low-k BEOL processing. A thick 120 nm barrier layer can be provided between a 1.2 μm aluminum layer and copper. Another possibility is to effectively split up the barrier layer, where the aluminum layer is disposed between the two barrier layers. The barrier layers may be 60 nm while the aluminum layer which is disposed between the barrier layers may be 0.6 μm. Another possibility is provide an extra 0.6 μm aluminum layer on the top barrier layer. Still another possibility is to provide an extra barrier layer on the top-most aluminum layer, such that a top barrier layer of 60 nm is provided on a 0.6 μm aluminum layer, followed by another harrier layer of 60 nm, another aluminum layer of 0.6 μm and another barrier layer of 60 nm.
摘要翻译：一种衬垫结构和钝化方案，可在Cu / Low-k BEOL处理期间减少或消除后引线键合模具中的IMC裂纹。可以在1.2μm的铝层和铜之间设置厚120nm的阻挡层。另一种可能性是有效地分离阻挡层，其中铝层设置在两个阻挡层之间。阻挡层可以是60nm，而设置在阻挡层之间的铝层可以是0.6μm。另一种可能性是在顶部阻挡层上提供额外的0.6μm的铝层。另一种可能性是在最顶层的铝层上提供额外的阻挡层，使得在0.6μm的铝层上设置60nm的顶部阻挡层，接着是60nm的另一个阻挡层，另一个为0.6的铝层 μm，另一个阻挡层为60nm。

18. 发明申请

US20070123024A1 Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processing 失效
标题翻译：消除后引线键合芯片中的IMC裂纹：在Cu / Low-K处理期间通过改变介电层/金属膜堆叠层的宏观级应力降低
公开(公告)号：US20070123024A1
公开(公告)日：2007-05-31
申请号：US11290087
申请日：2005-11-30
申请人： Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Sey-Shing Sun , Hong Ying , Chiyi Kao , Peter Burke , Ramaswamy Ranganathan , Qwai Low
发明人： Jayanthi Pallinti , Dilip Vijay , Hemanshu Bhatt , Sey-Shing Sun , Hong Ying , Chiyi Kao , Peter Burke , Ramaswamy Ranganathan , Qwai Low
IPC分类号： H01L21/4763
CPC分类号： H01L21/76801 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05556 , H01L2224/05624 , H01L2224/45124 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/48507 , H01L2224/48624 , H01L2224/48724 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/04953 , H01L2924/05042 , H01L2924/181 , H01L2924/351 , H01L2924/00
摘要： Different ways to reduce or eliminate the IMC cracking issues in wire bonded parts, including: changing to more compressive dielectric films for top, R1, and R2; changing the top passivation film stacks to more compressive films; changing the low k film to a higher compressive film; reducing the R layer thickness and pattern density to reduce tensile stress; and minimizing anneal and dielectric deposition temperatures. Each of the methods can be used individually or in combination with each other to reduce overall tensile stresses in the Cu/low-k wafer thus reducing or eliminating the IMC cracking issue currently seen in the post wire bonded parts.
摘要翻译：减少或消除引线接合部件中的IMC裂纹问题的不同方法，包括：改变为顶部R 1和R 2的更多的压电绝缘膜; 将顶部钝化膜堆叠更改为更多的压缩膜; 将低k膜改为较高的压缩膜; 降低R层厚度和图案密度以降低拉伸应力; 并最小化退火和介电沉积温度。每个方法可以单独使用或彼此组合使用以减少Cu / low-k晶片中的总拉伸应力，从而减少或消除了现在在后引线接合部件中看到的IMC裂纹问题。

19. 发明申请

US20060278902A1 Nano structure electrode design 有权
标题翻译：纳米结构电极设计
公开(公告)号：US20060278902A1
公开(公告)日：2006-12-14
申请号：US11270104
申请日：2005-11-09
申请人： Sey-Shing Sun , Hemanshu Bhatt , Peter Burke , Richard Carter
发明人： Sey-Shing Sun , Hemanshu Bhatt , Peter Burke , Richard Carter
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： G11C13/025 , B82Y10/00 , H01L51/0048 , H01L51/0595 , Y10S977/724
摘要： A microelectronic switch having a substrate layer, an electrically conductive switching layer formed on the substrate layer, an electrically conductive cavity layer formed on the switching layer, an electrically conductive cap layer formed on the cavity layer, the cap layer forming a first electrode and a second electrode that are physically and electrically separated one from another, and which both at least partially overlie the switching layer, and a cavity disposed between the switching layer and the second electrode, where the switching is layer is flexible to make electrical contact with the second electrode by flexing through the cavity upon selective application of an electrical bias.
摘要翻译：具有衬底层的微电子开关，形成在衬底层上的导电开关层，形成在开关层上的导电腔层，形成在腔层上的导电帽层，形成第一电极的帽层和第二电极在物理上和电气上彼此分离，并且至少部分地覆盖在开关层上，并且设置在开关层和第二电极之间的空腔，其中开关层是柔性的，以与第二电极电接触电极通过在选择性地施加电偏压时通过空腔弯曲。

20. 发明申请

US20050003562A1 Integrated circuit with inductor having horizontal magnetic flux lines 有权
标题翻译：具有水平磁通线的电感的集成电路
公开(公告)号：US20050003562A1
公开(公告)日：2005-01-06
申请号：US10614307
申请日：2003-07-02
申请人： Hemanshu Bhatt , Jan Fure , Derryl Allman
发明人： Hemanshu Bhatt , Jan Fure , Derryl Allman
IPC分类号： H01L21/00 , H01L21/02 , H01L23/522
CPC分类号： H01L28/10 , H01L23/5227 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit (IC) includes one or more inductors that have magnetic flux lines substantially parallel to a generally horizontal plane of the IC. The inductor is formed in a plurality of conductor layers separated by insulating layers of the IC. Regions of highest magnetic flux density of the inductor may preferably be located near the edge of the IC. Additionally, the inductor may preferably be segmented. The over-all inductance may preferably be controlled by turning on and off selected inductors or inductor segments.
摘要翻译：集成电路（IC）包括具有基本上平行于IC的大致水平面的磁通线的一个或多个电感器。电感器形成在由IC的绝缘层分离的多个导体层中。电感器的最大磁通密度的区域优选地位于IC边缘附近。另外，电感器可以优选地被分段。可以优选地通过接通和关断所选择的电感器或电感器段来控制全部电感。

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