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11. 发明授权

US5896513A Computer system providing a universal architecture adaptive to a variety of processor types and bus protocols 失效
标题翻译：计算机系统提供了适用于各种处理器类型和总线协议的通用架构
公开(公告)号：US5896513A
公开(公告)日：1999-04-20
申请号：US675723
申请日：1996-07-03
申请人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
发明人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
IPC分类号： G06F13/16 , G06F13/18 , G06F13/36 , G06F13/40 , G06F13/14
CPC分类号： G06F13/4027 , G06F13/4063
摘要： A computer system providing a universal architecture includes a processor card connected to a system bus of a host computer system. The processor card is adapted for insertion into a slot of the computer system and houses a processor and a bus bridge conversion device. The processor operates according to a signaling protocol which is different than the signaling protocol of the computer system bus. The bus conversion device converts the signaling protocol of the system bus to the signaling protocol of the processor, and vice-versa. The bus conversion device includes logic for bus arbitration conversion, bus lock conversion, and cache coherency control. Logic is also included that converts incoming and outgoing requests so that the card may properly transact with other agents coupled to the bus.
摘要翻译：提供通用架构的计算机系统包括连接到主计算机系统的系统总线的处理器卡。处理器卡适于插入到计算机系统的插槽中并且容纳处理器和总线桥转换装置。处理器根据与计算机系统总线的信令协议不同的信令协议进行操作。总线转换装置将系统总线的信令协议转换为处理器的信令协议，反之亦然。总线转换装置包括用于总线仲裁转换，总线锁转换和高速缓存一致性控制的逻辑。还包括逻辑，可转换传入和传出的请求，以便卡可以与耦合到总线的其他代理进行正确的交互。

12. 发明授权

US5784579A Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth 失效
标题翻译：基于总线管线深度从总线代理动态控制总线访问的方法和装置
公开(公告)号：US5784579A
公开(公告)日：1998-07-21
申请号：US709214
申请日：1996-09-06
申请人： Stephen S. Pawlowski , Nitin V. Sarangdhar , Michael W. Rhodehamel , Matthew A. Fisch , Peter D. MacWilliams
发明人： Stephen S. Pawlowski , Nitin V. Sarangdhar , Michael W. Rhodehamel , Matthew A. Fisch , Peter D. MacWilliams
IPC分类号： G06F13/38 , G06F13/40 , G06F13/42
CPC分类号： G06F13/387 , G06F13/4027 , G06F13/4217
摘要： A dynamic pipeline depth control method and apparatus is used with a bus which supports pipelined bus transactions. An agent coupled to the bus includes both a transmitter and a receiver. The transmitter is used to transmit an indication to the other agents coupled to the bus which prevents the other agents from issuing a transaction on the bus. The receiver is used to receive the indication, from another agent, that prevents the agent from issuing a transaction on the bus.
摘要翻译：动态流水线深度控制方法和装置与支持流水线总线事务的总线一起使用。耦合到总线的代理包括发射机和接收机。发射机用于向耦合到总线的其他代理发送指示，防止其他代理在总线上发出交易。接收机用于从另一代理接收指示，阻止代理在总线上发出交易。

13. 发明授权

US5778441A Method and apparatus for accessing split lock variables in a computer system 失效
标题翻译：用于访问计算机系统中的分裂锁定变量的方法和装置
公开(公告)号：US5778441A
公开(公告)日：1998-07-07
申请号：US764663
申请日：1996-12-11
申请人： Michael W. Rhodehamel , Nitin V. Sarangdhar , Matthew A. Fisch
发明人： Michael W. Rhodehamel , Nitin V. Sarangdhar , Matthew A. Fisch
IPC分类号： G06F13/16 , G06F12/00 , G06F13/00
CPC分类号： G06F13/1652
摘要： Atomicity of lock variables is preserved in a computer system in response to a request by a microprocessor for a bus lock access whether the lock variable is split between two cache lines or is within a single cache line. A non-split lock bus access which can be satisfied by a cacheable region within the same cluster as the microprocessor issuing the access is allowed to complete, regardless of whether ownership of the next level bus is available. If the non-split lock access can not be satisfied within the cluster, then ownership of the next level bus is obtained, if available, to satisfy the access. Similarly, a split lock access may complete if ownership of the second level bus can be obtained. However, a split lock access is aborted if the second level bus ownership is not available, regardless of whether a cacheable region within the same cluster can satisfy the request.
摘要翻译：响应于微处理器对于总线锁定访问的请求，锁定变量的原子性被保留在计算机系统中，无论锁定变量是在两个高速缓存行之间分离还是在单个高速缓存行内。允许通过与发出访问的微处理器相同的集群内的可缓存区域来满足的非分裂锁总线访问，而不管下一级总线的所有权是否可用。如果在集群内不能满足非分裂锁访问，则获得下一级总线的所有权（如果可用）以满足访问。类似地，如果可以获得第二级总线的所有权，则分裂锁定访问可以完成。但是，如果第二级总线所有权不可用，则无论同一个集群中的可缓存区域是否满足请求，则会中断拆分锁访问。

14. 发明授权

US06268749B1 Core clock correction in a 2/n mode clocking scheme 有权
标题翻译： 2 / n模式计时方案的核心时钟校正
公开(公告)号：US06268749B1
公开(公告)日：2001-07-31
申请号：US09586396
申请日：2000-05-31
申请人： Matthew A. Fisch , Chakrapani Pathikonda , Javed S. Barkatullah
发明人： Matthew A. Fisch , Chakrapani Pathikonda , Javed S. Barkatullah
IPC分类号： H03L700
CPC分类号： G06F1/12
摘要： A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
摘要翻译： 2 / N模式时钟发生器，其通过使用总线时钟使能信号来产生总线时钟信号，从而选择与核心时钟信号同相和异相的总线时钟脉冲。时钟发生器保持总线时钟信号和核心时钟信号之间的同步，使得它们总是处于预定的相位关系。

15. 发明授权

US06208180B1 Core clock correction in a 2/N mode clocking scheme 有权
标题翻译：核心时钟校正在2 / N模式计时方案
公开(公告)号：US06208180B1
公开(公告)日：2001-03-27
申请号：US09170997
申请日：1998-10-13
申请人： Matthew A. Fisch , Chakrapani Pathikonda , Javed S. Barkatullah
发明人： Matthew A. Fisch , Chakrapani Pathikonda , Javed S. Barkatullah
IPC分类号： H03L700
CPC分类号： G06F1/12
摘要： A 2/N mode dock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
摘要翻译：通过使用总线时钟使能信号来选择与核心时钟信号同相和异相的总线时钟脉冲来产生总线时钟信号的2 / N模式发射器。时钟发生器保持总线时钟信号和核心时钟信号之间的同步，使得它们总是处于预定的相位关系。

16. 发明授权

US6114887A Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme 失效
标题翻译：用于以2 / N模式计时方案产生具有1 / N特性的总线时钟信号的装置
公开(公告)号：US6114887A
公开(公告)日：2000-09-05
申请号：US971939
申请日：1997-11-17
申请人： Chakrapani Pathikonda , Matthew A. Fisch , Michael W. Rhodehamel
发明人： Chakrapani Pathikonda , Matthew A. Fisch , Michael W. Rhodehamel
IPC分类号： G06F1/12 , H03K1/04
CPC分类号： G06F1/12
摘要： A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
摘要翻译： 2 / N模式时钟发生器，其通过使用总线时钟使能信号来产生总线时钟信号，从而选择与核心时钟信号同相和异相的总线时钟脉冲。时钟发生器维持总线时钟信号和核心时钟信号之间的同步，使得它们总是处于预定的相位关系。

17. 发明授权

US6006299A Apparatus and method for caching lock conditions in a multi-processor system 失效
标题翻译：用于在多处理器系统中缓存锁定条件的装置和方法
公开(公告)号：US6006299A
公开(公告)日：1999-12-21
申请号：US204592
申请日：1994-03-01
申请人： Wen-Hann Wang , Konrad K. Lai , Gurbir Singh , Mandar S. Joshi , Nitin V. Sarangdhar , Matthew A. Fisch
发明人： Wen-Hann Wang , Konrad K. Lai , Gurbir Singh , Mandar S. Joshi , Nitin V. Sarangdhar , Matthew A. Fisch
IPC分类号： G06F9/46 , G06F13/08
CPC分类号： G06F9/52
摘要： In a computer system, an apparatus for handling lock conditions wherein a first instruction executed by a first processor processes data that is common to a second processor while the second processor is locked from simultaneously executing a second instruction that also processes this same data. A lock bit is set when the first processor begins execution of the first instruction. Thereupon, the second processor is prevented from executing its instruction until the first processor has completed its processing of the shared data. Hence, the second processor queues its request in a buffer. The lock bit is cleared after the first processor has completed execution of its instruction. The first processor then checks the buffer for any outstanding requests. In response to the second processor's queued request, the first processor transmits a signal to the second processor indicating that the data is now not locked.
摘要翻译：在计算机系统中，一种用于处理锁定条件的装置，其中由第一处理器执行的第一指令在第二处理器被锁定时处理与第二处理器相同的数据，同时执行也处理该相同数据的第二指令。当第一个处理器开始执行第一个指令时，锁定位被置位。于是，第二处理器被阻止执行其指令，直到第一处理器完成对共享数据的处理。因此，第二处理器将其请求排队在缓冲器中。在第一个处理器完成其指令执行后，锁定位被清零。然后，第一个处理器检查缓冲区是否有任何未完成的请求。响应于第二处理器的排队请求，第一处理器向第二处理器发送指示数据现在不被锁定的信号。

18. 发明授权

US5802132A Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme 失效
公开(公告)号：US5802132A
公开(公告)日：1998-09-01
申请号：US708928
申请日：1996-09-06
申请人： Chakrapani Pathikonda , Matthew A. Fisch , Michael W. Rhodehamel
发明人： Chakrapani Pathikonda , Matthew A. Fisch , Michael W. Rhodehamel
IPC分类号： G06F1/12 , H03K21/00
CPC分类号： G06F1/12
摘要： A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.

19. 发明授权

US5774700A Method and apparatus for determining the timing of snoop windows in a pipelined bus 失效
标题翻译：用于确定流水线总线中的窥探窗口的定时的方法和装置
公开(公告)号：US5774700A
公开(公告)日：1998-06-30
申请号：US425370
申请日：1995-04-20
申请人： Matthew A. Fisch , Nitin V. Sarangdhar
发明人： Matthew A. Fisch , Nitin V. Sarangdhar
IPC分类号： G06F12/08 , G06F1/04
CPC分类号： G06F12/0831
摘要： A method and apparatus for determining the timing of snoop windows in a pipelined bus includes a snoop timer, a snoop counter, and snoop resolution logic. The snoop timer indicates the number of clocks until the next snoop window. The snoop counter keeps track of the number of snoop windows currently being tracked by the apparatus and is updated by the snoop resolution logic. In one embodiment, the snoop resolution logic updates the snoop counter when a snoop event occurs on the bus. In one embodiment, the apparatus also includes snoop drive logic which drives snoop result signals onto the bus during snoop windows.
摘要翻译：用于确定流水线总线中的窥探窗口的定时的方法和装置包括窥探定时器，窥探计数器和窥探分辨率逻辑。监听定时器指示下一个监听窗口之前的时钟数。窥探计数器跟踪当前由设备跟踪的窥探窗口的数量，并由窥探分辨率逻辑更新。在一个实施例中，当在总线上发生窥探事件时，窥探分辨率逻辑更新窥探计数器。在一个实施例中，该装置还包括窥探驱动逻辑，其在窥探窗口期间将窥探结果信号驱动到总线上。

20. 发明授权

US5764934A Processor subsystem for use with a universal computer architecture 失效
标题翻译：处理器子系统，用于通用计算机体系结构
公开(公告)号：US5764934A
公开(公告)日：1998-06-09
申请号：US675854
申请日：1996-07-03
申请人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
发明人： Matthew A. Fisch , James E. Jacobson, Jr. , Michael W. Rhodehamel
IPC分类号： G06F13/36 , G06F13/38 , G06F13/40 , G06F13/42 , G06F15/76
CPC分类号： G06F13/4027
摘要： A processor subsystem includes a processor and a bus bridge conversion device for insertion into a slot of a host computer system. The processor operates according to a signaling protocol which is different than the signaling protocol of the computer system bus. The bus conversion device converts the signaling protocol of the system bus to the signaling protocol of the processor, and vice-versa. The bus conversion device includes logic for bus arbitration conversion, bus lock conversion, and cache coherency control. Logic is also included that converts incoming and outgoing requests so that the card may properly transact with other agents coupled to the bus.
摘要翻译：处理器子系统包括用于插入到主计算机系统的时隙中的处理器和总线桥转换装置。处理器根据与计算机系统总线的信令协议不同的信令协议进行操作。总线转换装置将系统总线的信令协议转换为处理器的信令协议，反之亦然。总线转换装置包括用于总线仲裁转换，总线锁转换和高速缓存一致性控制的逻辑。还包括逻辑，可转换传入和传出的请求，以便卡可以与耦合到总线的其他代理进行正确的交互。

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