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11. 发明授权

US06205462B1 Digital multiply-accumulate circuit that can operate on both integer and floating point numbers simultaneously 有权
标题翻译：可同时对整数和浮点数进行操作的数字乘法累加电路
公开(公告)号：US06205462B1
公开(公告)日：2001-03-20
申请号：US09414322
申请日：1999-10-06
申请人： David C. Wyland , David A. Harrison
发明人： David C. Wyland , David A. Harrison
IPC分类号： G06F744
CPC分类号： G06F7/5443 , G06F2207/3824
摘要： Disclosed is a Multiply-Accumulate circuit that includes an exponent adder circuit, a mantissa multiplier circuit, a shifter, a full adder, and an accumulator. The product adder circuit receives two operands in a special combined data format which prescribes a mantissa and an exponent for both integer and floating point operands. The exponent adder circuit adds the exponents of the two operands. But if before the addition the exponent adder circuit detects an integer as an operand, it replaces the exponent of the integer by a substitute value in that addition. This substitute value is related to the number of bits of the mantissa of the integer. The mantissa multiplier circuit multiplies the two mantissas of the two operands. The shifter shifts the resultant product of multiplication into a pre-defined fixed point format according to the resultant sum of the addition generated by the exponent adder circuit. The full adder adds this shifted product to the current content of the accumulator.
摘要翻译：公开了一种乘法累加电路，其包括指数加法器电路，尾数乘法器电路，移位器，全加器和累加器。产品加法器电路以特殊的组合数据格式接收两个操作数，它们规定了整数和浮点操作数的尾数和指数。指数加法器电路将两个操作数的指数相加。但是如果在加法之前，指数加法器电路检测一个整数作为一个操作数，它将以该加法代替整数的指数。该替代值与整数的尾数的位数有关。尾数乘法器电路将两个操作数的两个奇数相乘。移位器根据由指数加法器电路产生的加法结果之和将乘积乘积的乘积移位到预定义的固定点格式。全加器将此移位乘积加到累加器的当前内容。

12. 发明申请

US20130340050A1 ZERO CONFIGURATION COMMUNICATIONS BETWEEN A SANDBOXED PROGRAM AND A NETWORKED SERVICE 有权
标题翻译：沙发计划与网络服务之间的零配置通信
公开(公告)号：US20130340050A1
公开(公告)日：2013-12-19
申请号：US13967364
申请日：2013-08-15
申请人： David A. Harrison
发明人： David A. Harrison
IPC分类号： H04L29/06
CPC分类号： G06Q30/0269 , G06F3/14 , G06F17/30784 , G06F21/10 , G06F21/53 , G06F2221/033 , G06Q30/0255 , G08C17/02 , H04L12/18 , H04L61/1511 , H04L61/1541 , H04L61/2007 , H04L61/2514 , H04L61/2517 , H04L61/256 , H04L61/2575 , H04L61/6068 , H04L63/10 , H04L63/102 , H04L65/1069 , H04L65/4069 , H04L67/02 , H04L67/10 , H04L67/141 , H04L67/16 , H04N21/23424 , H04N21/2541 , H04N21/278 , H04N21/4126 , H04N21/41407 , H04N21/4147 , H04N21/435 , H04N21/4415 , H04N21/466 , H04N21/6175 , H04N21/64322 , H04N21/812 , H04N21/835 , H04N21/8352 , H04N21/8358 , H04N21/84
摘要： A method, apparatus and system related to zero configuration communication between a sandboxed program and a networked service are disclosed. In one aspect a system includes a networked device configured to announce a networked service to a discovery service, and/or perform the discovery service for a private network; and/or a client device configured to execute a sandboxed program in a security sandbox. The system also includes automatically instantiating a connection between the sandboxed program and the networked device and/or the networked service. The discovery agent may be running with the sandboxed program is configured to query the discovery service for a service information associated with of the networked device and/or the networked service. The service information may include a global unique identifier (GUID), an alphanumeric name, a public address pair, and/or a private address pair.
摘要翻译：公开了一种与沙盒程序和联网服务之间的零配置通信相关的方法，装置和系统。在一个方面，系统包括被配置为向发现服务通告联网服务的网络设备和/或为专用网络执行发现服务; 和/或被配置为在安全沙箱中执行沙箱程序的客户端设备。该系统还包括自动实例化沙盒程序与联网设备和/或联网服务之间的连接。发现代理可以运行，沙盒程序被配置为向发现服务查询与联网设备和/或联网服务相关联的服务信息。服务信息可以包括全局唯一标识符（GUID），字母数字名称，公共地址对和/或专用地址对。

13. 发明申请

US20100005470A1 METHOD AND SYSTEM FOR PERFORMING DMA IN A MULTI-CORE SYSTEM-ON-CHIP USING DEADLINE-BASED SCHEDULING 失效
标题翻译：使用基于DEADLINE的调度在多芯片系统中执行DMA的方法和系统
公开(公告)号：US20100005470A1
公开(公告)日：2010-01-07
申请号：US12167096
申请日：2008-07-02
申请人： Moshe B. Simon , Erik P. Machnicki , David A. Harrison
发明人： Moshe B. Simon , Erik P. Machnicki , David A. Harrison
IPC分类号： G06F9/46
CPC分类号： G06F13/28 , G06F13/30
摘要： A direct memory access (DMA) engine schedules data transfer requests of a system-on-chip data processing system according to both an assigned transfer priority and the deadline for completing a transfer. Transfer priority is based on a hardness representing the penalty for missing a deadline. Priorities are also assigned to zero-deadline transfer requests in which there is a penalty no matter how early the transfer completes. If desired, transfer requests may be scheduled in timeslices according to priority in order to bound the latency of lower priority requests, with the highest priority hard real-time transfers wherein the penalty for missing a deadline is severe are given the largest timeslice. Service requests for preparing a next data transfer are posted while a current transaction is in progress for maximum efficiency. Current transfers may be preempted whenever a higher urgency request is received.
摘要翻译：直接存储器访问（DMA）引擎根据分配的传送优先级和完成传送的截止时间调度片上系统数据处理系统的数据传输请求。转移优先级基于表示错过期限的惩罚的硬度。优先权也被分配到零期限转移请求，其中有罚款，无论传输完成的时间早。如果需要，可以根据优先级按照时间表调度传输请求，以便限制较低优先级请求的延迟，具有最高优先级的硬实时传输，其中丢失最后期限的惩罚是最大的时间片。在进行当前事务处理以最大效率的情况下，会发布准备下一次数据传输的服务请求。当接收到更高的紧急请求时，可以抢占当前的传输。

14. 发明授权

US5790882A Programmable logic device placement method utilizing weighting function to facilitate pin locking 失效
标题翻译：可编程逻辑器件放置方法利用加权函数来促进引脚锁定
公开(公告)号：US5790882A
公开(公告)日：1998-08-04
申请号：US746656
申请日：1996-11-13
申请人： Joshua M. Silver , David A. Harrison , Hua Xue
发明人： Joshua M. Silver , David A. Harrison , Hua Xue
IPC分类号： H03K19/173 , G06F17/50 , G06F3/00
CPC分类号： G06F17/5072 , G06F17/5054
摘要： A method for placing a logic function into the function blocks of a complex programmable logic device (CPLD) to maintain the same input/output pin locations after the logic function is subsequently modified by a user. The method utilizes a weighting function to assign portions of the logic function to the function blocks such that sufficient resources are available in each function block to implement subsequent modifications to the logic function without changing the originally-assigned input and output pin locations. For each portion of the logic function, the weighting function is employed to identify the function block which implements the portion while maximizing the available resources in all of the function blocks. If a particular equation cannot be placed, the method utilizes a corrective measure such as fitting refinement, buffering and logic reformation to place the equation. If the equation still cannot be placed, the weighting function is altered, thereby changing the criteria by which logic portions are assigned to the function blocks. The placement method is then repeated with the altered weighting function.
摘要翻译：一种用于将逻辑功能放置在复杂可编程逻辑器件（CPLD）的功能块中以在逻辑功能随后由用户修改之后保持相同的输入/输出引脚位置的方法。该方法利用加权函数将逻辑功能的部分分配给功能块，使得在每个功能块中有足够的资源可用于实现对逻辑功能的后续修改而不改变原始分配的输入和输出引脚位置。对于逻辑功能的每个部分，采用加权函数来识别实现该部分的功能块，同时使所有功能块中的可用资源最大化。如果不能放置特定的方程，则该方法利用纠正措施，例如拟合细化，缓冲和逻辑重构来排列方程。如果方程式仍然不能放置，则加权函数被改变，从而改变将逻辑部分分配给功能块的标准。然后用改变的加权函数重复放置方法。

15. 发明申请

US20120173786A1 METHOD AND SYSTEM FOR PERFORMING DMA IN A MULTI-CORE SYSTEM-ON-CHIP USING DEADLINE-BASED SCHEDULING 审中-公开
标题翻译：使用基于DEADLINE的调度在多芯片系统中执行DMA的方法和系统
公开(公告)号：US20120173786A1
公开(公告)日：2012-07-05
申请号：US13416971
申请日：2012-03-09
申请人： Moshe B. Simon , Erik P. Machnicki , David A. Harrison
发明人： Moshe B. Simon , Erik P. Machnicki , David A. Harrison
IPC分类号： G06F13/28
CPC分类号： G06F13/28 , G06F13/30
摘要： A direct memory access (DMA) engine schedules data transfer requests of a data processing system according to both an assigned transfer priority and the deadline for completing a transfer.
摘要翻译：直接存储器访问（DMA）引擎根据分配的传送优先级和完成传送的截止时间调度数据处理系统的数据传输请求。

16. 发明授权

US08151008B2 Method and system for performing DMA in a multi-core system-on-chip using deadline-based scheduling 失效
标题翻译：在使用基于时限的调度的多核片上系统片上执行DMA的方法和系统
公开(公告)号：US08151008B2
公开(公告)日：2012-04-03
申请号：US12167096
申请日：2008-07-02
申请人： Moshe B. Simon , Erik P. Machnicki , David A. Harrison
发明人： Moshe B. Simon , Erik P. Machnicki , David A. Harrison
IPC分类号： G06F13/28 , G06F13/30
CPC分类号： G06F13/28 , G06F13/30
摘要： A direct memory access (DMA) engine schedules data transfer requests of a system-on-chip data processing system according to both an assigned transfer priority and the deadline for completing a transfer. Transfer priority is based on a hardness representing the penalty for missing a deadline. Priorities are also assigned to zero-deadline transfer requests in which there is a penalty no matter how early the transfer completes. If desired, transfer requests may be scheduled in timeslices according to priority in order to bound the latency of lower priority requests, with the highest priority hard real-time transfers wherein the penalty for missing a deadline is severe are given the largest timeslice. Service requests for preparing a next data transfer are posted while a current transaction is in progress for maximum efficiency. Current transfers may be preempted whenever a higher urgency request is received.
摘要翻译：直接存储器访问（DMA）引擎根据分配的传送优先级和完成传送的截止时间调度片上系统数据处理系统的数据传输请求。转移优先级基于表示错过期限的惩罚的硬度。优先权也被分配到零期限转移请求，其中有罚款，无论传输完成的时间早。如果需要，可以根据优先级按照时间表调度传输请求，以便限制较低优先级请求的延迟，具有最高优先级的硬实时传输，其中丢失最后期限的惩罚是最大的时间片。在进行当前事务处理以最大效率的情况下，会发布准备下一次数据传输的服务请求。当接收到更高的紧急请求时，可以抢占当前的传输。

17. 发明申请

US20100192509A1 Repair Swatch For Hail Damaged Asphalt Roofing 审中-公开
标题翻译：冰雹损坏的沥青屋顶修理色板
公开(公告)号：US20100192509A1
公开(公告)日：2010-08-05
申请号：US12731088
申请日：2010-03-24
申请人： Frederick W. Sieling , William R. Carroll , David A. Harrison
发明人： Frederick W. Sieling , William R. Carroll , David A. Harrison
IPC分类号： E04B1/64 , E04D13/16 , B32B37/00
CPC分类号： E04D1/26 , E04D1/36 , E04D5/00 , E04D2001/005 , E04G23/0281 , Y10T156/10
摘要： A repair swatch (such as a patch) is provided that is preferably covered with appropriate granules on one face, with an opposite (back) face having an adhesive that allows the material to be placed over and adhere to small damaged areas of shingles and/or other types of roofing. The size, shape and color of the patch are such that it closely matches that of the existing shingle. Further, the size and shape of the patch are similar to shapes on laminated shingle products rendering the repair essentially invisible on such products.
摘要翻译：提供了修复样本（例如贴片），其优选地在一个表面上用适当的颗粒覆盖，相对（背面）的表面具有粘合剂，其允许将材料放置在并附着到带状疱疹的小损伤区域和/ 或其他类型的屋顶。贴片的尺寸，形状和颜色与现有瓦板的尺寸，形状和颜色密切相符。此外，贴片的尺寸和形状类似于层压瓦板产品上的形状，使得修复在这些产品上基本上不可见。

18. 发明授权

US07716269B2 Method and system for performing parallel integer multiply accumulate operations on packed data 有权
标题翻译：对打包数据执行并行整数乘法运算的方法和系统
公开(公告)号：US07716269B2
公开(公告)日：2010-05-11
申请号：US11153979
申请日：2005-06-16
申请人： Moshe B. Simon , Erik P. Machnicki , David A. Harrison , Rakesh K. Singh
发明人： Moshe B. Simon , Erik P. Machnicki , David A. Harrison , Rakesh K. Singh
IPC分类号： G06F7/38
CPC分类号： G06F7/49921 , G06F7/49994 , G06F7/505 , G06F7/523 , G06F7/5443 , G06F9/3001 , G06F9/30036 , G06F2207/382 , G06F2207/3828
摘要： A multiply accumulate unit (“MAC”) that performs operations on packed integer data. In one embodiment, the MAC receives 2 32-bit data words which, depending on the specified mode of operation, each contain either four 8-bit operands, two 16-bit operands, or one 32-bit operand. Depending on the mode of operation, the MAC performs either sixteen 8×8 operations, four 16×16 operations, or one 32×32 operation. Results may be individually retrieved from registers and the corresponding accumulator cleared after the read cycle. In addition, the accumulators may be globally initialized. Two results from the 8×8 operations may be packed into a single 32-bit register. The MAC may also shift and saturate the products as required.
摘要翻译：对打包的整数数据执行操作的乘法累加单元（“MAC”）。在一个实施例中，MAC接收2个32位数据字，其取决于指定的操作模式，每个包含四个8位操作数，两个16位操作数或一个32位操作数。根据操作模式，MAC执行十六个8×8操作，四个16×16操作或一个32×32操作。结果可以从寄存器单独检索，相应的累加器在读周期后清零。此外，累加器可以被全局初始化。来自8×8操作的两个结果可能被打包到单个32位寄存器中。 MAC也可能会根据需要移动和饱和产品。

19. 发明授权

US07510751B2 Molding of polypropylene with enhanced reheat characteristics 失效
标题翻译：具有增强再热特性的聚丙烯成型
公开(公告)号：US07510751B2
公开(公告)日：2009-03-31
申请号：US11877762
申请日：2007-10-24
申请人： Michael Anthony Neal , David A. Harrison , Stephen Derek Jenkins , J. Paul Davis
发明人： Michael Anthony Neal , David A. Harrison , Stephen Derek Jenkins , J. Paul Davis
IPC分类号： B29C49/02
CPC分类号： C08K3/08 , B29B11/08 , B29B11/14 , B29B2911/1402 , B29B2911/14026 , B29B2911/14033 , B29B2911/1404 , B29B2911/14106 , B29B2911/14133 , B29B2911/14326 , B29B2911/1444 , B29C47/003 , B29C47/8805 , B29C49/0005 , B29C49/06 , B29C49/12 , B29C49/4205 , B29C2035/0822 , B29K2023/12 , B29K2105/258 , B29K2623/12 , B29L2031/7158 , Y10T428/1321 , Y10T428/1352 , C08L23/12
摘要： Bottles, containers and other articles are formed from polypropylene compositions that include a reheating agent, such as antimony, carbon black, graphite, titanium, copper, manganese, iron, tungsten, graphite, infra-red absorbing dyes or other infra-red absorbing material. The reheating time for the polypropylene composition is shortened for injection stretch blow molding or thermoforming, and the polypropylene granule composition with reheating agent has an L* value of at least 80% of the L* value for a polypropylene granule control without added reheating agents as measured by the Gardner color test. The reheating agent may be incorporated into the polypropylene composition by in situ chemical reduction of a metal compound, such as antimony triglycolate, with a reducing agent, such as hypophosphorous acid. In addition, the polypropylene composition with reheating agent may be derived from a polypropylene masterbatch with high concentrations of reheating agent.
摘要翻译：瓶，容器和其它制品由包括再加热剂如锑，炭黑，石墨，钛，铜，锰，铁，钨，石墨，红外吸收染料或其它红外线吸收材料的聚丙烯组合物形成。对于注射拉伸吹塑或热成型，聚丙烯组合物的再加热时间缩短，并且具有再加热剂的聚丙烯颗粒组合物的L *值至少为聚丙烯颗粒对照的L *值的80％，而没有添加再加热剂通过加德纳颜色测试。再加热剂可以通过用还原剂如次磷酸原位化学还原金属化合物，例如三
乙酸锑锑，并入聚丙烯组合物中。此外，具有再加热剂的聚丙烯组合物可以衍生自具有高浓度再加热剂的聚丙烯母料。

20. 发明授权

US6091892A Method for mapping product terms in a complex programmable logic device 失效
标题翻译：用于在复杂可编程逻辑器件中映射产品术语的方法
公开(公告)号：US6091892A
公开(公告)日：2000-07-18
申请号：US746603
申请日：1996-11-13
申请人： Hua Xue , David A. Harrison , Joshua M. Silver
发明人： Hua Xue , David A. Harrison , Joshua M. Silver
IPC分类号： G06F17/50 , G06F3/00
CPC分类号： G06F17/5054
摘要： A method for programming complex programmable logic devices (CPLDs) to implement a logic function, whereby user-designated locked equations of the logic function are mapped into the macrocells of a function block, and then undesignated (non-locked) equations are mapped into the remaining macrocells. The method shifts product terms between the macrocells to adjust the placement arrangement of the mapped equations, thereby obtaining a placement arrangement which is both valid and meets user-defined timing constraints.
摘要翻译：一种用于编程复杂可编程逻辑器件（CPLD）以实现逻辑功能的方法，由此将逻辑功能的用户指定的锁定方程映射到功能块的宏单元中，然后将未指定（非锁定）方程映射到剩余的宏单元。该方法在宏小区之间移动产品项以调整映射方程的放置布置，从而获得既有效又满足用户定义的时序约束的放置布置。

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