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11. 发明申请

US20080052542A1 System and Method to Optimize Multi-Core Microprocessor Performance Using Voltage Offsets 失效
标题翻译：使用电压偏移优化多核微处理器性能的系统和方法
公开(公告)号：US20080052542A1
公开(公告)日：2008-02-28
申请号：US11466891
申请日：2006-08-24
申请人： Louis Bennie Capps , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
发明人： Louis Bennie Capps , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.
摘要翻译：提出了使用电压偏移来优化多核微处理器性能的系统和方法。多核设备测试每个处理器内核，以便识别每个处理器内核的最佳电源电压。反过来，该设备基于每个处理器核心的所识别的最佳电源电压来配置每个处理器核心的电压偏移网络。结果，从多核设备的主电压中减去由电压偏移网络产生的偏移电压，这导致电压偏移网络向每个处理器核提供最佳电源电压。电压偏移网络可以包括熔丝以产生固定的电压偏移，或者电压偏移网络可以包括在多核装置的操作期间动态地调节电压偏移的控制电路。

12. 发明授权

US08570820B2 Selectable repair pass masking 有权
标题翻译：可选择修复通过掩蔽
公开(公告)号：US08570820B2
公开(公告)日：2013-10-29
申请号：US13042881
申请日：2011-03-08
申请人： Kevin William Gorman , John Robert Goss , Michael Richard Ouellette , Troy Joseph Perry , Michael Anthony Ziegerhofer
发明人： Kevin William Gorman , John Robert Goss , Michael Richard Ouellette , Troy Joseph Perry , Michael Anthony Ziegerhofer
IPC分类号： G11C7/10
CPC分类号： G11C29/4401 , G11C29/76 , G11C29/802 , G11C2029/0401 , G11C2229/726
摘要： The present invention relates to a method and circuit for selectively repairing an embedded memory module having memory elements in an integrated circuit chip. The method includes performing a plurality of tests on the embedded memory module under operating conditions to identify a plurality of non-operational memory elements in the embedded memory module and, in response to identifying the non-operational memory elements, generating a plurality of corresponding repair solutions. The method further includes storing the plurality of corresponding repair solutions in a non-volatile storage element and determining from a mask a subset of the plurality of repair solutions that should be restored.
摘要翻译：本发明涉及一种用于选择性地修复在集成电路芯片中具有存储元件的嵌入式存储器模块的方法和电路。该方法包括在操作条件下对嵌入式存储器模块执行多个测试以识别嵌入式存储器模块中的多个非操作存储器元件，并且响应于识别非操作存储器元件，生成多个相应的修复解决方案该方法还包括将多个相应的修复解决方案存储在非易失性存储元件中，并且从掩模确定应该被恢复的多个修复解决方案的子集。

13. 发明授权

US07735031B2 Method and apparatus for self identification of circuitry 有权
标题翻译：用于电路自我识别的方法和装置
公开(公告)号：US07735031B2
公开(公告)日：2010-06-08
申请号：US11841125
申请日：2007-08-20
申请人： Valerie Hornbeck Chickanosky , Kevin William Gorman , Emory D. Keller , Michael Richard Ouellette
发明人： Valerie Hornbeck Chickanosky , Kevin William Gorman , Emory D. Keller , Michael Richard Ouellette
IPC分类号： G06F17/50
CPC分类号： G01R31/31724 , G01R31/31721
摘要： A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic element in the system assigns itself a unique identifier. Each logic element can then be controlled by another source or have a means to communicate with other logic elements in the system. The unique identifier enables greater system flexibility, thereby reducing cost and improving efficiency.
摘要翻译：一种包括用于启用枚举操作的控制器的系统。枚举操作由系统中的控制器（110）和逻辑元件（120）执行，使得系统中的每个逻辑元件分配自身唯一的标识符。然后，每个逻辑元件可以被另一个源控制，或者具有与系统中的其它逻辑元件通信的手段。独特的标识符可以实现更大的系统灵活性，从而降低成本并提高效率。

14. 发明申请

US20090052609A1 METHOD AND APPARATUS FOR SELF IDENTIFICATION OF CIRCUITRY 有权
标题翻译：自动识别电路的方法和装置
公开(公告)号：US20090052609A1
公开(公告)日：2009-02-26
申请号：US11841125
申请日：2007-08-20
申请人： Valerie Hornbeck Chickanosky , Kevin William Gorman , Emory D. Keller , Michael Richard Ouellette
发明人： Valerie Hornbeck Chickanosky , Kevin William Gorman , Emory D. Keller , Michael Richard Ouellette
IPC分类号： G01F15/06
CPC分类号： G01R31/31724 , G01R31/31721
摘要： A system that includes a controller for enabling an enumeration operation. The enumeration operation is performed by a controller (110) and logic elements (120) in a system, such that each logic element in the system assigns itself a unique identifier. Each logic element can then be controlled by another source or have a means to communicate with other logic elements in the system. The unique identifier enables greater system flexibility, thereby reducing cost and improving efficiency.
摘要翻译：一种包括用于启用枚举操作的控制器的系统。枚举操作由系统中的控制器（110）和逻辑元件（120）执行，使得系统中的每个逻辑元件分配自身唯一的标识符。然后，每个逻辑元件可以被另一个源控制，或者具有与系统中的其它逻辑元件通信的手段。独特的标识符可以实现更大的系统灵活性，从而降低成本并提高效率。

15. 发明授权

US06496432B2 Method and apparatus for testing a write function of a dual-port static memory cell 有权
公开(公告)号：US06496432B2
公开(公告)日：2002-12-17
申请号：US09733295
申请日：2000-12-08
申请人： Michael Richard Ouellette , Jeremy Paul Rowland , David Jerome Wager
发明人： Michael Richard Ouellette , Jeremy Paul Rowland , David Jerome Wager
IPC分类号： G11C2900
CPC分类号： G11C8/16 , G11C29/02
摘要： A method and apparatus for testing a write function of a dual-port static memory cell during a concurrent read/write cycle on a memory cell is disclosed. A memory cell of a dual-port static memory is read via a first port of the memory cell. After the read operation, the standard bitline restore operation that normally occurs after a read or write operation is suppressed from occurring on the bitlines for the first port. Then, the memory cell is read again via the first port at the same time the memory cell is being written via a second port with a logical data value that is opposite to the logical data value being read from the first port. After the completion of the write operation, the bitlines for the first and second ports are restored by a bitline restore operation. Finally, the logical data value in the memory cell is verified for its correctness.

16. 发明授权

US06442085B1 Self-Test pattern to detect stuck open faults 失效
标题翻译：自检模式，用于检测卡住的打开故障
公开(公告)号：US06442085B1
公开(公告)日：2002-08-27
申请号：US09677681
申请日：2000-10-02
申请人： Michael Thomas Fragano , Jeffery Howard Oppold , Michael Richard Ouellette , Jeremy Paul Rowland
发明人： Michael Thomas Fragano , Jeffery Howard Oppold , Michael Richard Ouellette , Jeremy Paul Rowland
IPC分类号： G11C700
CPC分类号： G11C29/02
摘要： A testing method and device for detecting the existence of “stuck-open”, faults within static decoder circuits of a SRAM. The device and method make use of a novel pattern that fully tests static decoders used with an SRAM integrated circuit. The test pattern is selected so as to cause a transition on each parallel FET in a decoder circuit. The test pattern simulates multiple random accesses to the SRAM by modifying the traditional sequential, unique address pattern. The invention uses a two-dimensional pattern in that it separately tests rows and column decoders. In the first part of the test the input address to the column decoders is held constant while the row decoders are cycled through two sets of N iterations where N is the number of row address bits to be decoded. During the second part of the test the input address to the row decoders is held constant while the column decoders are cycled through two sets of M iterations where M is the number of column address bits to be decoded.
摘要翻译：一种用于检测SRAM的静态解码器电路中存在“卡住开路”故障的测试方法和装置。该器件和方法利用了一种全新的模式来完全测试SRAM集成电路中使用的静态解码器。选择测试图案以便在解码器电路中的每个并联FET上产生转换。测试模式通过修改传统的顺序唯一地址模式来模拟对SRAM的多次随机访问。本发明使用二维图案，它分别测试行和列解码器。在测试的第一部分中，列解码器的输入地址保持不变，而行解码器循环通过两组N次迭代，其中N是要解码的行地址位数。在测试的第二部分期间，行解码器的输入地址保持不变，而列解码器循环通过两组M次迭代，其中M是待解码的列地址位数。

17. 发明申请

US20120230136A1 SELECTABLE REPAIR PASS MASKING 有权
标题翻译：可选修理通道掩蔽
公开(公告)号：US20120230136A1
公开(公告)日：2012-09-13
申请号：US13042881
申请日：2011-03-08
申请人： Kevin William Gorman , John Robert Goss , Michael Richard Ouellette , Troy Joseph Perry , Michael Anthony Ziegerhofer
发明人： Kevin William Gorman , John Robert Goss , Michael Richard Ouellette , Troy Joseph Perry , Michael Anthony Ziegerhofer
IPC分类号： G11C29/00
CPC分类号： G11C29/4401 , G11C29/76 , G11C29/802 , G11C2029/0401 , G11C2229/726
摘要： The present invention relates to a method and circuit for selectively repairing an embedded memory module having memory elements in an integrated circuit chip. The method comprises performing a plurality of tests on the embedded memory module under operating conditions to identify a plurality of non-operational memory elements in the embedded memory module and, in response to identifying the non-operational memory elements, generating a plurality of corresponding repair solutions. The method further comprises storing the plurality of corresponding repair solutions in a non-volatile storage element and determining from a mask a subset of the plurality of repair solutions that should be restored.
摘要翻译：本发明涉及一种用于选择性地修复在集成电路芯片中具有存储元件的嵌入式存储器模块的方法和电路。该方法包括在操作条件下对嵌入式存储器模块执行多个测试以识别嵌入式存储器模块中的多个非操作存储器元件，并且响应于识别非操作存储器元件，生成多个相应的修复解决方案该方法还包括将多个对应的修复解决方案存储在非易失性存储元件中，并从掩模确定应该被恢复的多个修复解决方案的子集。

18. 发明授权

US07930592B2 Enabling memory redundancy during testing 有权
标题翻译：在测试期间启用内存冗余
公开(公告)号：US07930592B2
公开(公告)日：2011-04-19
申请号：US11829187
申请日：2007-07-27
申请人： Michael Richard Ouellette , Jeremy Rowland
发明人： Michael Richard Ouellette , Jeremy Rowland
IPC分类号： G06F11/00
CPC分类号： G11C29/14 , G11C29/24 , G11C29/44 , G11C29/4401
摘要： A design structure embodied in a machine readable medium for designing, manufacturing, testing and/or enabling a redundant memory element (20) during testing of a memory array (14), and a method of repairing a memory array.
摘要翻译：体现在用于在存储器阵列（14）的测试期间设计，制造，测试和/或启用冗余存储器元件（20）的机器可读介质中的设计结构以及修复存储器阵列的方法。

19. 发明授权

US07895028B2 Structure for increasing fuse programming yield 有权
标题翻译：提高保险丝编程产量的结构
公开(公告)号：US07895028B2
公开(公告)日：2011-02-22
申请号：US11775531
申请日：2007-07-10
申请人： Darren Lane Anand , Michael Richard Ouellette , Michael Anthony Ziegerhofer
发明人： Darren Lane Anand , Michael Richard Ouellette , Michael Anthony Ziegerhofer
IPC分类号： G06F17/50
CPC分类号： G11C29/44 , G11C17/165 , G11C29/027 , G11C29/802
摘要： A design structure which enables e-fuse memory repair. The design structure uses a compressed bit string to generate another bit string based on a select value. The select value provides instructions to an encoding logic element, which generates a second bit string. For example, the select value may instruct the encoding logic to create a duplicate copy of each bit in the compressed bit string to generate a 2n-bit string. Once the fuses are programmed using the second bit string, the fuse values are read out as a third string, which is decoded by a decoding logic element according to the select value, thereby improving memory repair.
摘要翻译：一种能够进行电子保险丝内存修复的设计结构。设计结构使用压缩比特串根据选择值生成另一个比特串。该选择值向编码逻辑元件提供指令，该编码逻辑元件产生第二位串。例如，选择值可以指示编码逻辑在压缩比特串中创建每个比特的重复副本以生成2n比特串。一旦使用第二位串编程熔丝，则将熔丝值作为第三串读出，其由解码逻辑元件根据选择值解码，从而改善存储器修复。

20. 发明授权

US07721119B2 System and method to optimize multi-core microprocessor performance using voltage offsets 失效
标题翻译：使用电压补偿优化多核微处理器性能的系统和方法
公开(公告)号：US07721119B2
公开(公告)日：2010-05-18
申请号：US11466891
申请日：2006-08-24
申请人： Louis Bennie Capps, Jr. , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
发明人： Louis Bennie Capps, Jr. , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.
摘要翻译：提出了使用电压偏移来优化多核微处理器性能的系统和方法。多核设备测试每个处理器内核，以便识别每个处理器内核的最佳电源电压。反过来，该设备基于每个处理器核心的所识别的最佳电源电压来配置每个处理器核心的电压偏移网络。结果，从多核设备的主电压中减去由电压偏移网络产生的偏移电压，这导致电压偏移网络向每个处理器核提供最佳电源电压。电压偏移网络可以包括熔丝以产生固定的电压偏移，或者电压偏移网络可以包括在多核装置的操作期间动态地调节电压偏移的控制电路。

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