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11. 发明授权

US08877569B2 Method of manufacturing thin film transistor with oxide semiconductor using sputtering method 有权
标题翻译：使用溅射法制造具有氧化物半导体的薄膜晶体管的方法
公开(公告)号：US08877569B2
公开(公告)日：2014-11-04
申请号：US13455425
申请日：2012-04-25
申请人： Yoshiaki Oikawa , Hotaka Maruyama , Hiromichi Godo , Daisuke Kawae , Shunpei Yamazaki
发明人： Yoshiaki Oikawa , Hotaka Maruyama , Hiromichi Godo , Daisuke Kawae , Shunpei Yamazaki
IPC分类号： H01L21/00 , H01L21/44 , H01L29/786 , H01L27/12 , H01L21/02
CPC分类号： H01L27/1225 , G02F1/1368 , G02F2201/121 , G02F2201/123 , H01L21/02565 , H01L21/02631 , H01L27/1214 , H01L27/124 , H01L27/156 , H01L27/3248 , H01L27/3262 , H01L29/24 , H01L29/78618 , H01L29/7869 , H01L29/78693 , H01L29/78696
摘要： An object is to provide a semiconductor device provided with a thin film transistor having excellent electric characteristics using an oxide semiconductor layer. An In—Sn—O-based oxide semiconductor layer including SiOX is used for a channel formation region. In order to reduce contact resistance between the In—Sn—O-based oxide semiconductor layer including SiOX and a wiring layer formed from a metal material having low electric resistance, a source region or drain region is formed between a source electrode layer or drain electrode layer and the In—Sn—O-based oxide semiconductor layer including SiOX. The source region or drain region and a pixel region are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX.
摘要翻译：本发明的目的是提供一种具有使用氧化物半导体层的具有优异电特性的薄膜晶体管的半导体器件。包括SiOX的In-Sn-O系氧化物半导体层用于沟道形成区域。为了降低包含SiOX的In-Sn-O系氧化物半导体层与由电阻低的金属材料形成的布线层之间的接触电阻，在源电极层或漏电极之间形成源极区或漏极区层和包含SiOX的In-Sn-O系氧化物半导体层。使用不包含SiOX的In-Sn-O系氧化物半导体层来形成源极区域或漏极区域以及像素区域。

12. 发明授权

US08748880B2 Semiconductor device with oxide semiconductor 有权
标题翻译：具有氧化物半导体的半导体器件
公开(公告)号：US08748880B2
公开(公告)日：2014-06-10
申请号：US12949949
申请日：2010-11-19
申请人： Shunpei Yamazaki , Daisuke Kawae
发明人： Shunpei Yamazaki , Daisuke Kawae
IPC分类号： H01L29/10 , H01L29/786
CPC分类号： H01L29/7869 , H01L27/1225 , H01L29/42392 , H01L29/78606 , H01L29/78642 , H01L29/78696
摘要： Provided is a semiconductor device for high power application including a novel semiconductor material with high productivity. Alternatively, provided is a semiconductor device having a novel structure in which the novel semiconductor material is used. Provided is a vertical transistor including a channel formation region formed using an oxide semiconductor which has a wider band gap than a silicon semiconductor and is an intrinsic semiconductor or a substantially intrinsic semiconductor with impurities that can serve as electron donors (donors) in the oxide semiconductor removed. The thickness of the oxide semiconductor is greater than or equal to 1 μm, preferably greater than 3 μm, more preferably greater than or equal to 10 μm, and end portions of one of electrodes that are in contact with the oxide semiconductor is placed inside end portions of the oxide semiconductor.
摘要翻译：提供了一种用于高功率应用的半导体器件，包括具有高生产率的新型半导体材料。或者，提供了具有其中使用新型半导体材料的新颖结构的半导体器件。提供了一种垂直晶体管，其包括使用具有比硅半导体更宽的带隙的氧化物半导体形成的沟道形成区，并且是本征半导体或具有可用作氧化物半导体中的电子给体（供体）的杂质的本质半导体删除。氧化物半导体的厚度大于或等于1μm，优选大于3μm，更优选大于或等于10μm，并且与氧化物半导体接触的电极中的一个端部位于内侧部分氧化物半导体。

13. 发明授权

US08664652B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08664652B2
公开(公告)日：2014-03-04
申请号：US12974099
申请日：2010-12-21
申请人： Shunpei Yamazaki , Hiromichi Godo , Daisuke Kawae
发明人： Shunpei Yamazaki , Hiromichi Godo , Daisuke Kawae
IPC分类号： H01L29/786 , H01L29/12
CPC分类号： H01L29/7869 , H01L29/1033 , H01L29/42384 , H01L29/4908 , H01L29/66477 , H01L29/78696
摘要： A semiconductor device which includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer is provided. The thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 10 nm. The gate insulating layer satisfies a relation where ∈r/d is greater than or equal to 0.08 (nm−1) and less than or equal to 7.9 (nm−1) when the relative permittivity of a material used for the gate insulating layer is ∈r and the thickness of the gate insulating layer is d. The distance between the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 1 μm.
摘要翻译：一种半导体器件，包括氧化物半导体层，与氧化物半导体层电连接的源电极和漏电极，覆盖氧化物半导体层的栅绝缘层，源电极和漏电极以及栅电极提供栅极绝缘层。氧化物半导体层的厚度大于或等于1nm且小于或等于10nm。当栅极绝缘层使用的材料的相对介电常数为Er时，栅极绝缘层满足Er / d大于等于0.08（nm-1）且小于等于7.9（nm-1）的关系栅极绝缘层的厚度为d。源电极和漏电极之间的距离大于或等于10nm且小于或等于1μm。

14. 发明授权

US08415667B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08415667B2
公开(公告)日：2013-04-09
申请号：US12957434
申请日：2010-12-01
申请人： Shunpei Yamazaki , Daisuke Kawae , Hiromichi Godo
发明人： Shunpei Yamazaki , Daisuke Kawae , Hiromichi Godo
IPC分类号： H01L29/04 , H01L31/036 , H01L31/0376 , H01L31/20
CPC分类号： H01L29/45 , H01L27/1225 , H01L29/7869
摘要： One object is to provide a p-channel transistor including an oxide semiconductor. Another object is to provide a complementary metal oxide semiconductor (CMOS) structure of an n-channel transistor including an oxide semiconductor and a p-channel transistor including an oxide semiconductor. A p-channel transistor including an oxide semiconductor includes a gate electrode layer, a gate insulating layer, an oxide semiconductor layer, and a source and drain electrode layers in contact with the oxide semiconductor layer. When the electron affinity and the band gap of an oxide semiconductor used for the oxide semiconductor layer in the semiconductor device, respectively, are χ (eV) and Eg (eV), the work function (φm) of the conductor used for the source electrode layer and the drain electrode layer satisfies φm>χ+Eg/2 and the barrier for holes (φBp) represented by (χ+Eg−φm) is less than 0.25 eV.
摘要翻译：一个目的是提供一种包括氧化物半导体的p沟道晶体管。另一个目的是提供包括氧化物半导体的n沟道晶体管和包括氧化物半导体的p沟道晶体管的互补金属氧化物半导体（CMOS）结构。包括氧化物半导体的p沟道晶体管包括与氧化物半导体层接触的栅极电极层，栅极绝缘层，氧化物半导体层以及源极和漏极电极层。当半导体器件中用于氧化物半导体层的氧化物半导体的电子亲和力和带隙分别为χ（eV）和Eg（eV）时，用于所述半导体器件的导体的功函数（＆phgr; m）源电极层和漏电极层满足＆lt; m +χ+ Eg / 2，并且由（χ+ Eg-＆phgr; m）表示的空穴屏障（＆phgr; Bp）小于0.25eV。

15. 发明授权

US08373164B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08373164B2
公开(公告)日：2013-02-12
申请号：US12613769
申请日：2009-11-06
申请人： Shunpei Yamazaki , Kengo Akimoto , Daisuke Kawae
发明人： Shunpei Yamazaki , Kengo Akimoto , Daisuke Kawae
IPC分类号： H01L29/04 , H01L29/10 , H01L31/00 , H01L21/00
CPC分类号： H01L29/41733 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L27/1225 , H01L27/1288 , H01L29/4908 , H01L29/786 , H01L29/78618 , H01L29/7869 , H01L29/78696 , H01L51/0508 , H01L51/0512 , H01L51/0545 , H01L51/105
摘要： A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.
摘要翻译：下栅极薄膜晶体管中的源电极和漏电极之间可能发生的电场浓度被放宽并且抑制了开关特性的劣化的结构及其制造方法。制造在源电极和漏电极上设置氧化物半导体层的底栅薄膜晶体管，与氧化物半导体层接触的源电极的侧表面的角度和角度;角度和角度; 与氧化物半导体层接触的漏电极的侧面的两个面积分别被设定为大于或等于20°且小于90°，使得从上边缘到下边缘的距离每个电极的侧表面增加。

16. 发明申请

US20110121288A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110121288A1
公开(公告)日：2011-05-26
申请号：US12949949
申请日：2010-11-19
申请人： Shunpei Yamazaki , Daisuke Kawae
发明人： Shunpei Yamazaki , Daisuke Kawae
IPC分类号： H01L29/78
CPC分类号： H01L29/7869 , H01L27/1225 , H01L29/42392 , H01L29/78606 , H01L29/78642 , H01L29/78696
摘要： Provided is a semiconductor device for high power application including a novel semiconductor material with high productivity. Alternatively, provided is a semiconductor device having a novel structure in which the novel semiconductor material is used. Provided is a vertical transistor including a channel formation region formed using an oxide semiconductor which has a wider band gap than a silicon semiconductor and is an intrinsic semiconductor or a substantially intrinsic semiconductor with impurities that can serve as electron donors (donors) in the oxide semiconductor removed. The thickness of the oxide semiconductor is greater than or equal to 1 μm, preferably greater than 3 μm, more preferably greater than or equal to 10 μm, and end portions of one of electrodes that are in contact with the oxide semiconductor is placed inside end portions of the oxide semiconductor.
摘要翻译：提供了一种用于高功率应用的半导体器件，包括具有高生产率的新型半导体材料。或者，提供了具有其中使用新型半导体材料的新颖结构的半导体器件。提供了一种垂直晶体管，其包括使用具有比硅半导体更宽的带隙的氧化物半导体形成的沟道形成区，并且是本征半导体或具有可用作氧化物半导体中的电子给体（供体）的杂质的本质半导体删除。氧化物半导体的厚度大于或等于1μm，优选大于3μm，更优选大于或等于10μm，并且与氧化物半导体接触的电极中的一个端部位于内侧部分氧化物半导体。

17. 发明授权

US07812348B2 Thin-film transistor and display device 有权
标题翻译：薄膜晶体管和显示器件
公开(公告)号：US07812348B2
公开(公告)日：2010-10-12
申请号：US12390954
申请日：2009-02-23
申请人： Koji Dairiki , Hidekazu Miyairi , Yoshiyuki Kurokawa , Shunpei Yamazaki , Hiromichi Godo , Daisuke Kawae , Satoshi Kobayashi
发明人： Koji Dairiki , Hidekazu Miyairi , Yoshiyuki Kurokawa , Shunpei Yamazaki , Hiromichi Godo , Daisuke Kawae , Satoshi Kobayashi
IPC分类号： H01L27/14
CPC分类号： H01L29/78609 , H01L29/04 , H01L29/41733 , H01L29/4908 , H01L29/66765 , H01L29/78618 , H01L29/78669
摘要： A thin-film transistor in which problems with ON-state current and OFF-state current are solved, and a thin-film transistor capable of high-speed operation. The thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions, provided with a space therebetween so as to be overlapped with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of semiconductor layers in which an impurity element which serves as an acceptor is added, overlapped over the gate insulating layers with the gate electrode and the impurity semiconductor layers, and disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer being in contact with the gate insulating layer and the pair of semiconductor layers and extended between the pair of semiconductor layers.
摘要翻译：解决了导通状态电流和截止电流的问题的薄膜晶体管，以及能够进行高速运转的薄膜晶体管。薄膜晶体管包括一对杂质半导体层，其中添加赋予一种导电类型的杂质元素以形成源极和漏极区域，其间具有间隔，以便与具有栅极绝缘层的栅电极重叠插入在栅电极和杂质半导体层之间; 添加作为受体的杂质元素的一对半导体层，与栅极电极和杂质半导体层重叠在栅极绝缘层上，并且在沟道长度方向上间隔设置; 以及与所述栅绝缘层和所述一对半导体层接触并在所述一对半导体层之间延伸的非晶半导体层。

18. 发明授权

US08637861B2 Transistor having oxide semiconductor with electrode facing its side surface 有权
标题翻译：具有氧化物半导体的晶体管，其电极面向其侧表面
公开(公告)号：US08637861B2
公开(公告)日：2014-01-28
申请号：US12948969
申请日：2010-11-18
申请人： Shunpei Yamazaki , Daisuke Kawae
发明人： Shunpei Yamazaki , Daisuke Kawae
IPC分类号： H01L29/10 , H01L29/12 , H01L21/00 , H01L21/16
CPC分类号： H01L29/7869 , H01L27/1225 , H01L29/42392 , H01L29/78606 , H01L29/78642 , H01L29/78696
摘要： Provided is a semiconductor device for high power application including a novel semiconductor material with high productivity. Alternatively, provided is a semiconductor device having a novel structure in which the novel semiconductor material is used. Provided is a vertical transistor including a channel formation region formed using an oxide semiconductor which has a wider band gap than a silicon semiconductor and is an intrinsic semiconductor or a substantially intrinsic semiconductor with impurities that serve as electron donors (donors) in the oxide semiconductor removed. The thickness of the oxide semiconductor is greater than or equal to 1 micrometer, preferably greater than 3 micrometer, more preferably greater than or equal to 10 micrometer.
摘要翻译：提供了一种用于高功率应用的半导体器件，包括具有高生产率的新型半导体材料。或者，提供了具有其中使用新型半导体材料的新颖结构的半导体器件。提供了一种垂直晶体管，其包括使用具有比硅半导体更宽的带隙的氧化物半导体形成的沟道形成区，并且是具有杂质的本征半导体或具有用作氧化物半导体中的电子供体（供体）的本质半导体，其被去除。氧化物半导体的厚度大于或等于1微米，优选大于3微米，更优选大于或等于10微米。

19. 发明授权

US08183102B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08183102B2
公开(公告)日：2012-05-22
申请号：US12243085
申请日：2008-10-01
申请人： Shunpei Yamazaki , Yoshiyuki Kurokawa , Daisuke Kawae , Satoshi Kobayashi
发明人： Shunpei Yamazaki , Yoshiyuki Kurokawa , Daisuke Kawae , Satoshi Kobayashi
IPC分类号： H01L29/04
CPC分类号： H01L29/4908 , H01L29/04 , H01L29/41733 , H01L29/66765 , H01L29/78696
摘要： To improve field effect mobility of an inverted-staggered TFT using amorphous silicon. In an inverted-staggered TFT, a thin amorphous semiconductor layer which is made to have n-type conductivity is formed between a gate insulating film and an amorphous semiconductor layer. By depositing an amorphous semiconductor layer after a substrate over which up to a gate insulating film is formed is exposed to an atmosphere which contains a phosphine gas in a small amount, an amorphous semiconductor layer which contains phosphorus is formed during the early stage of deposition of the amorphous semiconductor layer. The thus obtained amorphous semiconductor layer has the concentration peak of phosphorus around the surface of the gate insulating film.
摘要翻译：为了提高使用非晶硅的反交错TFT的场效应迁移率。在反交错TFT中，在栅极绝缘膜和非晶半导体层之间形成具有n型导电性的薄的非晶半导体层。通过在其上形成至多栅极绝缘膜的基板之后沉积非晶半导体层，暴露于含有少量磷化氢气体的气氛中，在沉积的早期阶段形成含有磷的非晶半导体层非晶半导体层。由此获得的非晶半导体层具有围绕栅极绝缘膜的表面的磷的浓度峰值。

20. 发明授权

US07968885B2 Display device and manufacturing method thereof 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US07968885B2
公开(公告)日：2011-06-28
申请号：US12222256
申请日：2008-08-06
申请人： Satoshi Kobayashi , Yoshiyuki Kurokawa , Shunpei Yamazaki , Daisuke Kawae
发明人： Satoshi Kobayashi , Yoshiyuki Kurokawa , Shunpei Yamazaki , Daisuke Kawae
IPC分类号： H01L21/00 , H01L27/108 , H01L29/00 , H01L31/036 , H01L31/112
CPC分类号： H01L29/41733 , H01L29/04 , H01L29/66765 , H01L29/78696
摘要： To provide a display device having a thin film transistor with high electric characteristics and excellent reliability and a manufacturing method thereof. A gate electrode, a gate insulating film provided over the gate electrode, a first semiconductor layer provided over the gate insulating film and having a microcrystalline semiconductor, a second semiconductor layer provided over the first semiconductor layer and having an amorphous semiconductor, and a source region and a drain region provided over the second semiconductor layer are provided. The first semiconductor layer has high crystallinity than the second semiconductor layer. The second semiconductor layer includes an impurity region having a conductivity type different from a conductivity type of the source region and the drain region between the source region and the drain region.
摘要翻译：提供具有高电特性和优异可靠性的薄膜晶体管的显示装置及其制造方法。栅电极，设置在栅电极上的栅极绝缘膜，设置在栅绝缘膜上并具有微晶半导体的第一半导体层，设置在第一半导体层上并具有非晶半导体的第二半导体层，以及源极区并且设置在第二半导体层上的漏极区。第一半导体层具有比第二半导体层高的结晶度。第二半导体层包括具有不同于源极区域的导电类型和源极区域与漏极区域之间的漏极区域的导电类型的杂质区域。

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