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1. 发明授权

US08373203B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08373203B2
公开(公告)日：2013-02-12
申请号：US12954222
申请日：2010-11-24
申请人： Shunpei Yamazaki , Hiromichi Godo , Daisuke Kawae
发明人： Shunpei Yamazaki , Hiromichi Godo , Daisuke Kawae
IPC分类号： H01L27/148
CPC分类号： H01L29/78693 , H01L29/41733 , H01L29/42384 , H01L29/4908 , H01L29/66969 , H01L29/7869 , H01L29/78696
摘要： An intrinsic or substantially intrinsic semiconductor, which has been subjected to a step of dehydration or dehydrogenation and a step of adding oxygen so that the carrier concentration is less than 1×1012/cm3 is used for an oxide semiconductor layer of an insulated gate transistor, in which a channel region is formed. The length of the channel formed in the oxide semiconductor layer is set to 0.2 μm to 3.0 μm an inclusive and the thicknesses of the oxide semiconductor layer and the gate insulating layer are set to 15 nm to 30 nm inclusive and 20 nm to 50 nm inclusive, respectively, or 15 nm to 100 nm inclusive and 10 nm to 20 nm inclusive, respectively. Consequently, a short-channel effect can be suppressed, and the amount of change in threshold voltage can be less than 0.5 V in the range of the above channel lengths.
摘要翻译：对于绝缘栅极晶体管的氧化物半导体层，使用已进行脱水或脱氢工序的本征或本质上本征的半导体，以及添加氧以使载流子浓度小于1×10 12 / cm 3的步骤，其中形成沟道区。将形成在氧化物半导体层中的沟道的长度设定为0.2μm〜3.0μm，氧化物半导体层和栅极绝缘层的厚度为15nm〜30nm，包括20nm〜50nm ，或分别为15nm〜100nm，10nm〜20nm。因此，可以抑制短沟道效应，并且在上述通道长度的范围内阈值电压的变化量可以小于0.5V。

2. 发明授权

US08174021B2 Semiconductor device and method of manufacturing the semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08174021B2
公开(公告)日：2012-05-08
申请号：US12695179
申请日：2010-01-28
申请人： Yoshiaki Oikawa , Hotaka Maruyama , Hiromichi Godo , Daisuke Kawae , Shunpei Yamazaki
发明人： Yoshiaki Oikawa , Hotaka Maruyama , Hiromichi Godo , Daisuke Kawae , Shunpei Yamazaki
IPC分类号： H01L27/14
CPC分类号： H01L27/1225 , G02F1/1368 , G02F2201/121 , G02F2201/123 , H01L21/02565 , H01L21/02631 , H01L27/1214 , H01L27/124 , H01L27/156 , H01L27/3248 , H01L27/3262 , H01L29/24 , H01L29/78618 , H01L29/7869 , H01L29/78693 , H01L29/78696
摘要： An object is to provide a semiconductor device provided with a thin film transistor having excellent electric characteristics using an oxide semiconductor layer. An In—Sn—O-based oxide semiconductor layer including SiOX is used for a channel formation region. In order to reduce contact resistance between the In—Sn—O-based oxide semiconductor layer including SiOX and a wiring layer formed from a metal material having low electric resistance, a source region or drain region is formed between a source electrode layer or drain electrode layer and the In—Sn—O-based oxide semiconductor layer including SiOX. The source region or drain region and a pixel region are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX.
摘要翻译：本发明的目的是提供一种具有使用氧化物半导体层的具有优异电特性的薄膜晶体管的半导体器件。包括SiOX的In-Sn-O系氧化物半导体层用于沟道形成区域。为了降低包含SiOX的In-Sn-O系氧化物半导体层与由电阻低的金属材料形成的布线层之间的接触电阻，在源电极层或漏极之间形成源极区或漏极区层和包含SiOX的In-Sn-O系氧化物半导体层。使用不包含SiOX的In-Sn-O系氧化物半导体层来形成源极区域或漏极区域以及像素区域。

3. 发明授权

US07786485B2 Thin-film transistor and display device 有权
标题翻译：薄膜晶体管和显示器件
公开(公告)号：US07786485B2
公开(公告)日：2010-08-31
申请号：US12390144
申请日：2009-02-20
申请人： Koji Dairiki , Hidekazu Miyairi , Yoshiyuki Kurokawa , Shunpei Yamazaki , Hiromichi Godo , Daisuke Kawae , Satoshi Kobayashi
发明人： Koji Dairiki , Hidekazu Miyairi , Yoshiyuki Kurokawa , Shunpei Yamazaki , Hiromichi Godo , Daisuke Kawae , Satoshi Kobayashi
IPC分类号： H01L27/14 , H01L29/04 , H01L29/15
CPC分类号： H01L27/1214 , H01L27/1288 , H01L29/04 , H01L29/458 , H01L29/4908 , H01L29/66765
摘要： A thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions so as to be overlapped at least partly with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of conductive layers which is overlapped over the gate insulating layers at least partly with the gate electrode and the impurity semiconductor layers, and is disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer which is in contact with the gate insulating layer and the pair of conductive layers and is extended between the pair of conductive layers.
摘要翻译：薄膜晶体管包括一对杂质半导体层，其中添加赋予一种导电类型的杂质元素以形成源极区和漏极区，以至少部分地与栅电极重叠，栅极绝缘层介于栅电极和杂质半导体层; 一对导电层，其至少部分地与所述栅电极和所述杂质半导体层重叠在所述栅极绝缘层上方，并且在沟道长度方向上设置有间隔; 以及与所述栅极绝缘层和所述一对导电层接触并在所述一对导电层之间延伸的非晶半导体层。

4. 发明申请

US20110127525A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110127525A1
公开(公告)日：2011-06-02
申请号：US12954222
申请日：2010-11-24
申请人： Shunpei Yamazaki , Hiromichi Godo , Daisuke Kawae
发明人： Shunpei Yamazaki , Hiromichi Godo , Daisuke Kawae
IPC分类号： H01L29/786
CPC分类号： H01L29/78693 , H01L29/41733 , H01L29/42384 , H01L29/4908 , H01L29/66969 , H01L29/7869 , H01L29/78696
摘要： An intrinsic or substantially intrinsic semiconductor, which has been subjected to a step of dehydration or dehydrogenation and a step of adding oxygen so that the carrier concentration is less than 1×1012/cm3 is used for an oxide semiconductor layer of an insulated gate transistor, in which a channel region is formed. The length of the channel formed in the oxide semiconductor layer is set to 0.2 μm to 3.0 μm an inclusive and the thicknesses of the oxide semiconductor layer and the gate insulating layer are set to 15 nm to 30 nm inclusive and 20 nm to 50 nm inclusive, respectively, or 15 nm to 100 nm inclusive and 10 nm to 20 nm inclusive, respectively. Consequently, a short-channel effect can be suppressed, and the amount of change in threshold voltage can be less than 0.5 V in the range of the above channel lengths.
摘要翻译：对于绝缘栅极晶体管的氧化物半导体层，使用已进行脱水或脱氢工序的本征或本质上本征的半导体，以及添加氧以使载流子浓度小于1×10 12 / cm 3的步骤，其中形成沟道区。将形成在氧化物半导体层中的沟道的长度设定为0.2μm〜3.0μm，氧化物半导体层和栅极绝缘层的厚度为15nm〜30nm，包括20nm〜50nm ，或分别为15nm〜100nm，10nm〜20nm。因此，可以抑制短沟道效应，并且在上述通道长度的范围内阈值电压的变化量可以小于0.5V。

5. 发明授权

US08877569B2 Method of manufacturing thin film transistor with oxide semiconductor using sputtering method 有权
标题翻译：使用溅射法制造具有氧化物半导体的薄膜晶体管的方法
公开(公告)号：US08877569B2
公开(公告)日：2014-11-04
申请号：US13455425
申请日：2012-04-25
申请人： Yoshiaki Oikawa , Hotaka Maruyama , Hiromichi Godo , Daisuke Kawae , Shunpei Yamazaki
发明人： Yoshiaki Oikawa , Hotaka Maruyama , Hiromichi Godo , Daisuke Kawae , Shunpei Yamazaki
IPC分类号： H01L21/00 , H01L21/44 , H01L29/786 , H01L27/12 , H01L21/02
CPC分类号： H01L27/1225 , G02F1/1368 , G02F2201/121 , G02F2201/123 , H01L21/02565 , H01L21/02631 , H01L27/1214 , H01L27/124 , H01L27/156 , H01L27/3248 , H01L27/3262 , H01L29/24 , H01L29/78618 , H01L29/7869 , H01L29/78693 , H01L29/78696
摘要： An object is to provide a semiconductor device provided with a thin film transistor having excellent electric characteristics using an oxide semiconductor layer. An In—Sn—O-based oxide semiconductor layer including SiOX is used for a channel formation region. In order to reduce contact resistance between the In—Sn—O-based oxide semiconductor layer including SiOX and a wiring layer formed from a metal material having low electric resistance, a source region or drain region is formed between a source electrode layer or drain electrode layer and the In—Sn—O-based oxide semiconductor layer including SiOX. The source region or drain region and a pixel region are formed using an In—Sn—O-based oxide semiconductor layer which does not include SiOX.
摘要翻译：本发明的目的是提供一种具有使用氧化物半导体层的具有优异电特性的薄膜晶体管的半导体器件。包括SiOX的In-Sn-O系氧化物半导体层用于沟道形成区域。为了降低包含SiOX的In-Sn-O系氧化物半导体层与由电阻低的金属材料形成的布线层之间的接触电阻，在源电极层或漏电极之间形成源极区或漏极区层和包含SiOX的In-Sn-O系氧化物半导体层。使用不包含SiOX的In-Sn-O系氧化物半导体层来形成源极区域或漏极区域以及像素区域。

6. 发明授权

US08664652B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08664652B2
公开(公告)日：2014-03-04
申请号：US12974099
申请日：2010-12-21
申请人： Shunpei Yamazaki , Hiromichi Godo , Daisuke Kawae
发明人： Shunpei Yamazaki , Hiromichi Godo , Daisuke Kawae
IPC分类号： H01L29/786 , H01L29/12
CPC分类号： H01L29/7869 , H01L29/1033 , H01L29/42384 , H01L29/4908 , H01L29/66477 , H01L29/78696
摘要： A semiconductor device which includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer is provided. The thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 10 nm. The gate insulating layer satisfies a relation where ∈r/d is greater than or equal to 0.08 (nm−1) and less than or equal to 7.9 (nm−1) when the relative permittivity of a material used for the gate insulating layer is ∈r and the thickness of the gate insulating layer is d. The distance between the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 1 μm.
摘要翻译：一种半导体器件，包括氧化物半导体层，与氧化物半导体层电连接的源电极和漏电极，覆盖氧化物半导体层的栅绝缘层，源电极和漏电极以及栅电极提供栅极绝缘层。氧化物半导体层的厚度大于或等于1nm且小于或等于10nm。当栅极绝缘层使用的材料的相对介电常数为Er时，栅极绝缘层满足Er / d大于等于0.08（nm-1）且小于等于7.9（nm-1）的关系栅极绝缘层的厚度为d。源电极和漏电极之间的距离大于或等于10nm且小于或等于1μm。

7. 发明授权

US08415667B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08415667B2
公开(公告)日：2013-04-09
申请号：US12957434
申请日：2010-12-01
申请人： Shunpei Yamazaki , Daisuke Kawae , Hiromichi Godo
发明人： Shunpei Yamazaki , Daisuke Kawae , Hiromichi Godo
IPC分类号： H01L29/04 , H01L31/036 , H01L31/0376 , H01L31/20
CPC分类号： H01L29/45 , H01L27/1225 , H01L29/7869
摘要： One object is to provide a p-channel transistor including an oxide semiconductor. Another object is to provide a complementary metal oxide semiconductor (CMOS) structure of an n-channel transistor including an oxide semiconductor and a p-channel transistor including an oxide semiconductor. A p-channel transistor including an oxide semiconductor includes a gate electrode layer, a gate insulating layer, an oxide semiconductor layer, and a source and drain electrode layers in contact with the oxide semiconductor layer. When the electron affinity and the band gap of an oxide semiconductor used for the oxide semiconductor layer in the semiconductor device, respectively, are χ (eV) and Eg (eV), the work function (φm) of the conductor used for the source electrode layer and the drain electrode layer satisfies φm>χ+Eg/2 and the barrier for holes (φBp) represented by (χ+Eg−φm) is less than 0.25 eV.
摘要翻译：一个目的是提供一种包括氧化物半导体的p沟道晶体管。另一个目的是提供包括氧化物半导体的n沟道晶体管和包括氧化物半导体的p沟道晶体管的互补金属氧化物半导体（CMOS）结构。包括氧化物半导体的p沟道晶体管包括与氧化物半导体层接触的栅极电极层，栅极绝缘层，氧化物半导体层以及源极和漏极电极层。当半导体器件中用于氧化物半导体层的氧化物半导体的电子亲和力和带隙分别为χ（eV）和Eg（eV）时，用于所述半导体器件的导体的功函数（＆phgr; m）源电极层和漏电极层满足＆lt; m +χ+ Eg / 2，并且由（χ+ Eg-＆phgr; m）表示的空穴屏障（＆phgr; Bp）小于0.25eV。

8. 发明授权

US07812348B2 Thin-film transistor and display device 有权
标题翻译：薄膜晶体管和显示器件
公开(公告)号：US07812348B2
公开(公告)日：2010-10-12
申请号：US12390954
申请日：2009-02-23
申请人： Koji Dairiki , Hidekazu Miyairi , Yoshiyuki Kurokawa , Shunpei Yamazaki , Hiromichi Godo , Daisuke Kawae , Satoshi Kobayashi
发明人： Koji Dairiki , Hidekazu Miyairi , Yoshiyuki Kurokawa , Shunpei Yamazaki , Hiromichi Godo , Daisuke Kawae , Satoshi Kobayashi
IPC分类号： H01L27/14
CPC分类号： H01L29/78609 , H01L29/04 , H01L29/41733 , H01L29/4908 , H01L29/66765 , H01L29/78618 , H01L29/78669
摘要： A thin-film transistor in which problems with ON-state current and OFF-state current are solved, and a thin-film transistor capable of high-speed operation. The thin-film transistor includes a pair of impurity semiconductor layers in which an impurity element imparting one conductivity type is added to form a source and drain regions, provided with a space therebetween so as to be overlapped with a gate electrode with a gate insulating layer interposed between the gate electrode and the impurity semiconductor layers; a pair of semiconductor layers in which an impurity element which serves as an acceptor is added, overlapped over the gate insulating layers with the gate electrode and the impurity semiconductor layers, and disposed with a space therebetween in a channel length direction; and an amorphous semiconductor layer being in contact with the gate insulating layer and the pair of semiconductor layers and extended between the pair of semiconductor layers.
摘要翻译：解决了导通状态电流和截止电流的问题的薄膜晶体管，以及能够进行高速运转的薄膜晶体管。薄膜晶体管包括一对杂质半导体层，其中添加赋予一种导电类型的杂质元素以形成源极和漏极区域，其间具有间隔，以便与具有栅极绝缘层的栅电极重叠插入在栅电极和杂质半导体层之间; 添加作为受体的杂质元素的一对半导体层，与栅极电极和杂质半导体层重叠在栅极绝缘层上，并且在沟道长度方向上间隔设置; 以及与所述栅绝缘层和所述一对半导体层接触并在所述一对半导体层之间延伸的非晶半导体层。

9. 发明授权

US07968880B2 Thin film transistor and display device 有权
标题翻译：薄膜晶体管和显示装置
公开(公告)号：US07968880B2
公开(公告)日：2011-06-28
申请号：US12391398
申请日：2009-02-24
申请人： Koji Dairiki , Takayuki Ikeda , Hidekazu Miyairi , Yoshiyuki Kurokawa , Hiromichi Godo , Daisuke Kawae , Takayuki Inoue , Satoshi Kobayashi
发明人： Koji Dairiki , Takayuki Ikeda , Hidekazu Miyairi , Yoshiyuki Kurokawa , Hiromichi Godo , Daisuke Kawae , Takayuki Inoue , Satoshi Kobayashi
IPC分类号： H01L29/04 , H01L31/036 , H01L31/0376 , H01L31/20
CPC分类号： H01L29/78618 , H01L29/04 , H01L29/41733 , H01L29/4908 , H01L29/66765 , H01L29/78696
摘要： To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added.
摘要翻译：为了改善薄膜晶体管的导通电流和截止电流的问题，薄膜晶体管包括一对杂质半导体层，赋予一种导电类型的杂质元素，在其间具有间隔; 在所述栅极绝缘层上与所述栅电极和添加了赋予一种导电类型的杂质元素的所述一对杂质半导体层中的一个重叠的导电层; 以及非晶半导体层，其被连续地设置在赋予一种导电类型的杂质元素的一对杂质半导体层之间，使得非晶半导体层从导电层延伸到栅极绝缘层上并且接触同时添加赋予一种导电类型的杂质元素的一对杂质半导体层。

10. 发明授权

US08618544B2 Thin film transistor and display device 有权
标题翻译：薄膜晶体管和显示装置
公开(公告)号：US08618544B2
公开(公告)日：2013-12-31
申请号：US13167762
申请日：2011-06-24
申请人： Koji Dairiki , Takayuki Ikeda , Hidekazu Miyairi , Yoshiyuki Kurokawa , Hiromichi Godo , Daisuke Kawae , Takayuki Inoue , Satoshi Kobayashi
发明人： Koji Dairiki , Takayuki Ikeda , Hidekazu Miyairi , Yoshiyuki Kurokawa , Hiromichi Godo , Daisuke Kawae , Takayuki Inoue , Satoshi Kobayashi
IPC分类号： H01L29/04 , H01L31/036 , H01L31/0376 , H01L31/20
CPC分类号： H01L29/78618 , H01L29/04 , H01L29/41733 , H01L29/4908 , H01L29/66765 , H01L29/78696
摘要： To improve problems with on-state current and off-state current of thin film transistors, a thin film transistor includes a pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added, provided with a space therebetween; a conductive layer which is overlapped, over the gate insulating layer, with the gate electrode and one of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added; and an amorphous semiconductor layer which is provided successively between the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added in such a manner that the amorphous semiconductor layer extends over the gate insulating layer from the conductive layer and is in contact with both of the pair of impurity semiconductor layers to which an impurity element imparting one conductivity type is added.
摘要翻译：为了改善薄膜晶体管的导通电流和截止电流的问题，薄膜晶体管包括一对杂质半导体层，赋予一种导电类型的杂质元素，在其间具有间隔; 在所述栅极绝缘层上与所述栅电极和添加了赋予一种导电类型的杂质元素的所述一对杂质半导体层中的一个重叠的导电层; 以及非晶半导体层，其被连续地设置在赋予一种导电类型的杂质元素的一对杂质半导体层之间，使得非晶半导体层从导电层延伸到栅极绝缘层上并且接触同时添加赋予一种导电类型的杂质元素的一对杂质半导体层。

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