专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US6104642A Method and apparatus for 1 of 4 register file design 有权
标题翻译： 1/4寄存器文件设计方法和装置
公开(公告)号：US6104642A
公开(公告)日：2000-08-15
申请号：US207806
申请日：1998-12-09
申请人： James S. Blomgren , Terence M. Potter , Michael R. Seningen , Stephen C. Horne
发明人： James S. Blomgren , Terence M. Potter , Michael R. Seningen , Stephen C. Horne
IPC分类号： G06F1/08 , G06F5/01 , G06F7/02 , G06F7/49 , G06F7/50 , G06F7/544 , G06F17/50 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/096 , H03K19/21 , G11C7/00
CPC分类号： G06F7/5443 , G06F1/08 , G06F17/5045 , G06F5/015 , G06F7/02 , G06F7/026 , G06F7/49 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0813 , H03K19/0963 , H03K19/215 , G06F2207/3824 , G06F7/483 , G06F7/508 , G11C7/1006
摘要： The present invention is a method and apparatus for a register cell that is configured to store information. The cell includes a multiplexer that is configurable to select various inputs when the multiplexer is in various states. The multiplexer is configurable to select a first input when the multiplexer is in a first state, and to select a second input when the multiplexer is in a second state. The multiplexer is further configured to provide storage data, the first input being configured to receive data from outside the cell. An output element, such as a second multiplexer, is configured to receive a word enable. The output of the first multiplexer is delayed in a delay element, and is provided as one of the inputs to the first multiplexer.
摘要翻译：本发明是一种用于存储信息的寄存器单元的方法和装置。该单元包括多路复用器，其可配置为当多路复用器处于不同状态时选择各种输入。多路复用器可配置为当多路复用器处于第一状态时选择第一输入，并且当多路复用器处于第二状态时选择第二输入。复用器还被配置为提供存储数据，第一输入被配置为从单元外部接收数据。诸如第二多路复用器的输出元件被配置为接收字使能。第一多路复用器的输出在延迟元件中延迟，并且被提供为第一多路复用器的输入之一。

12. 发明授权

US5920097A Compact, dual-transistor integrated circuit 失效
标题翻译：紧凑型双晶体管集成电路
公开(公告)号：US5920097A
公开(公告)日：1999-07-06
申请号：US824323
申请日：1997-03-26
申请人： Stephen C. Horne
发明人： Stephen C. Horne
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/72
CPC分类号： H01L27/11 , H01L27/1104
摘要： A compact, integrated semiconductor device includes a first transistor and a second transistor. The first transistor has a gate formed by a first portion of a gate material. A second portion of the gate material provides the bulk material for a second transistor. The device can be utilized in a six-transistor SRAM cell. The two-transistor structure can include a p-channel transistor and an n-channel transistor of such a cell.
摘要翻译：紧凑的集成半导体器件包括第一晶体管和第二晶体管。第一晶体管具有由栅极材料的第一部分形成的栅极。栅极材料的第二部分提供用于第二晶体管的体材料。该器件可用于六晶体管SRAM单元。双晶体管结构可以包括这种单元的p沟道晶体管和n沟道晶体管。

13. 发明授权

US06732346B2 Generation of route rules 有权
标题翻译：生成路线规则
公开(公告)号：US06732346B2
公开(公告)日：2004-05-04
申请号：US10155042
申请日：2002-05-24
申请人： Stephen C. Horne , Gopal Vijayan , Donald W. Glowka
发明人： Stephen C. Horne , Gopal Vijayan , Donald W. Glowka
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： This invention discloses a software tool 20 that generates wire route rules between logic gates in a semiconductor device for the automated layout of the logic gates in the device. The software tool 20 includes a routing rule generation tool 22 that creates a route rule database 30 for a given semiconductor fabrication technology and circuit family of logic gates, and includes a block build tool 32 that interconnects the logic gates with routes according to the route rules generated by the routing rule generation tool 22. The routing rule generation tool 22 further includes a noise sensitivity/gate characterization tool 24 and a rule generator tool 28. The block build tool 32 further includes a gate sizing tool 34, a gate analysis tool 36, a route rule selecting tool 38, a route assigning tool 42.
摘要翻译：本发明公开了一种在半导体器件中的逻辑门之间产生线路规则的软件工具20，用于设备中的逻辑门的自动布局。软件工具20包括路由规则生成工具22，其为给定的半导体制造技术和电路逻辑门系列创建路由规则数据库30，并且包括块逻辑门建立工具32，其将逻辑门与根据路由规则的路由互连路由规则生成工具22还包括噪声敏感度/门表征工具24和规则生成器工具28.块构建工具32还包括门尺寸工具34，门分析工具36 ，路线规则选择工具38，路线分配工具42。

14. 发明授权

US06571378B1 Method and apparatus for a N-NARY logic circuit using capacitance isolation 有权
标题翻译：使用电容隔离的N-NARY逻辑电路的方法和装置
公开(公告)号：US06571378B1
公开(公告)日：2003-05-27
申请号：US09587729
申请日：2000-06-05
申请人： James S. Blomgren , Terence M. Potter , Stephen C. Horne , Michael R. Seningen , Anthony M. Petro
发明人： James S. Blomgren , Terence M. Potter , Stephen C. Horne , Michael R. Seningen , Anthony M. Petro
IPC分类号： G06F1750
CPC分类号： G11C8/00 , G06F1/08 , G06F5/015 , G06F7/02 , G06F7/026 , G06F7/483 , G06F7/49 , G06F7/508 , G06F7/5443 , G06F17/5045 , G06F2207/3824 , G11C7/1006 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0813 , H03K19/0963 , H03K19/215
摘要： A logic device with improved capacitance isolation and a design methodology that reduces parasitic capacitance is disclosed. The logic device includes a virtual ground node, a plurality of input signals that may be individual wires of one or more N-NARY signals, and two or more discharge paths. Each discharge path includes an evaluate node, one or more transistors gated by the input signals, and one or more intermediate nodes, one of which is coupled to the virtual ground node. In one embodiment, the discharge paths are perfectly isolated from each other for every combination of inputs. In another embodiment, intermediate nodes on discharge paths maybe electrically coupled to the evaluation path only at the intermediate node coupled to the virtual ground node.
摘要翻译：公开了具有改善的电容隔离的逻辑器件和减小寄生电容的设计方法。逻辑器件包括虚拟接地节点，可以是一个或多个N-NARY信号的单独线的多个输入信号以及两个或更多个放电路径。每个放电路径包括评估节点，由输入信号选通的一个或多个晶体管，以及一个或多个中间节点，其中一个中间节点耦合到虚拟接地节点。在一个实施例中，对于输入的每个组合，排出路径彼此完全隔离。在另一个实施例中，放电路径上的中间节点可以仅在耦合到虚拟接地节点的中间节点处电耦合到评估路径。

15. 发明授权

US06412085B1 Method and apparatus for a special stress mode for N-NARY logic that initializes the logic into a functionally illegal state 失效
标题翻译：用于N-NARY逻辑的特殊应力模式的方法和装置，将逻辑初始化为功能非法状态
公开(公告)号：US06412085B1
公开(公告)日：2002-06-25
申请号：US09468760
申请日：1999-12-21
申请人： Stephen C. Horne , Kenneth D. Amstutz
发明人： Stephen C. Horne , Kenneth D. Amstutz
IPC分类号： G01R3128
CPC分类号： G01R31/318577 , G01R31/318594
摘要： The present invention is a method and apparatus that initializes N-NARY logic and dynamic logic to a special stress mode. The present invention has a logic circuit that includes a shared logic tree with one or more evaluate nodes, one or more precharge devices, and an evaluate device. Coupled to the evaluate nodes is a state generation control circuit that generates a state signal. A state generation circuit receives the state signal from the state generation control circuit and initializes the evaluate nodes to a functionally illegal state that initializes the logic circuit to the special stress mode. One embodiment of the present invention initializes the evaluate nodes to a low state. When the first logic circuit in a series of logic circuits is initialized to the functionally illegal state, the present invention will initialize the succeeding logic circuits in the series as each phase in the different clock domains evaluate, which initializes the succeeding logic circuits to the special stress mode.
摘要翻译：本发明是将N-NARY逻辑和动态逻辑初始化为特殊应力模式的方法和装置。本发明具有包括具有一个或多个评估节点的共享逻辑树，一个或多个预充电装置和评估装置的逻辑电路。耦合到评估节点的是产生状态信号的状态产生控制电路。状态产生电路从状态产生控制电路接收状态信号，并将评估节点初始化为将逻辑电路初始化为特殊压力模式的功能非法状态。本发明的一个实施例将评估节点初始化为低状态。当一系列逻辑电路中的第一逻辑电路被初始化为功能非法状态时，本发明将在不同时钟域中的每个阶段评估系列中的后续逻辑电路的初始化，其将后续逻辑电路初始化为特殊压力模式。

16. 发明授权

US5892373A Distributed gated clock driver 失效
标题翻译：分布式门控时钟驱动
公开(公告)号：US5892373A
公开(公告)日：1999-04-06
申请号：US790393
申请日：1997-01-29
申请人： Raghuram S. Tupuri , Stephen C. Horne
发明人： Raghuram S. Tupuri , Stephen C. Horne
IPC分类号： H03K3/037 , H03K19/096
CPC分类号： H03K3/0375
摘要： A gated clock driver is configured to provide an enable signal and a gated clock signal at each of a plurality flip-flops. One of the p-channel transistors of the gated clock driver's NOR gate is distributed to each of the flip-flops or latches in the system. Additionally, an extra n-channel transistor is provided in the gated clock circuit to form an inverter with the nondistributed p-channel transistor. More particularly, the p-channel transistor that is driven by the system clock input is distributed to each of the flip-flops. Similarly, the enable input (at the output of the new inverter) is distributed to each of the flip-flops. Since the gated clock signal cannot be generated without the enable signal being high and the system clock being low, distributing enable and the p-channel transistor which receives the system clock as an input minimizes clock skew as compared to flip-flops with a completely shared clock gating clock.
摘要翻译：门控时钟驱动器被配置为在多个触发器中的每一个提供使能信号和门控时钟信号。门控时钟驱动器的或非门的p沟道晶体管之一被分配到系统中的每个触发器或锁存器。此外，在门控时钟电路中提供了额外的n沟道晶体管，以形成具有非分布式p沟道晶体管的反相器。更具体地，由系统时钟输入驱动的p沟道晶体管被分配到每个触发器。类似地，使能输入（在新的反相器的输出处）被分配给每个触发器。由于门控时钟信号不能在没有使能信号为高电平且系统时钟为低的情况下产生，所以与具有完全共享的触发器相比，接收系统时钟作为输入的分配使能和p沟道晶体管使时钟偏移最小化时钟门控时钟。

17. 发明授权

US5812832A Digital clock waveform generator and method for generating a clock signal 失效
标题翻译：数字时钟波形发生器和用于产生时钟信号的方法
公开(公告)号：US5812832A
公开(公告)日：1998-09-22
申请号：US011068
申请日：1993-01-29
申请人： Stephen C. Horne , Scott H. R. McMahon
发明人： Stephen C. Horne , Scott H. R. McMahon
IPC分类号： H03K5/151 , G06F1/04 , H03K5/156 , G06F1/08
CPC分类号： H03K5/1565 , G06F1/04
摘要： A digital clock waveform generator and method for generating a clock signal are provided for a microprocessor or other digital circuit to provide on chip generation of internal clock signals having the same frequency as or a higher or lower frequency than an externally applied clock signal. In one embodiment, the waveform generator includes a delay chain and a control unit that matches the propagation delay of the delay chain to the period of an input timing signal. The waveform generator provides precise control of the duty cycles of the internally generated clock signals, and allows for rapid starting and stopping of the internal clock signals for power reduction functions. The waveform generator may further provide a system clock, and may include circuitry to precisely control the phase relationships between the various clock signals. The waveform generator is easily manufactured with digital circuitry that automatically compensates for changing environmental conditions such as operating voltage and temperature.
摘要翻译：提供了一种用于产生时钟信号的数字时钟波形发生器和方法，用于微处理器或其它数字电路，以提供具有与外部施加的时钟信号相同频率或更高或更低频率的内部时钟信号的片上产生。在一个实施例中，波形发生器包括延迟链和控制单元，其将延迟链的传播延迟与输入定时信号的周期相匹配。波形发生器可精确控制内部产生的时钟信号的占空比，并允许快速启动和停止用于功耗降低功能的内部时钟信号。波形发生器还可以提供系统时钟，并且可以包括用于精确控制各种时钟信号之间的相位关系的电路。波形发生器易于制造，数字电路可自动补偿不断变化的环境条件，如工作电压和温度。

18. 发明授权

US5295259A Data cache and method for handling memory errors during copy-back 失效
标题翻译：用于在复制期间处理内存错误的数据缓存和方法
公开(公告)号：US5295259A
公开(公告)日：1994-03-15
申请号：US650681
申请日：1991-02-05
申请人： Stephen C. Horne
发明人： Stephen C. Horne
IPC分类号： G06F11/07 , G06F12/08 , G06F1/00
CPC分类号： G06F11/073 , G06F11/0724 , G06F11/0793 , G06F12/0804
摘要： Apparatus and method of a data cache which provides for the handling of errors during data copy-back from a data cache write buffer to external memory in a processing system including a processor. When data requested by the processor at an addressed storage location of the data cache is data which is valid, modified, and other than the data requested by the processor, the data is first transferred to the data cache write buffer and then written back to external memory after the requested data is fetched from a memory bus. If an error occurs during the write back of the data from the write buffer to external memory, the data is transferred from the write buffer to the storage location of the data cache originally addressed by the processor before the memory bus is released.
摘要翻译：数据高速缓冲存储器的装置和方法，其在包括处理器的处理系统中提供从数据高速缓存写入缓冲器到外部存储器的数据复制期间的错误的处理。当处理器在数据高速缓存的寻址存储位置请求的数据是有效，修改的数据，而不是由处理器请求的数据时，数据首先被传送到数据高速缓存写入缓冲器，然后写回到外部从存储器总线中取出所请求的数据后的存储器。如果在将写入缓冲区写入外部存储器的数据写入期间发生错误，则在释放存储器总线之前，将数据从写入缓冲区传送到最初由处理器寻址的数据缓存的存储位置。

19. 发明授权

US08837226B2 Memory including a reduced leakage wordline driver 有权
标题翻译：存储器包括减少泄漏字线驱动器
公开(公告)号：US08837226B2
公开(公告)日：2014-09-16
申请号：US13286351
申请日：2011-11-01
申请人： Edward M. McCombs , Stephen C. Horne , Alexander E. Runas , Daniel C. Chow
发明人： Edward M. McCombs , Stephen C. Horne , Alexander E. Runas , Daniel C. Chow
IPC分类号： G11C11/34 , G11C8/08
CPC分类号： G11C8/08
摘要： A memory includes a wordline driver having reduced leakage. The memory includes a storage array coupled to a first voltage supply, and a number of wordline driver units each including a driver inverter. During a low power mode, the voltage of the voltage supply coupled to the wordline circuit is reduced or removed, while the voltage of the voltage supply coupled to the storage array is kept at least at a retention voltage. In addition a p-type transistor is coupled between the array voltage supply and an input to the wordline driver inverter, thereby keeping the output of the wordline driver inverter at a low logic level to prevent inadvertent wordline firing.
摘要翻译：存储器包括具有减少泄漏的字线驱动器。存储器包括耦合到第一电压源的存储阵列以及包括驱动器反相器的多个字线驱动器单元。在低功率模式期间，耦合到字线电路的电压源的电压被减小或去除，而耦合到存储阵列的电压源的电压至少保持在保持电压。此外，p型晶体管耦合在阵列电压源和字线驱动器反相器的输入之间，从而将字线驱动器反相器的输出保持在低逻辑电平以防止意外的字线触发。

20. 发明授权

US06271683B1 Dynamic logic scan gate method and apparatus 有权
标题翻译：动态逻辑扫描门法和装置
公开(公告)号：US06271683B1
公开(公告)日：2001-08-07
申请号：US09468972
申请日：1999-12-21
申请人： Stephen C. Horne , James S. Blomgren , Michael R. Seningen
发明人： Stephen C. Horne , James S. Blomgren , Michael R. Seningen
IPC分类号： H03K1900
CPC分类号： H03K19/096 , G06F1/08 , G06F5/015 , G06F7/02 , G06F7/026 , G06F7/483 , G06F7/49 , G06F7/508 , G06F7/5443 , G06F17/5045 , G06F2207/3824 , G11C7/1006 , G11C8/00 , G11C8/10 , G11C8/16 , G11C8/18 , G11C11/418 , G11C11/419 , G11C11/56 , G11C19/00 , H03K19/0002 , H03K19/00346 , H03K19/00361 , H03K19/00384 , H03K19/0813 , H03K19/0963 , H03K19/215
摘要： A method and apparatus for random-access scan of a network of dynamic logic or N-nary logic, wherein the network includes sequentially clocked precharge logic gates and one or more scan gates is disclosed. Each clocked precharge logic gate and each scan gate further comprise a logic tree having one or more evaluate nodes, a precharge circuit, an evaluate circuit, and one or more output buffers. Each scan gate further comprises a scan circuit that accepts scan control signals and couples to one or more scan registers in a RAM-like architecture. A scan control circuit generates scan control signals and scan timing signals which operate to capture the state of the output buffers of the scan gate and provide that state to one or more scan registers. Scan control signals and scan timing signals also operate to force the output buffers of the scan gate to a preselected level, which then propagates through the network to create an output state on the next scan gate in the network, which can then be read and compared to an expected output state given the output state of the previous scan gate.
摘要翻译：一种用于动态逻辑或N-Nary逻辑网络的随机存取扫描的方法和装置，其中所述网络包括顺序时钟的预充电逻辑门和一个或多个扫描门。每个时钟预充电逻辑门和每个扫描门还包括具有一个或多个评估节点，预充电电路，评估电路和一个或多个输出缓冲器的逻辑树。每个扫描门还包括扫描电路，该扫描电路接受扫描控制信号并且以类似RAM的架构耦合到一个或多个扫描寄存器。扫描控制电路产生扫描控制信号和扫描定时信号，其操作以捕获扫描门的输出缓冲器的状态，并将该状态提供给一个或多个扫描寄存器。扫描控制信号和扫描定时信号也可以将扫描门的输出缓冲器强制到预选的电平，然后传输通过网络在网络中的下一个扫描门上产生输出状态，然后可以读取和比较到给定前一扫描门的输出状态的预期输出状态。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式