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11. 发明申请

US20070195635A1 Non-volatile memory device with page buffer having dual registers and methods using the same 失效
标题翻译：具有双缓存器的页缓冲器的非易失性存储器件和使用其的方法
公开(公告)号：US20070195635A1
公开(公告)日：2007-08-23
申请号：US11358767
申请日：2006-02-21
申请人： Chung Chen , Jo Wang
发明人： Chung Chen , Jo Wang
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C7/1042 , G11C16/0483 , G11C16/10 , G11C16/102 , G11C16/105 , G11C16/26 , G11C2216/14
摘要： A non-volatile memory device with a page buffer having dual registers includes a memory cell array, a selector circuit and a page buffer circuit, the selector circuit being coupled to an exterior data line, the page buffer circuit including a first register and a second register being coupled between the memory cell array and the selector circuit, and the first register and second register being commonly coupled through a sense node. The first and second registers alternately write data to the memory cell array for programming. As one of the first and second registers performs programming, the other register stores data from the data line concurrently. In other words, the second register stores data from the data line when the first register is in programming, whereas the first register stores data from the data line when the second register is in programming.
摘要翻译：具有双寄存器的页缓冲器的非易失性存储器件包括存储单元阵列，选择器电路和页缓冲电路，选择器电路耦合到外部数据线，该页缓冲电路包括第一寄存器和第二寄存器寄存器耦合在存储单元阵列和选择器电路之间，并且第一寄存器和第二寄存器通常通过感测节点耦合。第一和第二寄存器交替地将数据写入存储单元阵列用于编程。作为第一和第二寄存器之一执行编程，其他寄存器同时存储来自数据线的数据。换句话说，当第一寄存器处于编程时，第二寄存器存储来自数据线的数据，而当第二寄存器处于编程时，第一寄存器存储来自数据线的数据。

12. 发明申请

US20070133304A1 Method and apparatus for determining sensing timing of flash memory 有权
公开(公告)号：US20070133304A1
公开(公告)日：2007-06-14
申请号：US11297527
申请日：2005-12-08
申请人： Chung Chen
发明人： Chung Chen
IPC分类号： G11C11/34
CPC分类号： G11C16/3436 , G11C16/28 , G11C16/32 , G11C16/3445 , G11C16/3459
摘要： A method of automatically determining a sensing timing in a page buffer of a NAND flash memory device is disclosed, which includes the steps of discharging a first reference bit line, discharging a second reference bit line, determining a first control signal and determining a second control signal. To perform the method, an apparatus of automatically determining a sensing timing in a page buffer of a NAND flash memory device is also disclosed. The apparatus includes a first reference bit line, a first current sink, a first reference page buffer, the second reference bit line, a second current sink and a second reference page buffer. The first reference bit line is coupled to the first current sink and the first reference page buffer at both ends thereof. The second reference bit line is coupled to the second current sink and the second reference page buffer at both ends thereof.

13. 发明申请

US20060240654A1 Process of forming a self-aligned contact in a semiconductor device 有权
标题翻译：在半导体器件中形成自对准接触的工艺
公开(公告)号：US20060240654A1
公开(公告)日：2006-10-26
申请号：US11111345
申请日：2005-04-22
申请人： An Wei , Chung Chen
发明人： An Wei , Chung Chen
IPC分类号： H01L21/4763
CPC分类号： H01L21/76897
摘要： A process is implemented to form a contact opening in a semiconductor device that includes a gate electrode on a substrate, a spacer on a sidewall of the gate electrode and a dielectric material covering the gate electrode. The process comprises forming a photoresist pattern on a surface of the dielectric material, etching the dielectric material until the bottom liner layer is exposed, forming a protective layer on a sidewall of the spacer while etching the dielectric material, and etching the bottom liner layer.
摘要翻译：实现了一种在半导体器件中形成接触开口的工艺，该半导体器件包括衬底上的栅电极，栅电极的侧壁上的间隔物和覆盖栅电极的电介质材料。该方法包括在电介质材料的表面上形成光致抗蚀剂图案，蚀刻电介质材料，直到底层衬底露出，在蚀刻电介质材料的同时在隔离物的侧壁上形成保护层，并蚀刻底衬层。

14. 发明申请

US20050195657A1 Bit switch voltage drop compensation during programming in nonvolatile memory 有权
标题翻译：非易失性存储器编程期间的位开关压降补偿
公开(公告)号：US20050195657A1
公开(公告)日：2005-09-08
申请号：US10792120
申请日：2004-03-03
申请人： Chung Chen
发明人： Chung Chen
IPC分类号： G11C11/22
CPC分类号： G11C5/147 , G11C5/143 , G11C7/12 , G11C16/24 , G11C16/28 , G11C16/30
摘要： A method is provided of regulating a supply voltage for providing a bit line voltage in a semiconductor memory device where the bit line voltage is provided to memory cells in a bit line from the supply voltage through a bit switch. A bit line current provided to the memory cells is detected. The supply voltage is adjusted responsive to the deducted bit line current to at least partially compensate for a voltage drop across the bit switch where the voltage drop is dependent at least in part on the bit line current.
摘要翻译：提供了一种调节用于在半导体存储器件中提供位线电压的电源电压的方法，其中位线电压通过位开关从电源电压提供给位线中的存储器单元。检测提供给存储器单元的位线电流。响应于扣除的位线电流来调节电源电压，以至少部分地补偿位开关上的电压降，其中电压降至少部分地取决于位线电流。

15. 发明授权

US06333940B1 Integrated digital loop carrier system with virtual tributary mapper circuit 失效
标题翻译：具有虚拟支路映射器电路的集成数字环路载波系统
公开(公告)号：US06333940B1
公开(公告)日：2001-12-25
申请号：US09475507
申请日：1999-12-30
申请人： Ertugrul Baydar , J. Bradley Boudreaux , Nicholas Carter , Chung Chen , Steven Klonsky , Michael Moran , Peter Renucci , Jeffrey Timbs , Thomas Tucker , Waleed Wardak
发明人： Ertugrul Baydar , J. Bradley Boudreaux , Nicholas Carter , Chung Chen , Steven Klonsky , Michael Moran , Peter Renucci , Jeffrey Timbs , Thomas Tucker , Waleed Wardak
IPC分类号： H04J306
CPC分类号： H04L41/0213 , H04J3/1611 , H04J2203/0028 , H04J2203/0041 , H04J2203/0046 , H04J2203/0048 , H04J2203/006 , H04L41/0226 , H04L41/046 , H04Q3/0095 , H04Q11/0407 , H04Q2213/13003 , H04Q2213/1301 , H04Q2213/13106 , H04Q2213/13176 , H04Q2213/13209 , H04Q2213/13292 , H04Q2213/1332 , H04Q2213/13367 , H04Q2213/13381
摘要： An integrated digital loop carrier (IDLC) system includes digital line feeders and signal processors to interface with the feeders and to ultimately provide data to subscriber instruments. The system can be employed as a central office terminal (COT) or remote digital terminal (RDT) with analog, T1 or SONET feeders and any conventional link medium. Data are put in DS1 format and multiplexed onto token ring optical loops for delivery to banks of channel units wherein the optical signals are translated to electrical signals for delivery to the CUs and subscribers. A method and apparatus is provided for mapping and demapping signals between virtual tributaries (VT) and digital signal formats in the RDT of an integrated digital loop carrier. An application-specific circuit provides such mapping and demapping functions as Floating Byte Synchronous VT to Locked Byte Synchronous VT, Floating Asynchronous VT to Locked Byte Synchronous VT, Floating Asynchronous VT to Floating Asynchronous VT, DS1 to Locked Byte Synchronous VT, DS1 to Floating Asynchronous VT, and DS1 to Floating Byte Synchronous VT.
摘要翻译：集成数字环路载波（IDLC）系统包括数字线路馈线和信号处理器，与馈线接口并最终向用户设备提供数据。该系统可以用作具有模拟，T1或SONET馈线和任何常规链路介质的中心局终端（COT）或远程数字终端（RDT）。数据采用DS1格式并复用到令牌环光环路上，用于传送到信道单元组，其中光信号被转换为电信号以传送到CU和用户。提供了一种用于在集成数字环路载波的RDT中的虚拟支路（VT）和数字信号格式之间映射和解映射信号的方法和装置。应用专用电路提供浮动字节同步VT到锁定字节同步VT，浮动异步VT到锁定字节同步VT，浮动异步VT到浮动异步VT，DS1到锁定字节同步VT，DS1到浮动异步的映射和解映射功能 VT和DS1到浮点字节同步VT。

16. 发明申请

US20070263446A1 Method for programming NAND flash memory device and page buffer performing the same 有权
标题翻译：用于编程NAND闪存器件和执行相同操作的页缓冲器的方法
公开(公告)号：US20070263446A1
公开(公告)日：2007-11-15
申请号：US11432416
申请日：2006-05-12
申请人： Chung Chen
发明人： Chung Chen
IPC分类号： G11C11/34 , G11C16/04 , G11C14/00
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C16/24 , G11C2211/5642
摘要： A method for programming a multi-level-cell NAND flash memory device having plural memory cells is disclosed to reduce the programming time. The method comprises: programming each memory cell to a zero state, programming from the zero state to a first state by activating a first program signal and programming from the zero state to a quasi-second state and a semi-third state by activating a second program signal, programming from the quasi-second state to a second state and programming from the semi-third state to a quasi-third state by activating the second program signal, and programming from the quasi-third state to a third state by activating the first program signal. The present invention also discloses a page buffer to perform the method for programming a multi-level-cell NAND flash memory device, which comprises a bit line selection circuit, a first register, a second register, a first verify circuit, a second verify circuit and an exclusion circuit.
摘要翻译：公开了一种用于编程具有多个存储器单元的多电平单元NAND快闪存储器件的方法，以减少编程时间。该方法包括：将每个存储器单元编程为零状态，通过激活第一程序信号并通过激活第二程序从零状态到准秒状态和半第三状态从零状态编程到第一状态程序信号，从准秒状态编程到第二状态，并通过激活第二程序信号从半第三状态到准第三状态的编程，以及通过激活第三状态从准第三状态进行编程第一个程序信号。本发明还公开了一种用于执行用于编程多电平单元NAND闪速存储器件的方法的页缓冲器，其包括位线选择电路，第一寄存器，第二寄存器，第一校验电路，第二校验电路和排除电路。

17. 发明申请

US20070263438A1 Method for reading NAND memory device and memory cell array thereof 有权
标题翻译：读取NAND存储器件及其存储单元阵列的方法
公开(公告)号：US20070263438A1
公开(公告)日：2007-11-15
申请号：US11432501
申请日：2006-05-12
申请人： Chung Chen
发明人： Chung Chen
IPC分类号： G11C16/04
CPC分类号： G11C16/26
摘要： A method for reading a NAND flash memory device having plural normal cells, which utilizes plural reference bit lines associated with plural reference cells to read the normal cells in one phase to reduce the read time, is disclosed. The method comprises ramping up a selected word line voltage in a predetermined period and reading the normal cells with a zero state, a first state, a second state and a third state in the predetermined period. The present invention also discloses a memory cell array concerning the method for reading a NAND flash memory device. The memory cell array, which utilizes a voltage generator and plural reference cells to read the normal cells in one phase to reduce the amount of precharging and discharging of the normal bit lines, comprises plural normal cell blocks arranged in parallel, plural reference cell blocks interleaved between the normal cell blocks, plural normal bit lines coupled to the normal cell blocks, plural reference bit lines coupled to the reference cell blocks and a voltage generator.
摘要翻译：公开了一种读取具有多个正常单元的NAND快闪存储器件的方法，其利用与多个参考单元相关联的多个参考位线以一个相位读取正常单元以减少读取时间。该方法包括在预定时间段内升高所选择的字线电压，并且在预定周期内以零状态，第一状态，第二状态和第三状态读取正常单元。本发明还公开了一种关于读取NAND闪存器件的方法的存储单元阵列。存储单元阵列利用电压发生器和多个参考单元在一个相位中读取正常单元以减少正常位线的预充电和放电量，包括并行排列的多个正常单元块，多个参考单元块交错在正常单元块之间，耦合到正常单元块的多个标准位线，耦合到参考单元块的多个参考位线和电压发生器。

18. 发明申请

US20070263437A1 METHOD AND APPARATUS TO IMPROVE NONVOLATILE MEMORY DATA RETENTION 有权
标题翻译：改善非易失性存储器数据保持的方法和装置
公开(公告)号：US20070263437A1
公开(公告)日：2007-11-15
申请号：US11382350
申请日：2006-05-09
申请人： Chung Chen
发明人： Chung Chen
IPC分类号： G11C16/06 , G11C11/34
CPC分类号： G11C16/3418 , G11C16/3431
摘要： Disclosed are apparatuses, methods, and manufacturing methods relating to improving data retention in nonvolatile memory. In many embodiments, monitor reference currents in addition to a normal reference current are used to determine whether to refresh the data memory.
摘要翻译：公开了与改善非易失性存储器中的数据保持有关的装置，方法和制造方法。在许多实施例中，除了正常参考电流之外，监视参考电流被用于确定是否刷新数据存储器。

19. 发明申请

US20070182883A1 Light Diffusion Module and a Back Light Module Using the Same 有权
标题翻译：光扩散模块和使用其的背光模块
公开(公告)号：US20070182883A1
公开(公告)日：2007-08-09
申请号：US11533846
申请日：2006-09-21
申请人： Chung Chen , Kuang Cheng , Kai-TI Chen
发明人： Chung Chen , Kuang Cheng , Kai-TI Chen
IPC分类号： G02F1/1335
CPC分类号： G02F1/133606 , G02F2001/133607
摘要： A light diffusion module and a back light module using the same. The light diffusion module is disposed corresponding to the light source module of the back light module. The light diffusion module includes a first diffusion layer and the second diffusion layer. The first diffusion layer is disposed on top of the light source module and the top light exit surface has a plurality of first micro structures juxtapositioned to each other. The second diffusion layer is disposed on top of the first diffusion layer, and the top surface has a plurality of second micro structures juxtapositioned to each other. The ratio of the width of each first micro structure to the width of each second micro structure is between 1.1 and 1.8. The ratio of the height of each first micro structure to the height of each second micro structure is between 0.8 and 1.5
摘要翻译：光扩散模块和使用其的背光模块。光扩散模块相对于背光模块的光源模块设置。光扩散模块包括第一扩散层和第二扩散层。第一扩散层设置在光源模块的顶部，顶部光出射表面具有彼此并置的多个第一微结构。第二扩散层设置在第一扩散层的顶部，并且顶表面具有彼此并置的多个第二微结构。每个第一微结构的宽度与每个第二微结构的宽度之比在1.1和1.8之间。每个第一微结构的高度与每个第二微结构的高度之比在0.8和1.5之间

20. 发明申请

US20060038600A1 Substantially temperature independent delay chain 有权
标题翻译：基本上独立于温度的延迟链
公开(公告)号：US20060038600A1
公开(公告)日：2006-02-23
申请号：US10922798
申请日：2004-08-20
申请人： Chung Chen
发明人： Chung Chen
IPC分类号： H03H11/26
CPC分类号： G11C7/22 , G11C7/04 , G11C7/222 , H03K2005/00097 , H03K2005/00117 , H03K2005/00143
摘要： Methods and apparatuses are discussed for generating a temperature compensated signal, used for example to provide a signal with a delay within a pre-specified range over a range of temperatures to a sense amplifier of a memory array. In response to a start signal, a varying signal is generated. A clock signal causes additional loads of impedance to be coupled to the varying signal, for example via control circuitry generating temperature compensating signals.
摘要翻译：讨论了用于产生温度补偿信号的方法和装置，其用于例如在存储器阵列的读出放大器的温度范围内提供具有在预定范围内的预定范围内的延迟的信号。响应于启动信号，产生变化的信号。时钟信号使额外的阻抗负载耦合到变化信号，例如通过产生温度补偿信号的控制电路。

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