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11. 发明申请

US20060291573A1 Signal interface 有权
标题翻译：信号接口
公开(公告)号：US20060291573A1
公开(公告)日：2006-12-28
申请号：US11168677
申请日：2005-06-28
申请人： Jung-Zone Chen , Tsung-Yu Wu , Ying-Lieh Chen
发明人： Jung-Zone Chen , Tsung-Yu Wu , Ying-Lieh Chen
IPC分类号： H04B3/00 , H04B1/38
CPC分类号： G09G3/3688 , G09G2310/0297
摘要： The present invention discloses a signal interface to transmit a data signal to a driving circuit. The signal interface comprises a first circuit, a second circuit and a data bus. The first circuit comprises a first register. The second circuit comprises a selector, a second register, a receiver and a third register. If the data signal is a single-end signal, the first register and the selector receive the data signal. Then, the selector transmits the data signal to the second register. The data bus transmits the signal saved in the first register and the second register to the driving circuit. If the data signal is a serial signal, the selector receives and transmits the data signal to the receiver to have it transferred to a single-end signal. Then, the signal is transmitted to the third register and output via the data bus.
摘要翻译：本发明公开了一种将数据信号发送到驱动电路的信号接口。信号接口包括第一电路，第二电路和数据总线。第一电路包括第一寄存器。第二电路包括选择器，第二寄存器，接收器和第三寄存器。如果数据信号是单端信号，则第一寄存器和选择器接收数据信号。然后，选择器将数据信号发送到第二寄存器。数据总线将保存在第一寄存器和第二寄存器中的信号发送到驱动电路。如果数据信号是串行信号，则选择器接收并发送数据信号给接收机以将其传送到单端信号。然后，信号被发送到第三寄存器并通过数据总线输出。

12. 发明授权

US08289302B2 Output buffer circuit with enhanced slew rate 有权
标题翻译：输出缓冲电路具有增强的压摆率
公开(公告)号：US08289302B2
公开(公告)日：2012-10-16
申请号：US12349432
申请日：2009-01-06
申请人： Yi-Jan Emry Chen , Pang-Jung Liu , Jyun-Ping Jiang , Tsung-Yu Wu
发明人： Yi-Jan Emry Chen , Pang-Jung Liu , Jyun-Ping Jiang , Tsung-Yu Wu
IPC分类号： G06F3/038
CPC分类号： H03K17/0412 , H03K19/0013 , H03K19/01707 , H03K2217/0036
摘要： An output buffer circuit with enhanced slew rate is disclosed. A first and a second slew-rate enhancing transistor are configured to enhance the slew rate of the source transistor and the sink transistor of an output stage. A first control circuit and a second control circuit turn off the first and the second slew-rate enhancing transistors during the static state, and turn on the first and the second slew-rate enhancing transistors during the transition.
摘要翻译：公开了一种具有增强压摆率的输出缓冲电路。第一和第二转换速率增强晶体管被配置为增强输出级的源极晶体管和吸收晶体管的转换速率。第一控制电路和第二控制电路在静态期间关断第一和第二压摆率增强晶体管，并且在转换期间导通第一和第二压摆率增强晶体管。

13. 发明申请

US20110069260A1 Display panel and repair method thereof 审中-公开
标题翻译：显示面板及其修理方法
公开(公告)号：US20110069260A1
公开(公告)日：2011-03-24
申请号：US12590777
申请日：2009-11-13
申请人： He-Yuan Yang , Che-Hsiu Yang , You-Ming Nian , Ching-Yao Chen , Tsung-Yu Wu
发明人： He-Yuan Yang , Che-Hsiu Yang , You-Ming Nian , Ching-Yao Chen , Tsung-Yu Wu
IPC分类号： G02F1/1333 , H01J9/50
CPC分类号： G02F1/1309 , G02F1/133512 , G02F2201/508
摘要： A method for repairing a display panel having a defect is provided, wherein a polarizer has been attached to a surface of the display panel, and the method includes following steps. First, a recess corresponding to the defect is formed at an outer surface of the polarizer. Afterward, a light-shielding material is filled into the recess. Besides, a display panel with a good display quality is also provided.
摘要翻译：提供了一种用于修复具有缺陷的显示面板的方法，其中偏振器已经附着到显示面板的表面，并且该方法包括以下步骤。首先，在偏振片的外表面形成与缺陷相对应的凹部。之后，遮光材料被填充到凹部中。此外，还提供了具有良好显示质量的显示面板。

14. 发明申请

US20110051361A1 ELECTRONIC DEVICE 有权
标题翻译：电子设备
公开(公告)号：US20110051361A1
公开(公告)日：2011-03-03
申请号：US12623519
申请日：2009-11-23
申请人： Wen-Ji Tsai , Bo-Ren Yan , Tsung-Yu Wu
发明人： Wen-Ji Tsai , Bo-Ren Yan , Tsung-Yu Wu
IPC分类号： G06F1/16
CPC分类号： G06F1/1643 , G06F1/1616 , G06F3/0428
摘要： An electronic device is provided, including a first body, a second body, an axle assembly, a supporting frame, a display panel, a lens unit and a reflective unit. The second body is connected to the first body. The axle assembly is disposed between the first body and the second body, and via which first body is rotatable relative to the second body. The supporting frame is disposed in the second body and connected to the axle assembly, wherein the supporting frame is rotated with the rotation of the axle assembly. The display panel is fastened in the supporting frame. The lens unit is disposed on an end of the supporting frame. The reflective unit is disposed on the supporting frame and adjacent to the display panel.
摘要翻译：提供一种电子设备，包括第一主体，第二主体，轴组件，支撑框架，显示面板，透镜单元和反射单元。第二主体连接到第一主体。轴组件设置在第一主体和第二主体之间，并且第一主体经由该第一主体相对于第二主体可旋转。支撑框架设置在第二主体中并连接到轴组件，其中支撑框架随着轴组件的旋转而旋转。显示面板固定在支撑框架中。透镜单元设置在支撑框架的一端。反射单元设置在支撑框架上并且与显示面板相邻。

15. 发明申请

US20100213918A1 Layout of a Reference Generating System 有权
标题翻译：参考生成系统的布局
公开(公告)号：US20100213918A1
公开(公告)日：2010-08-26
申请号：US12393955
申请日：2009-02-26
申请人： Yi-Chang Lu , Cheng-Hung Li , Chung-Yui Kuo , Tsung-Yu Wu
发明人： Yi-Chang Lu , Cheng-Hung Li , Chung-Yui Kuo , Tsung-Yu Wu
IPC分类号： G05F3/00
CPC分类号： G05F3/08
摘要： A layout of a voltage/current reference system is disclosed. A first voltage/current reference circuit (for example, a bandgap reference circuit) and a second voltage/current reference circuit are respectively laid out on either side of a substrate, such as edges or perimeter sides of the substrate. A reference voltage/current is derived by averaging respective output reference voltage/current values of the first and the second voltage/current reference circuits. Accordingly, the noise influence on the voltage/current reference system is minimized.
摘要翻译：公开了电压/电流参考系的布局。第一电压/电流参考电路（例如，带隙参考电路）和第二电压/电流参考电路分别布置在诸如衬底的边缘或周边侧的衬底的任一侧上。通过平均第一和第二电压/电流参考电路的各个输出参考电压/电流值来导出参考电压/电流。因此，对电压/电流参考系统的噪声影响被最小化。

16. 发明申请

US20100213764A1 Power Distribution System 有权
标题翻译：配电系统
公开(公告)号：US20100213764A1
公开(公告)日：2010-08-26
申请号：US12393994
申请日：2009-02-26
申请人： Yi-Chang Lu , Cheng-Hung Li , Chung-Yui Kuo , Tsung-Yu Wu
发明人： Yi-Chang Lu , Cheng-Hung Li , Chung-Yui Kuo , Tsung-Yu Wu
IPC分类号： H05K1/11
CPC分类号： H02J1/06 , H05K1/0265 , H05K2201/09254 , H05K2201/09727 , H05K2201/0979 , Y10T307/492
摘要： A power distribution system is disclosed. The system includes a first power line and a second power line laid out on a substrate. The first power line is spaced apart from the second power line. The system also includes at least one conductive connecting line that electrically couples the first power line at one end and the second power line at another end. A power supply supplies power to the first power line and the second power line. A supply node on the conductive connecting line is then used to provide the supplied power.
摘要翻译：公开了配电系统。该系统包括布置在基板上的第一电源线和第二电源线。第一电力线与第二电力线隔开。该系统还包括至少一个导电连接线，其在一端电耦合第一电力线和在另一端电耦合第二电力线。电源为第一电力线和第二电力线供电。然后使用导电连接线上的供电节点来提供所供电的电力。

17. 发明授权

US07136039B2 Method and related apparatus for driving an LCD monitor 有权
公开(公告)号：US07136039B2
公开(公告)日：2006-11-14
申请号：US10065665
申请日：2002-11-07
申请人： Lin-Kai Bu , Chin-Feng Cheng , Tsung-Yu Wu , Chuan-Cheng Hsiao
发明人： Lin-Kai Bu , Chin-Feng Cheng , Tsung-Yu Wu , Chuan-Cheng Hsiao
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3614 , G09G3/3648 , G09G3/3685 , G09G3/3696 , G09G2310/027 , G09G2310/0291 , G09G2310/0297 , G09G2320/0233 , G09G2320/0276 , G09G2330/021
摘要： A method for driving an LCD monitor is disclosed. The LCD monitor includes a voltage selection unit used for outputting a plurality of driving voltages according to display data, and a plurality of output buffers each electrically connected to the voltage selection circuit and a corresponding pixel. In the beginning, an output port of each output buffer approaches voltage at an input port. Then, the output ports of the driving units, which approach the same input voltage, are electrically connected to have an average voltage. In addition, the LCD monitor further includes a timing controller for controlling operation of the output buffers. When output ports of the output buffers, which approach the same input voltage, are electrically connected, the output buffers are turned off for saving power.

18. 发明申请

US20060238228A1 Cascade system capable of restraining duty cycle offsets 审中-公开
标题翻译：级联系统能够限制占空比偏移
公开(公告)号：US20060238228A1
公开(公告)日：2006-10-26
申请号：US11407369
申请日：2006-04-20
申请人： Tsung-Yu Wu , Lin-Kai Bu
发明人： Tsung-Yu Wu , Lin-Kai Bu
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： The invention relates to a cascade system capable of restraining duty cycle offsets. The cascade system receives an input signal with an input duty cycle. The cascade system comprises a plurality of circuit units. The circuit units are connected in series. Each circuit unit receives a signal from a previous circuit unit. Through at least one circuit unit, a duty cycle offset exists between the processing duty cycle and the input duty cycle. At least one circuit unit is selected at predetermined intervals, and the processing signal thereof is inverted so that the duty cycle offsets are compensated for and restrained within a predetermined range
摘要翻译：本发明涉及能够抑制占空比偏移的级联系统。级联系统接收具有输入占空比的输入信号。级联系统包括多个电路单元。电路单元串联连接。每个电路单元接收来自先前电路单元的信号。通过至少一个电路单元，在处理占空比和输入占空比之间存在占空比偏移。以预定间隔选择至少一个电路单元，并且其处理信号被反转，使得占空比偏移在预定范围内被补偿和约束

19. 发明授权

US07764259B2 Wire-on-array liquid crystal display 有权
标题翻译：线阵列液晶显示器
公开(公告)号：US07764259B2
公开(公告)日：2010-07-27
申请号：US11267289
申请日：2005-11-07
申请人： Tsung-Yu Wu , Ying-Lieh Chen , Lin-Kai Bu
发明人： Tsung-Yu Wu , Ying-Lieh Chen , Lin-Kai Bu
IPC分类号： G09G3/36
CPC分类号： G09G3/2096 , G09G2310/0275 , G09G2320/0223
摘要： A wire-on-array (WOA) flat panel display is provided. The wire-on-array (WOA) flat panel display is characterized in a plurality of high input impedance components between the flexible printed circuit (FPC) board and the corresponding source driver circuits. Each of the high input impedance components is able to receive gamma voltages with little input current and then transmit the gamma voltages to each of the source driver circuit for production of source voltages of little banding effect.
摘要翻译：提供线阵列（WOA）平板显示器。线对阵（WOA）平板显示器的特征在于柔性印刷电路板（FPC）板和对应的源极驱动电路之间的多个高输入阻抗分量。每个高输入阻抗分量能够接收具有很小输入电流的伽马电压，然后将伽马电压传输到每个源极驱动电路，用于产生具有小带效应的源电压。

20. 发明申请

US20100171727A1 Output Buffer Circuit with Enhanced Slew Rate 有权
标题翻译：具有增强压摆率的输出缓冲电路
公开(公告)号：US20100171727A1
公开(公告)日：2010-07-08
申请号：US12349432
申请日：2009-01-06
申请人： Yi-Jan Emry Chen , Pang-Jung Liu , Jyun-Ping Jiang , Tsung-Yu Wu
发明人： Yi-Jan Emry Chen , Pang-Jung Liu , Jyun-Ping Jiang , Tsung-Yu Wu
IPC分类号： G06F3/038
CPC分类号： H03K17/0412 , H03K19/0013 , H03K19/01707 , H03K2217/0036
摘要： An output buffer circuit with enhanced slew rate is disclosed. A first and a second slew-rate enhancing transistor are configured to enhance the slew rate of the source transistor and the sink transistor of an output stage. A first control circuit and a second control circuit turn off the first and the second slew-rate enhancing transistors during the static state, and turn on the first and the second slew-rate enhancing transistors during the transition.
摘要翻译：公开了一种具有增强压摆率的输出缓冲电路。第一和第二转换速率增强晶体管被配置为增强输出级的源极晶体管和吸收晶体管的转换速率。第一控制电路和第二控制电路在静态期间关断第一和第二压摆率增强晶体管，并且在转换期间导通第一和第二压摆率增强晶体管。

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