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11. 发明授权

US5235592A Dynamic switch protocols on a shared medium network 失效
标题翻译：一个共享媒体网络的动态切换协议
公开(公告)号：US5235592A
公开(公告)日：1993-08-10
申请号：US744153
申请日：1991-08-13
申请人： Ting D. Cheng , Peter A. Franaszek , Christos J. Georgiou , Gregory M. Nordstrom , Thomas K. Philips , Martin W. Sachs , Anujan M. Varma , Thomas M. Walker
发明人： Ting D. Cheng , Peter A. Franaszek , Christos J. Georgiou , Gregory M. Nordstrom , Thomas K. Philips , Martin W. Sachs , Anujan M. Varma , Thomas M. Walker
IPC分类号： H04L12/417 , H04L29/06
CPC分类号： H04L29/06 , H04L12/417
摘要： Dynamic switch protocols are implemented on a token bus protocol in a shared medium network to improve the basic token bus functional capabilities and link utilization, and to produce a uniform transaction protocol that supports both token bus and dynamic switch networks. Frame formats common to both token bus and dynamic switch protocols are utilized, and circuit switched protocols are superimposed on a token bus protocol in interlocked and data transmissions to establish a circuit switched path between a token holder sender node and a destination node. An initial frame transmission uses a normal link header and establishes the circuit switched path between the sender node and the destination node. Subsequent data frames contain no link header information, thereby improving transmission efficiency, and the last frame in such a transmission disconnects the switched circuit path, thereby allowing other transmissions to resume. The use of circuit switched protocols within a token bus protocol allows more general transmission sequences and improves the utilization of token bus bandwidth.

12. 发明授权

US4929940A Collision crossbar switch 失效
标题翻译：碰撞横梁开关
公开(公告)号：US4929940A
公开(公告)日：1990-05-29
申请号：US275164
申请日：1988-11-18
申请人： Peter A. Franaszek , Christos J. Georgiou
发明人： Peter A. Franaszek , Christos J. Georgiou
IPC分类号： H04Q3/52 , H04Q11/04
CPC分类号： H04L49/101 , H04L49/252 , H04Q11/04
摘要： A high speed collision N.times.M tri-state crossbar switch having M collision busses uses contention detection at the destination. In the event of a collision of messages, remedial action can be taken such as rerouting colliding messages over an alternate path provided by a second interconnection network with contention resolution capability. Collision detection codes are transmitted prior to the transmission of messages to each input port. The tri-state output buses are monitored for the collison detection codes to detect an error. In order to prevent damage to driver transistors connected to the tri-state buses when a contention occurs, current limiting is provided to limit the current through the driver transistors to a predetermined level.

13. 发明授权

US4635250A Full-duplex one-sided cross-point switch 失效
标题翻译：全双工单向交叉点开关
公开(公告)号：US4635250A
公开(公告)日：1987-01-06
申请号：US599874
申请日：1984-04-13
申请人： Christos J. Georgiou
发明人： Christos J. Georgiou
IPC分类号： H03K17/00 , H04Q3/52 , H04Q3/00
CPC分类号： H04Q3/521
摘要： A full-duplex one-sided switching chip comprising externally connected lines as input/output pairs and pairs of bi-directional interconnection lines. Duplex cross-points selectively connect input/output line pairs to the interconnection line pairs. The interconnection lines can be coupled to interconnection lines on other chips for multichip switching arrays.
摘要翻译：一种全双工单向切换芯片，包括外部连接的线路作为输入/输出对和双向互连线对。双工交叉点选择性地将输入/输出线对连接到互连线对。互连线可以耦合到用于多芯片开关阵列的其它芯片上的互连线。

14. 发明授权

US4630045A Controller for a cross-point switching matrix 失效
标题翻译：用于交叉点开关矩阵的控制器
公开(公告)号：US4630045A
公开(公告)日：1986-12-16
申请号：US544653
申请日：1983-10-24
申请人： Christos J. Georgiou
发明人： Christos J. Georgiou
IPC分类号： H04Q3/545 , H04Q3/52 , H04Q9/00
CPC分类号： H04Q3/521
摘要： A controller for controlling a one-sided switching matrix comprising a plurality of circuit elements under the control of logic circuitry. The controller interprets a request for connection or disconnection, determines if it is possible, selects a path through the matrix and sends control signals to the matrix. The circuit elements are arranged in a parallel/pipeline architecture with multiple circuit elements simultaneously operating on a request. The controller can fetch a second request while executing a first request. The result of a request is to connect or disconnect interconnection paths on the switching matrix.
摘要翻译：一种用于在逻辑电路的控制下控制包括多个电路元件的单面开关矩阵的控制器。控制器解释连接或断开请求，确定是否可能，选择通过矩阵的路径，并向矩阵发送控制信号。电路元件被布置成并行/流水线架构，其中多个电路元件同时根据请求进行操作。执行第一个请求时，控制器可以获取第二个请求。请求的结果是连接或断开交换矩阵上的互连路径。

15. 发明授权

US08811422B2 Single chip protocol converter 有权
标题翻译：单芯片协议转换器
公开(公告)号：US08811422B2
公开(公告)日：2014-08-19
申请号：US13269065
申请日：2011-10-07
申请人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
发明人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
IPC分类号： H04J3/16 , G06F15/167 , H04L12/56 , G06F15/78
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译：一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行在单一集成电路芯片内。单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。

16. 发明申请

US20120082171A1 SINGLE CHIP PROTOCOL CONVERTER 有权
标题翻译：单芯片协议转换器
公开(公告)号：US20120082171A1
公开(公告)日：2012-04-05
申请号：US13269065
申请日：2011-10-07
申请人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
发明人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
IPC分类号： H04L12/00
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译：一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行在单一集成电路芯片内。单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。

17. 发明申请

US20090059955A1 SINGLE CHIP PROTOCOL CONVERTER 失效
标题翻译：单芯片协议转换器
公开(公告)号：US20090059955A1
公开(公告)日：2009-03-05
申请号：US12189675
申请日：2008-08-11
申请人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
发明人： Christos J. Georgiou , Victor L. Gregurick , Indira Nair , Valentina Salapura
IPC分类号： H04J3/22
CPC分类号： G06F15/7842 , G06F15/167 , G06F15/7825 , G06F15/7832 , H04L49/109 , H04L49/602
摘要： A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. Packet conversion may additionally entail converting packets generated according to a first protocol version level and processing the said packets to implement protocol conversion for generating converted packets according to a second protocol version level, but within the same protocol family type. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.
摘要翻译：一种单芯片协议转换器集成电路（IC），其能够接收根据第一协议类型生成的分组，并且处理所述分组以实现协议转换并产生用于输出的第二协议类型的转换分组，所述协议转换的过程完全执行在单个集成电路芯片内。单片协议转换器可以进一步实现为片上系统（SoC）实现中的宏核心，其中协议转换过程包含在SoC协议转换宏核内，而不需要主机系统的处理资源。分组转换还可能需要转换根据第一协议版本级别生成的分组，并且处理所述分组以实现根据第二协议版本级别而是在相同协议族类型内生成转换的分组的协议转换。单芯片协议转换器集成电路和SoC协议转换宏实现包括多处理能力，包括可配置为适应和修改芯片的操作功能的处理器设备。

18. 发明授权

US5355366A Traffic intermixing mechanism for fast circuit switching 失效
标题翻译：快速电路切换的交通混合机制
公开(公告)号：US5355366A
公开(公告)日：1994-10-11
申请号：US51968
申请日：1993-04-23
申请人： Chung-Sheng Li , Christos J. Georgiou
发明人： Chung-Sheng Li , Christos J. Georgiou
IPC分类号： H04L29/08 , H04L12/64 , H04J3/16
CPC分类号： H04L12/6402 , H04L2012/6408 , H04L2012/6459
摘要： A method and apparatus for intermixing circuit and packet data on a shared transmission medium. With this invention, the history of gaps between transmitted circuit frames is used to predict future gap sizes. If the size of a predicted gap is larger than the size of a frame of packet data to be transmitted, then the packet data is inserted in the next gap. If a circuit data frame arrives before the completion of transmission of a packet frame, the circuit data will be stored in an insertion buffer until completion of transmission of the packet frame.
摘要翻译：一种在共享传输介质上混合电路和分组数据的方法和装置。利用本发明，传输电路帧之间的间隙的历史用于预测未来的间隙大小。如果预测间隙的大小大于要发送的分组数据的大小，则将分组数据插入到下一个间隙中。如果电路数据帧在分组帧的传输完成之前到达，则电路数据将被存储在插入缓冲器中，直到分组帧的传输完成。

19. 发明授权

US07917729B2 System on chip IC with subsystem of multiple processing cores switch coupled to network protocol device and bus bridge to local system bus 有权
标题翻译：具有多处理核心子系统的片上集成电路交换机与网络协议设备和总线桥耦合到本地系统总线
公开(公告)号：US07917729B2
公开(公告)日：2011-03-29
申请号：US11757166
申请日：2007-06-01
申请人： Christos J. Georgiou , Victor L. Gregurick , Valentina Salapura
发明人： Christos J. Georgiou , Victor L. Gregurick , Valentina Salapura
IPC分类号： G06F15/16
CPC分类号： G06F15/7832 , H04L49/109 , H04L49/602
摘要： A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means connecting each processor cluster within an SoC integrated circuit (IC). The single SoC independent multiprocessor subsystem core is capable of performing multi-threading operation processing for SoC devices when configured as a DSP, coprocessor, Hybrid ASIC, or network processing arrangements. The switch fabric means additionally interconnects a SoC local system bus device with SoC processor components with the independent multiprocessor subsystem core.
摘要翻译：一种片上系统（SoC）组件，其包括包括多个多个处理器的单个独立多处理器子系统核心，每个多处理器具有与其相关联的本地存储器形成处理器集群; 并且交换结构意味着连接SoC集成电路（IC）中的每个处理器集群。当配置为DSP，协处理器，混合ASIC或网络处理安排时，单个SoC独立多处理器子系统内核能够对SoC设备执行多线程操作处理。交换结构意味着另外将SoC本地系统总线设备与SoC处理器组件与独立的多处理器子系统核心互连。

20. 发明申请

US20080313339A1 CONNECTION MANAGEMENT METHOD, SYSTEM, AND PROGRAM PRODUCT 失效
标题翻译：连接管理方法，系统和程序产品
公开(公告)号：US20080313339A1
公开(公告)日：2008-12-18
申请号：US12191336
申请日：2008-08-14
申请人： Marc R. Faucher , Christos J. Georgiou , Ann Marie Rincon
发明人： Marc R. Faucher , Christos J. Georgiou , Ann Marie Rincon
IPC分类号： G06F15/16
CPC分类号： G06F13/385 , G06F12/0875 , G06F12/122 , H04L49/90 , H04L67/14 , H04L69/28
摘要： The invention provides a method, system, and program product for managing a connection. In particular, the invention manages connection information in memory based on an expected usage of the corresponding connection. Connection information can be stored in faster memory, such as cache memory, when the connection is expected to have numerous additional messages. Similarly, the connection information for a connection not expected to have many additional messages can be swapped out of the cache memory and stored in relatively slower memory. As a result, the connection information that is more frequently used is more likely to be available in a faster memory.
摘要翻译：本发明提供了一种用于管理连接的方法，系统和程序产品。特别地，本发明基于相应连接的预期使用来管理存储器中的连接信息。连接信息可以存储在较快的存储器中，如缓存存储器，当连接预期有大量附加消息时。类似地，不期望具有许多附加消息的连接的连接信息可以从高速缓存存储器中交换并存储在相对较慢的存储器中。因此，更频繁使用的连接信息更有可能在更快的存储器中可用。

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