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11. 发明授权

US06171962B2 Shallow trench isolation formation without planarization mask 失效
标题翻译：浅沟槽隔离形成无平面化掩模
公开(公告)号：US06171962B2
公开(公告)日：2001-01-09
申请号：US08993889
申请日：1997-12-18
申请人： Olov Karlsson , Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Larry Wang , Effiong Ibok
发明人： Olov Karlsson , Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Larry Wang , Effiong Ibok
IPC分类号： H01L21302
CPC分类号： H01L21/76229 , H01L21/31053
摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate without a planarization mask or etch. Embodiments include forming trenches and refilling them with an insulating material which also covers the substrate surface, followed by polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches. A second layer of insulating material is then deposited to fill seams in the insulating material above the small trenches and to fill steps in the insulating material above the large trenches. The insulating material is then planarized. Since the insulating material is partially planarized by the first polish and the seams and steps are filled by the second deposition, the resulting topography of the upper surface of the second layer of insulating material is small enough to enable a direct final polish without the need to create and implement a planarization mask and to perform an etch and mask removal, thereby reducing manufacturing costs and increasing production throughput.
摘要翻译：在半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构，而不需要平坦化掩模或蚀刻。实施例包括用绝缘材料形成沟槽并再填充它们，该绝缘材料也覆盖衬底表面，接着进行抛光以除去绝缘材料的上部并使小沟槽上方的绝缘材料平坦化。然后沉积第二层绝缘材料以填充小沟槽上方的绝缘材料中的接缝，并填充大沟槽上方的绝缘材料的步骤。然后将绝缘材料平坦化。由于绝缘材料被第一抛光部分地平坦化并且接缝和步骤通过第二次沉积来填充，所以第二层绝缘材料的上表面的所得形貌足够小以使得能够进行直接的最终抛光，而不需要创建并实现平面化掩模并执行蚀刻和掩模去除，从而降低制造成本并提高生产量。

12. 发明授权

US6130467A Shallow trench isolation with spacers for improved gate oxide quality 失效
标题翻译：浅沟槽隔离带隔板，提高栅极氧化物质量
公开(公告)号：US6130467A
公开(公告)日：2000-10-10
申请号：US993857
申请日：1997-12-18
申请人： Basab Bandyopadhyay , Nick Kepler , Olov Karlsson , Larry Wang , Effiong Ibok , Christopher F. Lyons
发明人： Basab Bandyopadhyay , Nick Kepler , Olov Karlsson , Larry Wang , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L21/762 , H01L29/00
CPC分类号： H01L21/76224
摘要： An insulated trench isolation structure is formed in a semiconductor substrate with an oxide or nitride spacer overlying and protecting a portion of a pad oxide layer at the trench edge such that the pad oxide layer acts as part of the gate oxide layer. Embodiments include providing a step between the trench fill and the pad oxide layer and forming the protective spacer thereon. The protective spacer protects the underlying portion of the pad oxide layer at the trench edge during pad oxide removal prior to forming a gate oxide. Therefore, it is only necessary to grow the gate oxide on the main surface of the substrate, not at the trench edges. The gate oxide can then be formed uniformly thin, while the remaining pad oxide at the trench edges is relatively thick.
摘要翻译：在具有氧化物或氮化物间隔物的半导体衬底中形成绝缘沟槽隔离结构，覆盖并保护沟槽边缘处的焊盘氧化物层的一部分，使得焊盘氧化物层用作栅极氧化物层的一部分。实施例包括在沟槽填充物和衬垫氧化物层之间提供步骤，并在其上形成保护隔离物。在形成栅极氧化物之前，保护间隔物在衬垫氧化物去除期间保护焊盘氧化物层的沟槽边缘的下面部分。因此，仅需要在衬底的主表面上而不是在沟槽边缘处生长栅极氧化物。然后可以将栅极氧化物均匀地形成，而沟槽边缘处的剩余焊盘氧化物相对较厚。

13. 发明授权

US5930645A Shallow trench isolation formation with reduced polish stop thickness 失效
标题翻译：浅沟隔离结构，减少抛光停止厚度
公开(公告)号：US5930645A
公开(公告)日：1999-07-27
申请号：US993881
申请日：1997-12-18
申请人： Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Olov Karlsson , Larry Wang , Effiong Ibok
发明人： Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Olov Karlsson , Larry Wang , Effiong Ibok
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232
摘要： An insulated trench isolation structure is formed in a semiconductor substrate using a thin amorphous silicon or polysilicon polish stop layer by adding a reflectance compensation layer on the polish stop layer. As a result, the topological step between the main surface of the substrate and the uppermost surface of the trench fill is reduced, thereby facilitating the application and enhancing the accuracy of photolithographic techniques in forming features with minimal dimensions.
摘要翻译：通过在抛光停止层上添加反射率补偿层，在半导体衬底中使用薄的非晶硅或多晶硅抛光停止层形成绝缘沟槽隔离结构。结果，衬底的主表面和沟槽填充物的最上表面之间的拓扑步骤减少，从而有助于在最小尺寸形成特征时光刻技术的应用和提高精度。

14. 发明授权

US06239031B1 Stepper alignment mark structure for maintaining alignment integrity 有权
标题翻译：用于保持对准完整性的步进对准标记结构
公开(公告)号：US06239031B1
公开(公告)日：2001-05-29
申请号：US09487493
申请日：2000-01-19
申请人： Nick Kepler , Olov Karlsson , Larry Wang , Basab Bandyopadhyah , Effiong Ibok , Christopher F. Lyons
发明人： Nick Kepler , Olov Karlsson , Larry Wang , Basab Bandyopadhyah , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L21302
CPC分类号： G03F9/7076 , G03F9/70 , H01L23/544 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： Accurate photolighographic processing is achieved employing a stepper global alignment structure enabling formation thereon of a substantially transparent layer having a substantially planar upper surface. Embodiments include a set of global alignment marks comprising spaced apart trenches, each trench segmented into a plurality of narrow trenches spaced apart by uprights and forming a dummy topographical area of narrow trenches surrounding the set of alignment marks. The segmented trenches and the dummy topographical area effectively provide a substantially uniform topography enabling deposition of a transparent layer without steps and effective local planarization. Since the upper surface of the transparent layer is substantially planar, layers of material deposited on the transparent layer during subsequent processing also have a substantially planar upper surface, thereby enabling transmission of the signal produced by the alignment marks to the stepper with minimal distortion.
摘要翻译：使用步进全局对准结构可实现准确的视差处理，该结构能够在其上形成具有基本平坦的上表面的基本透明的层。实施例包括一组包括间隔开的沟槽的全局对准标记，每个沟槽被分段成由立柱间隔开的多个窄沟槽，并形成围绕该组对准标记的窄沟槽的虚拟地形区域。分段沟槽和虚拟地形区域有效地提供基本均匀的形貌，使得能够沉积透明层而无需步骤和有效的局部平面化。由于透明层的上表面基本上是平面的，因此在随后的处理期间沉积在透明层上的材料层也具有基本平坦的上表面，从而能够以最小的变形将由对准标记产生的信号传输到步进机。

15. 发明授权

US6090713A Shallow trench isolation formation with simplified reverse planarization mask 失效
标题翻译：浅沟槽隔离形成，具有简化的反向平面化掩模
公开(公告)号：US6090713A
公开(公告)日：2000-07-18
申请号：US992491
申请日：1997-12-18
申请人： Olov Karlsson , Christopher F. Lyons , Basab Bandyophadhyay , Nick Kepler , Larry Wang , Effiong Ibok
发明人： Olov Karlsson , Christopher F. Lyons , Basab Bandyophadhyay , Nick Kepler , Larry Wang , Effiong Ibok
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/316
CPC分类号： H01L21/76229 , H01L21/31053 , H01L21/31055
摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate using a simplified reverse source/drain planarization mask. Embodiments include forming trenches and refilling them with an insulating material which also covers the substrate surface, polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches, depositing a second, thin layer of insulating material filling seams in the insulating material above the small trenches, masking the insulating material above the large trenches, isotropically etching, and polishing to planarize the insulating material. Since the insulating material is partially planarized and the seams over the small trenches are filled, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. The use of a planarization mask having relatively few features with relatively large geometry avoids the necessity of creating and implementing a complex, critical mask, thereby reducing manufacturing costs and increasing production throughput.
摘要翻译：使用简化的反向源极/漏极平面化掩模在半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构。实施例包括形成沟槽并用也覆盖衬底表面的绝缘材料再填充它们，抛光以去除绝缘材料的上部并平面化小沟槽上方的绝缘材料，沉积第二薄层的绝缘材料填充接缝在小沟槽上方的绝缘材料中，掩蔽大沟槽上方的绝缘材料，各向同性蚀刻和抛光以使绝缘材料平坦化。由于绝缘材料被部分平坦化并且填充了小沟槽上的接缝，所以可以在仅在大沟槽而不是小沟槽上形成相对简单的平坦化掩模之后进行蚀刻。使用具有相对较小几何特征的平面化掩模具有相对大的几何形状避免了创建和实施复杂的关键掩模的必要性，从而降低制造成本并提高生产量。

16. 发明授权

US06238986B1 Formation of junctions by diffusion from a doped film at silicidation 有权
标题翻译：通过硅化物从掺杂膜扩散形成结
公开(公告)号：US06238986B1
公开(公告)日：2001-05-29
申请号：US09187427
申请日：1998-11-06
申请人： Nick Kepler , Karsten Wieczorek , Larry Wang , Paul Raymond Besser
发明人： Nick Kepler , Karsten Wieczorek , Larry Wang , Paul Raymond Besser
IPC分类号： H01L2128
CPC分类号： H01L29/66575 , H01L21/2257 , H01L21/823814 , H01L21/823835 , H01L29/665
摘要： High integrity shallow source/drain junctions are formed employing cobalt silicide contacts. A layer of cobalt and a cap layer of titanium or titanium nitride are deposited on a substrate above intended source/drain regions, followed by silicidation. Embodiments include low-temperature rapid thermal annealing to form a high-resistivity phase cobalt silicide, removing the cap layer, depositing a doped film on the first phase cobalt silicide, and heating, as by high-temperature rapid thermal annealing, to form a low-resistance cobalt silicide during which impurities from the doped film diffuse through the cobalt silicide into the substrate to form source/drain regions having junctions extending into the substrate a constant depth below the cobalt silicide/silicon substrate interface. In another embodiment, impurities are diffused from the doped film to form source/drain regions and self-aligned junctions following formation of the low-resistance phase cobalt silicide. The formation of source/drain junctions self-aligned to the cobalt silicide/silicon substrate interface prevents junction leakage while allowing the formation of cobalt silicide contacts at optimum thickness to avoid parasitic series resistances, thereby facilitating reliable device scaling.
摘要翻译：使用硅化钴接触形成高度完整的浅源极/漏极结。一层钴和钛或氮化钛的覆盖层沉积在预期的源极/漏极区域上的衬底上，随后进行硅化。实施例包括低温快速热退火以形成高电阻率相硅化钴，去除覆盖层，在第一相钴硅化物上沉积掺杂膜，并且通过高温快速热退火加热以形成低电阻的硅化钴，其中来自掺杂膜的杂质通过硅化钴扩散到衬底中以形成具有在硅化钴/硅衬底界面下方延伸到衬底中的连续恒定深度的接合的源/漏区。在另一个实施例中，在形成低电阻相钴硅化物之后，杂质从掺杂膜扩散以形成源/漏区和自对准结。与硅化钴/硅衬底界面自对准的源极/漏极结的形成可防止结合泄漏，同时允许以最佳厚度形成硅化钴触点，以避免寄生串联电阻，从而便于可靠的器件缩放。

17. 发明授权

US06169005A Formation of junctions by diffusion from a doped amorphous silicon film during silicidation 有权
标题翻译：在硅化过程中由掺杂的非晶硅膜扩散形成接合点
公开(公告)号：US06169005A
公开(公告)日：2001-01-02
申请号：US09318824
申请日：1999-05-26
申请人： Nick Kepler , Karsten Wieczorek , Larry Wang , Paul Raymond Besser
发明人： Nick Kepler , Karsten Wieczorek , Larry Wang , Paul Raymond Besser
IPC分类号： H01L21386
CPC分类号： H01L21/28518 , H01L21/2257 , H01L21/76895 , H01L29/665
摘要： High integrity ultra-shallow source/drain junctions are formed employing cobalt silicide contacts. These are formed by depositing a layer of cobalt on a substrate above intended source/drain regions, and depositing a doped amorphous silicon film on the cobalt. Silicidation, as by rapid thermal annealing, is performed to form a low-resistance cobalt suicide while consuming the amorphous silicon film and diffusing impurities from the doped amorphous silicon film through the cobalt silicide into the substrate. The diffusion of the impurities forms shallow junctions extending into the substrate a substantially constant depth below the cobalt silicide/silicon substrate interface. The consumption of the amorphous silicon film during silicidation, which results in less consumption of substrate silicon, and formation of source/drain junctions self-aligned to the cobalt silicide/silicon substrate interface, enables the formation of ultra-shallow source/drain junctions without junction leakage while allowing the formation of cobalt silicide contacts at optimum thickness, thereby facilitating reliable device scaling.
摘要翻译：使用硅化钴接触形成高完整性超浅源极/漏极结。这些是通过在目标源极/漏极区域上的衬底上沉积钴层而在钴上沉积掺杂的非晶硅膜形成的。通过快速热退火进行硅化，以形成低电阻的硅化钴，同时消耗非晶硅膜并将杂质从掺杂的非晶硅膜通过硅化钴扩散到衬底中。杂质的扩散形成延伸到衬底中的浅结，在硅化钴/硅衬底界面下方基本上恒定的深度。在硅化期间，非晶硅膜的消耗导致较少的衬底硅消耗，以及与硅化钴/硅衬底界面自对准的源极/漏极结的形成使得能够形成超浅源极/漏极结而不形成结点泄漏，同时允许以最佳厚度形成钴硅化物触点，从而便于可靠的器件缩放。

18. 发明授权

US06380040B1 Prevention of dopant out-diffusion during silicidation and junction formation 有权
标题翻译：在硅化和结形成期间防止掺杂剂扩散
公开(公告)号：US06380040B1
公开(公告)日：2002-04-30
申请号：US09629883
申请日：2000-08-01
申请人： Nick Kepler , Karsten Wieczorek , Larry Wang , Paul R. Besser
发明人： Nick Kepler , Karsten Wieczorek , Larry Wang , Paul R. Besser
IPC分类号： H01L21386
CPC分类号： H01L29/665 , H01L21/28052 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L21/823878
摘要： High integrity cobalt silicide contacts are formed with shallow source/drain junctions. Embodiments include depositing a layer of cobalt on a substrate above intended source/drain regions, followed by silicidation and diffusing impurities from a doped film during or after silicidation in an environment which discourages out-diffusion of the impurities to the environment. The resulting source/drain junctions are self-aligned to the cobalt silicide/silicon substrate interface, thereby preventing junction leakage while advantageously enabling forming the cobalt silicide contacts at optimum thickness to avoid parasitic series resistances. The formation of self-aligned source/drain junctions to the cobalt silicide/silicon substrate interface facilitates reliable device scaling, while the avoidance of unwanted diffusion of impurities to the environment assures adequate doping of the source/drain regions.
摘要翻译：高完整性的硅化钴触点形成有浅的源极/漏极结。实施例包括在期望的源极/漏极区域上方的衬底上沉积钴层，随后在阻止杂质向环境的扩散的环境中硅化处理期间或之后从掺杂膜上硅化并扩散杂质。所得的源极/漏极结与钴硅化物/硅衬底界面自对准，从而防止结漏电，同时有利地使钴硅化物触点形成最佳厚度以避免寄生串联电阻。对硅化钴/硅衬底界面的自对准源极/漏极结的形成有利于可靠的器件缩放，同时避免杂质向环境的不期望的扩散确保了源极/漏极区域的充分掺杂。

19. 发明授权

US6162689A Multi-depth junction formation tailored to silicide formation 有权
标题翻译：针对硅化物形成的多层结形成
公开(公告)号：US6162689A
公开(公告)日：2000-12-19
申请号：US187231
申请日：1998-11-06
申请人： Nick Kepler , Karsten Wieczorek , Larry Wang , Paul Raymond Besser
发明人： Nick Kepler , Karsten Wieczorek , Larry Wang , Paul Raymond Besser
IPC分类号： H01L21/266 , H01L21/285 , H01L21/336 , H01L29/417
CPC分类号： H01L29/66598 , H01L21/266 , H01L21/28518 , H01L29/41775 , H01L29/665 , H01L29/6656 , H01L29/6659
摘要： High integrity ultra-shallow source/drain junctions are formed employing cobalt silicide contacts. Emdodiments include forming field oxide regions, gates, spacers, and lightly doped implants, and then depositing a layer of oxide on a substrate. The oxide layer is masked to protect portions of the oxide layer located near the gate, where it is desired to have a shallow junction, then etched to expose portions of the intended source/drain regions where the silicided contacts are to be formed. A high-dosage source/drain implant is thereafter carried out to form deep source/drain junctions with the substrate where the oxide layer has been etched away, and to form shallower junctions near the gates, where the implant must travel through the oxide layer before reaching the substrate. A layer of cobalt is thereafter deposited and silicidation is performed to form metal silicide contacts over only the deep source/drain junctions, while the cobalt on the oxide layer (i.e., above the shallower junctions) does not react to form cobalt silicide, and is thereafter removed. The present invention provides ultra-shallow source-drain junctions near the gates for improved electrical characteristics, and deeper junctions away from the gates, with cobalt silicide contacts above only the deeper junction portions to avoid junction leakage, thereby facilitating reliable device scaling.
摘要翻译：使用硅化钴接触形成高完整性超浅源极/漏极结。实例包括形成场氧化物区域，栅极，间隔物和轻掺杂的植入物，然后在衬底上沉积氧化物层。掩模氧化层以保护位于栅极附近的氧化物层的部分，期望具有浅结，然后蚀刻以暴露要形成硅化物触点的预期源/漏区的部分。此后，进行高剂量源/漏注入，以与氧化物层被蚀刻掉的衬底形成深的源极/漏极结，并且在栅极附近形成较浅的结，其中植入物必须在到达基板。此后沉积一层钴，并且仅在深源极/漏极接合处进行硅化以形成金属硅化物接触，而氧化物层上的钴（即，较浅的接合点上方）不反应形成硅化钴，并且是此后取出。本发明提供了栅极附近的超浅源极 - 漏极结，用于改善电气特性，以及远离栅极的较深的结，钴硅化物接触仅在较深的接合部分上方，以避免结漏电，从而便于可靠的器件缩放。

20. 发明授权

US6096599A Formation of junctions by diffusion from a doped film into and through a silicide during silicidation 有权
标题翻译：在硅化过程中，从掺杂膜扩散到硅化物中并通过硅化物形成结
公开(公告)号：US6096599A
公开(公告)日：2000-08-01
申请号：US187521
申请日：1998-11-06
申请人： Nick Kepler , Karsten Wieczorek , Larry Wang , Paul Raymond Besser
发明人： Nick Kepler , Karsten Wieczorek , Larry Wang , Paul Raymond Besser
IPC分类号： H01L21/225 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/8238 , H01L21/8242
CPC分类号： H01L29/66575 , H01L21/2257 , H01L21/28052 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L29/665 , Y10S438/923
摘要： High integrity shallow source/drain junctions are formed employing cobalt silicide contacts. Embodiments include depositing a layer of cobalt on a substrate above intended source/drain regions, depositing a cap layer of titanium or titanium nitride on the cobalt, depositing a doped film on the cap layer, and performing silicidation, as by rapid thermal annealing, to form a low-resistivity cobalt silicide and to diffuse impurities from the doped film through the cobalt silicide into the substrate to form a junction extending into the substrate a constant depth below the cobalt silicide interface. The formation of source/drain junctions self-aligned to the cobalt silicide/silicon interface prevents junction leakage while allowing the formation of cobalt silicide contacts at optimum thickness, thereby facilitating reliable device scaling.
摘要翻译：使用硅化钴接触形成高度完整的浅源极/漏极结。实施例包括在目标源极/漏极区域上的衬底上沉积钴层，在钴上沉积钛或氮化钛的覆盖层，在覆盖层上沉积掺杂的膜，并通过快速热退火进行硅化，形成低电阻率的硅化钴，并且通过硅化钴将掺杂的膜中的杂质扩散到衬底中，以形成在硅化钴界面下面延伸到衬底中的恒定深度的结。与硅化钴/硅界面自对准的源极/漏极结的形成防止结漏，同时允许在最佳厚度下形成硅化钴触点，从而便于可靠的器件缩放。

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