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11. 发明申请

US20120281475A1 NAND FLASH MEMORY DEVICE AND METHOD OF MAKING SAME 有权
标题翻译： NAND闪存存储器件及其制造方法
公开(公告)号：US20120281475A1
公开(公告)日：2012-11-08
申请号：US13553242
申请日：2012-07-19
申请人： Dong-Yean Oh , Woon-Kyung Lee , Seung-Chul Lee
发明人： Dong-Yean Oh , Woon-Kyung Lee , Seung-Chul Lee
IPC分类号： G11C16/06
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3454
摘要： An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.
摘要翻译：集成电路包括一个包括串选择晶体管SST的NAND串和设置在串联存储单元MC的任一端的接地选择晶体管GST。每个存储器存储单元是具有浮置栅极的存储晶体管，并且串选择晶体管SST和接地选择晶体管GST中的至少一个是具有浮置栅极的存储晶体管。可编程串选择晶体管SST和接地选择晶体管GST的阈值电压Vth是可变的并且用户可控，并且不需要在制造期间通过注入建立。存储器块中的每个可编程串选择晶体管SST和接地选择晶体管GST可用于存储随机数据，从而增加闪存器件的存储器存储容量。

12. 发明授权

US08243518B2 NAND flash memory device and method of making same 有权
标题翻译： NAND闪存器件及其制作方法
公开(公告)号：US08243518B2
公开(公告)日：2012-08-14
申请号：US12424135
申请日：2009-04-15
申请人： Dong-Yean Oh , Woon-Kyung Lee , Seung-Chul Lee
发明人： Dong-Yean Oh , Woon-Kyung Lee , Seung-Chul Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3454
摘要： An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.
摘要翻译：集成电路包括一个包括串选择晶体管SST的NAND串和设置在串联存储单元MC的任一端的接地选择晶体管GST。每个存储器存储单元是具有浮置栅极的存储晶体管，并且串选择晶体管SST和接地选择晶体管GST中的至少一个是具有浮置栅极的存储晶体管。可编程串选择晶体管SST和接地选择晶体管GST的阈值电压Vth是可变的并且用户可控，并且不需要在制造期间通过注入建立。存储器块中的每个可编程串选择晶体管SST和接地选择晶体管GST可用于存储随机数据，从而增加闪存器件的存储器存储容量。

13. 发明申请

US20100020617A1 NONVOLATILE SEMICONDUCTOR DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权
标题翻译：非线性半导体器件和包括其的存储器系统
公开(公告)号：US20100020617A1
公开(公告)日：2010-01-28
申请号：US12480352
申请日：2009-06-08
申请人： Dong-Yean Oh , Woon-Kyung Lee
发明人： Dong-Yean Oh , Woon-Kyung Lee
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/3454 , G11C16/0483 , G11C16/10 , H01L27/11551 , H01L27/11556
摘要： A nonvolatile semiconductor memory device including a vertical array structure comprised of bit lines and source lines arranged in the same direction as the bit lines, each source lines corresponding to the bit lines and memory cell strings vertically formed between each pair of the bit lines and source lines. Multiple strings of memory cells can be stacked in the vertical direction, and adjacent memory cell strings may share bit line or source line.
摘要翻译：一种非易失性半导体存储器件，包括垂直阵列结构，其包括与位线相同方向布置的位线和源极线，每个源极线对应于在每对位线和源极之间垂直形成的位线和存储单元串线条。多个存储单元串可以在垂直方向堆叠，并且相邻的存储单元串可以共享位线或源极线。

14. 发明申请

US20090287879A1 NAND FLASH MEMORY DEVICE AND METHOD OF MAKING SAME 有权
标题翻译： NAND闪存存储器件及其制造方法
公开(公告)号：US20090287879A1
公开(公告)日：2009-11-19
申请号：US12424135
申请日：2009-04-15
申请人： Dong-Yean Oh , Woon-Kyung Lee , Seung-Chul Lee
发明人： Dong-Yean Oh , Woon-Kyung Lee , Seung-Chul Lee
IPC分类号： G06F12/00 , G11C16/04 , G11C16/06 , G06F12/02
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3454
摘要： An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.
摘要翻译：集成电路包括一个包括串选择晶体管SST的NAND串和设置在串联存储单元MC的任一端的接地选择晶体管GST。每个存储器存储单元是具有浮置栅极的存储晶体管，并且串选择晶体管SST和接地选择晶体管GST中的至少一个是具有浮置栅极的存储晶体管。可编程串选择晶体管SST和接地选择晶体管GST的阈值电压Vth是可变的并且用户可控，并且不需要在制造期间通过注入建立。存储器块中的每个可编程串选择晶体管SST和接地选择晶体管GST可用于存储随机数据，从而增加闪存器件的存储器存储容量。

15. 发明授权

US07851304B2 Nonvolatile memory device and fabrication method 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US07851304B2
公开(公告)日：2010-12-14
申请号：US11641869
申请日：2006-12-20
申请人： Woon-Kyung Lee , Jeong-Hyuk Choi
发明人： Woon-Kyung Lee , Jeong-Hyuk Choi
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , Y10S438/981
摘要： Provided is a nonvolatile memory device and a fabrication method. The nonvolatile memory device includes an active region defined in a semiconductor substrate, a gate insulating layer formed on the active region and a plurality of gate patterns formed on the gate insulating layer, and crossing over the active region. The gate insulating layer includes a discharge region in a predetermined portion between the gate patterns, the discharge region having a lesser thickness than that of the gate insulating layer under the gate pattern, because a thickness portion of the gate insulating layer is removed to form the discharge region.
摘要翻译：提供了一种非易失性存储器件和制造方法。非易失性存储器件包括限定在半导体衬底中的有源区，形成在有源区上的栅极绝缘层和形成在栅极绝缘层上并跨过有源区的多个栅极图案。栅极绝缘层包括在栅极图案之间的预定部分中的放电区域，由于栅极绝缘层的厚度部分被去除以形成栅极绝缘层的厚度部分，所以放电区域的厚度小于栅极图案下的栅极绝缘层的厚度。放电区域。

16. 发明申请

US20080096350A1 Nonvolatile memory device and fabrication method 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US20080096350A1
公开(公告)日：2008-04-24
申请号：US11641869
申请日：2006-12-20
申请人： Woon-Kyung Lee , Jeong-Hyuk Choi
发明人： Woon-Kyung Lee , Jeong-Hyuk Choi
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524 , Y10S438/981
摘要： Provided is a nonvolatile memory device and a fabrication method. The nonvolatile memory device includes an active region defined in a semiconductor substrate, a gate insulating layer formed on the active region and a plurality of gate patterns formed on the gate insulating layer, and crossing over the active region. The gate insulating layer includes a discharge region in a predetermined portion between the gate patterns, the discharge region having a lesser thickness than that of the gate insulating layer under the gate pattern, because a thickness portion of the gate insulating layer is removed to form the discharge region.
摘要翻译：提供了一种非易失性存储器件和制造方法。非易失性存储器件包括限定在半导体衬底中的有源区，形成在有源区上的栅极绝缘层和形成在栅极绝缘层上并跨过有源区的多个栅极图案。栅极绝缘层包括在栅极图案之间的预定部分中的放电区域，由于栅极绝缘层的厚度部分被去除以形成栅极绝缘层的厚度部分，所以放电区域的厚度小于栅极图案下的栅极绝缘层的厚度。放电区域。

17. 发明申请

US20070001212A1 NAND-type memory devices including recessed source/drain regions and related methods 审中-公开
标题翻译： NAND型存储器件包括凹陷源极/漏极区域和相关方法
公开(公告)号：US20070001212A1
公开(公告)日：2007-01-04
申请号：US11431273
申请日：2006-05-10
申请人： Woon-Kyung Lee , Jeong-Hyuk Choi
发明人： Woon-Kyung Lee , Jeong-Hyuk Choi
IPC分类号： H01L29/788 , H01L21/8238
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A NAND-type memory device may include first and second selection transistors on a semiconductor substrate and a plurality of memory cell transistors coupled in series between the first and second selection transistors. A first source/drain region may be shared between the first selection transistor and a first of the memory cell transistors, and a second source/drain region may be shared between the second selection transistor and a last of the memory cell transistors. Moreover, a portion of at least one of the first and/or second source/drain regions may be recessed relative to a surface of the semiconductor substrate. Related methods are also discussed.
摘要翻译： NAND型存储器件可以包括半导体衬底上的第一和第二选择晶体管和串联耦合在第一和第二选择晶体管之间的多个存储单元晶体管。第一源/漏区可以在第一选择晶体管和第一存储单元晶体管之间共享，并且第二源/漏区可以在第二选择晶体管和最后的存储单元晶体管之间共享。此外，第一和/或第二源极/漏极区域中的至少一个的一部分可以相对于半导体衬底的表面凹陷。还讨论了相关方法。

18. 发明申请

US20130168800A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130168800A1
公开(公告)日：2013-07-04
申请号：US13717803
申请日：2012-12-18
申请人： Jae-Joo Shim , Han-Soo Kim , Woon-Kyung Lee , Ju-Young Lim , Sung-Min Hwang
发明人： Jae-Joo Shim , Han-Soo Kim , Woon-Kyung Lee , Ju-Young Lim , Sung-Min Hwang
IPC分类号： H01L29/06
CPC分类号： H01L29/0657 , H01L27/0207 , H01L27/1157 , H01L27/11582
摘要： Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.
摘要翻译：提供了包括设置在基板上的第一和第二隔离图案的半导体器件。交替层叠的层间绝缘图案和导电图案设置在第一和第二隔离图案之间的基板的表面上。支撑图案穿透导电图案和层间绝缘图案，并且具有比第一和第二隔离图案更小的宽度。第一和第二垂直结构设置在第一隔离和支撑图案之间并且穿透导电图案和层间绝缘图案。第二垂直结构设置在第二隔离图案和支撑图案之间并且穿透导电图案和层间绝缘图案。支撑图案的顶表面和底表面之间的距离大于支撑图案的底表面和基底表面之间的距离。

19. 发明申请

US20080079038A1 Semiconductor devices with gate insulation layers having different thicknesses and methods of forming the same 审中-公开
标题翻译：具有不同厚度的栅绝缘层的半导体器件及其形成方法
公开(公告)号：US20080079038A1
公开(公告)日：2008-04-03
申请号：US11646127
申请日：2006-12-27
申请人： Tae-Kyung Kim , Woon-Kyung Lee
发明人： Tae-Kyung Kim , Woon-Kyung Lee
IPC分类号： H01L29/76
CPC分类号： H01L21/2652 , H01L21/28123 , H01L21/28238 , H01L21/823462 , H01L21/823481 , H01L29/42368
摘要： Methods of forming a semiconductor device include an active region and a shallow trench isolation region in a semiconductor substrate, and forming a gate insulation layer on the active region. The gate insulation layer includes a first part spaced apart from the shallow trench isolation region and a second part adjacent the shallow trench isolation region and disposed between the shallow trench isolation region and the first part, and thicker than the first part. The methods further include forming a first impurity region in the active region of the semiconductor substrate adjacent the first part, and forming a gate line on the gate insulation layer. Corresponding semiconductor devices are also disclosed.
摘要翻译：形成半导体器件的方法包括半导体衬底中的有源区和浅沟槽隔离区，并且在有源区上形成栅极绝缘层。栅极绝缘层包括与浅沟槽隔离区域间隔开的第一部分和与浅沟槽隔离区域相邻并且设置在浅沟槽隔离区域和第一部分之间并且比第一部分更厚的第二部分。所述方法还包括在所述半导体衬底的与所述第一部分相邻的有源区中形成第一杂质区，以及在所述栅极绝缘层上形成栅极线。还公开了相应的半导体器件。

20. 发明申请

US20060231885A1 Semiconductor device and method of fabricating the same 有权
公开(公告)号：US20060231885A1
公开(公告)日：2006-10-19
申请号：US11455888
申请日：2006-06-20
申请人： Woon-Kyung Lee
发明人： Woon-Kyung Lee
IPC分类号： H01L29/76 , H01L29/00
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11534 , H01L27/11568
摘要： The present invention provides a semiconductor device in which the gate is self-aligned to the device isolation film and a fabricating method thereof. A device isolation film restricting an active region is disposed on a portion of a semiconductor substrate, and a word line is across over the device isolation film. A gate pattern is disposed between the word line and the active region, and a tunnel oxide film is disposed between the gate pattern and the active region. The gate pattern comprises a floating gate pattern, a gate interlayer dielectric film pattern and a control gate electrode pattern deposited in the respective order, and has a sidewall self-aligned to the device isolation film. To form the gate pattern having the sidewall self-aligned to the device isolation film, a gate insulation film and a gate material film are formed in the respective order on the semiconductor substrate.

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