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11. 发明授权

US08981536B1 Semiconductor structure 有权
标题翻译：半导体结构
公开(公告)号：US08981536B1
公开(公告)日：2015-03-17
申请号：US14048078
申请日：2013-10-08
申请人： Chipbond Technology Corporation
发明人： Chin-Tang Hsieh , You-Ming Hsu , Ming-Sheng Liu , Chih-Ping Wang
IPC分类号： H01L29/06 , H01L23/58 , H01L23/495 , H01L23/00 , H01L29/02
CPC分类号： H01L23/562 , H01L23/31 , H01L23/3192 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. The second protective layer reveals the first anti-stress zone and comprises a second surface, a first lateral side, a second lateral side and a first connection side. The second surface comprises a second anti-stress zone. An extension line of the first lateral side intersects with an extension line of the second lateral side to form a first intersection point. A zone formed by connecting the first intersection point and two points of the first connection side is the first anti-stress zone. The third protective layer reveals the second anti-stress zone and comprises a second connection side projected on the first surface to form a projection line parallel to the first connection side.
摘要翻译：半导体结构包括载体，第一保护层，第二保护层和第三保护层。第一保护层的第一表面包括第一抗应力区。第二保护层揭示第一抗应力区，并包括第二表面，第一横向侧，第二横向侧和第一连接侧。第二表面包括第二抗应力区。第一侧面的延伸线与第二侧面的延伸线相交形成第一交点。通过连接第一交点和第一连接侧的两个点形成的区域是第一抗应力区域。第三保护层显示第二抗应力区域，并且包括突出在第一表面上的第二连接侧，以形成平行于第一连接侧的突出线。

12. 发明申请

US20150069584A1 SEMICONDUCTOR STRUCTURE 有权
标题翻译：半导体结构
公开(公告)号：US20150069584A1
公开(公告)日：2015-03-12
申请号：US14042976
申请日：2013-10-01
申请人： Chipbond Technology Corporation
发明人： Chin-Tang Hsieh , You-Ming Hsu , Ming-Sheng Liu , Chih-Ping Wang
IPC分类号： H01L23/00
CPC分类号： H01L23/562 , H01L23/28 , H01L23/3192 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. A first extension line from a first bottom edge intersects with a second extension line from a second bottom edge to form a first base point. A first projection line is formed on the first surface, an extension line of the first projection line intersects with the second bottom edge to form a first intersection point, a second projection line is formed on the first surface, and an extension line of the second projection line intersects with the first bottom edge to form a second intersection point. A zone by connecting the first base point, the first intersection point and the second intersection point is the first anti-stress zone.
摘要翻译：半导体结构包括载体，第一保护层，第二保护层和第三保护层。第一保护层的第一表面包括第一抗应力区。来自第一底部边缘的第一延伸线与第二延伸线从第二底部边缘相交以形成第一基点。第一投影线形成在第一表面上，第一投影线的延长线与第二底边缘相交形成第一交点，第二投影线形成在第一表面上，第二投影线形成在第二表面的延伸线上投影线与第一底边相交形成第二交点。通过连接第一基点，第一交点和第二交点的区域是第一抗应力区域。

13. 发明申请

US20130213702A1 BUMPING PROCESS AND STRUCTURE THEREOF 有权
标题翻译：保鲜工艺及其结构
公开(公告)号：US20130213702A1
公开(公告)日：2013-08-22
申请号：US13852663
申请日：2013-03-28
申请人： Chipbond Technology Corporation
发明人： Chin-Tang Hsieh , Chih-Ming Kuo
IPC分类号： H05K1/11
CPC分类号： H05K1/111 , H01L21/4846 , H01L23/3192 , H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0347 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/05147 , H01L2224/05541 , H01L2224/05547 , H01L2224/05556 , H01L2224/05557 , H01L2224/05565 , H01L2224/05567 , H01L2224/05578 , H01L2224/05583 , H01L2224/05647 , H01L2224/05655 , H01L2224/05687 , H01L2224/1147 , H01L2224/11912 , H01L2224/13005 , H01L2224/13006 , H01L2224/13017 , H01L2224/13018 , H01L2224/13022 , H01L2224/13083 , H01L2224/13147 , H01L2224/13155 , H01L2224/13565 , H01L2224/13687 , H01L2924/00014 , H01L2924/301 , H01L2924/384 , Y10T428/12396 , H01L2924/00012 , H01L2924/05042 , H01L2924/05442 , H01L2924/058 , H01L2224/05552
摘要： A bumping process comprises steps of forming a metal layer with copper on a substrate, and the metal layer with copper comprises a plurality of first zones and second zones; forming a photoresist layer on the metal layer with copper; patterning the photoresist layer to form a plurality of openings; forming a plurality of copper bumps within the openings, each of the copper bumps covers the first zones and comprises a first top surface; forming a connection layer on the first top surface; removing the photoresist layer; removing the second zones and enabling each of the first zones to form an under bump metallurgy layer, wherein the under bump metallurgy layer, the copper bump, and the connection layer possess their corresponded peripheral walls, and covering sections of a first protective layer formed on the connection layer may cover those peripheral walls to prevent ionization phenomenon.
摘要翻译：凸起工艺包括在基底上形成具有铜的金属层的步骤，并且具有铜的金属层包括多个第一区域和第二区域; 用铜在金属层上形成光致抗蚀剂层; 图案化光致抗蚀剂层以形成多个开口; 在所述开口内形成多个铜凸块，每个所述铜凸块覆盖所述第一区域并且包括第一顶表面; 在所述第一顶表面上形成连接层; 去除光致抗蚀剂层; 去除所述第二区域并且使得所述第一区域中的每一个形成凸起下冶金层，其中所述凸起下的冶金层，所述铜凸块和所述连接层具有其对应的周壁，以及覆盖在第一区上形成的第一保护层的覆盖部分连接层可以覆盖那些外围壁以防止电离现象。

14. 发明申请

US20200091385A1 CHIP PACKAGE AND CHIP THEREOF 审中-公开
公开(公告)号：US20200091385A1
公开(公告)日：2020-03-19
申请号：US16260528
申请日：2019-01-29
申请人： CHIPBOND TECHNOLOGY CORPORATION
发明人： Chin-Tang Hsieh , Cheng-Hung Shih
IPC分类号： H01L33/62 , H01L33/38
摘要： A microchip is electrically connected to a substrate to become a chip package, preferably for LED. A chip of the package includes a body and at least one electrode which is disposed and exposed on a surface of the body. The electrode includes a confining groove and a confining wall. The confining wall is peripherally located around the confining groove and provided to confine at least one conductive particle of an adhesive in the confining groove. The electrode of the chip is electrically connected to a bonding pad of a substrate via the conductive particle confined in the confining groove.

15. 发明授权

US10504828B2 Semiconductor package and circuit substrate thereof 有权
公开(公告)号：US10504828B2
公开(公告)日：2019-12-10
申请号：US15990747
申请日：2018-05-28
申请人： CHIPBOND TECHNOLOGY CORPORATION
发明人： Chin-Tang Hsieh
IPC分类号： H01L23/498 , H01L23/31 , H01L23/00 , H01L21/48
CPC分类号： H01L23/49838 , H01L23/3185 , H01L24/16 , H01L21/4846 , H01L2224/16238
摘要： A semiconductor package includes a chip and a circuit substrate having leads. Each of the leads has an upper wide portion and a lower wide portion in a bonding area so as there are an upper notch and a lower notch in the bonding area. The upper and lower notches face toward the upper and lower wide portions of the adjacent lead, respectively. The upper and lower wide portions are designed to prevent defective bonding caused by shifting between the leads and the chip humps. Additionally, there are adequate etching spaces between the leads because the wide portions and the notches are staggered with each other such that incomplete etching between the leads is preventable during etching process.

16. 发明授权

US10340216B1 Semiconductor package and circuit substrate thereof 有权
公开(公告)号：US10340216B1
公开(公告)日：2019-07-02
申请号：US15990747
申请日：2018-05-28
申请人： CHIPBOND TECHNOLOGY CORPORATION
发明人： Chin-Tang Hsieh
IPC分类号： H01L23/498 , H01L23/31 , H01L23/00 , H01L23/14 , H01L23/12 , H01L25/00 , H01L21/48
摘要： A semiconductor package includes a chip and a circuit substrate having leads. Each of the leads has an upper wide portion and a lower wide portion in a bonding area so as there are an upper notch and a lower notch in the bonding area. The upper and lower notches face toward the upper and lower wide portions of the adjacent lead, respectively. The upper and lower wide portions are designed to prevent defective bonding caused by shifting between the leads and the chip humps. Additionally, there are adequate etching spaces between the leads because the wide portions and the notches are staggered with each other such that incomplete etching between the leads is preventable during etching process.

17. 发明授权

US09510441B2 Flexible substrate 有权
标题翻译：柔性基材
公开(公告)号：US09510441B2
公开(公告)日：2016-11-29
申请号：US14642945
申请日：2015-03-10
申请人： CHIPBOND TECHNOLOGY CORPORATION
发明人： Chin-Tang Hsieh , Fei-Jain Wu , Chia-Jung Tu
IPC分类号： H05K1/00 , H05K1/02 , H05K1/03
CPC分类号： H05K1/0209 , H05K1/0203 , H05K1/028 , H05K1/0346 , H05K1/0393 , H05K1/189 , H05K2201/0154 , H05K2201/066 , H05K2201/068
摘要： A flexible substrate includes a circuit board, a flexible heat-dissipating structure and an adhesive. The circuit board has a substrate and a circuit layer formed on a top surface of the substrate, and the flexible heat-dissipating structure has a flexible supporting plate and a flexible heat-dissipating metal layer formed on a surface of the flexible supporting plate. The flexible heat-dissipating metal layer of the flexible heat-dissipating structure is connected with a bottom surface of the substrate by the adhesive. The circuit layer and the flexible heat-dissipating metal layer are made of same material.
摘要翻译：柔性基板包括电路板，柔性散热结构和粘合剂。电路基板具有形成在基板顶面的基板和电路层，柔性散热结构具有柔性支撑板和形成在柔性支撑板的表面上的柔性散热金属层。柔性散热结构的柔性散热金属层通过粘合剂与基板的底面连接。电路层和柔性散热金属层由相同的材料制成。

18. 发明授权

US09159660B2 Semiconductor package structure and method for making the same 有权
标题翻译：半导体封装结构及其制造方法
公开(公告)号：US09159660B2
公开(公告)日：2015-10-13
申请号：US14042979
申请日：2013-10-01
申请人： CHIPBOND TECHNOLOGY CORPORATION
发明人： Chin-Tang Hsieh , Chih-Ming Kuo , Chia-Jung Tu , Shih-Chieh Chang , Chih-Hsien Ni , Lung-Hua Ho , Chaun-Yu Wu , Kung-An Lin
IPC分类号： H01L23/498 , H01L23/31 , H01L21/56 , H01L23/00 , H01L25/065 , H01L21/48
CPC分类号： H01L23/49811 , H01L21/4846 , H01L21/563 , H01L23/3128 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2224/1147 , H01L2224/11472 , H01L2224/11831 , H01L2224/11903 , H01L2224/11906 , H01L2224/13011 , H01L2224/13017 , H01L2224/13019 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16058 , H01L2224/8114 , H01L2224/81193 , H01L2224/81345 , H01L2225/06513 , H01L2225/06565 , H01L2924/00014 , H01L2924/014
摘要： A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.
摘要翻译：半导体封装结构包括第一衬底，第二衬底和密封剂。第一基板包括多个第一凸块和多个第一焊料层。每个第一焊料层形成在每个第一凸块上，并且包括具有内表面的锥形槽。第二基板包括多个第二凸块和多个第二焊料层。每个第二焊料层形成在每个第二凸块上并且包括外表面。每个第二焊料层是锥形体。第二焊料层耦合到第一焊料层并且容纳在第一焊料层内。锥形槽的内表面与第二焊料层的外表面接触。密封剂形成在第一基板和第二基板之间。

19. 发明申请

US20140141606A1 SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE THEREOF 有权
标题翻译：半导体制造方法及其半导体结构
公开(公告)号：US20140141606A1
公开(公告)日：2014-05-22
申请号：US14164628
申请日：2014-01-27
申请人： Chipbond Technology Corporation
发明人： Chih-Ming Kuo , Lung-Hua Ho , Shih-Chieh Chang , Chia-Yeh Huang , Chin-Tang Hsieh
IPC分类号： H01L21/768
CPC分类号： H01L21/76885 , H01L21/4853 , H01L23/48 , H01L23/49811 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05568 , H01L2224/05644 , H01L2224/05647 , H01L2224/1147 , H01L2224/11849 , H01L2224/11903 , H01L2224/13006 , H01L2224/13016 , H01L2224/13023 , H01L2224/13076 , H01L2224/13082 , H01L2224/13083 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552
摘要： A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.
摘要翻译：半导体制造方法包括提供载体; 形成第一光致抗蚀剂层; 形成多个芯部; 去除第一光致抗蚀剂层; 形成第二光致抗蚀剂层; 形成多个连接部分，所述多个连接部分中的每一个包括第一连接层和第二连接层，并且连接到每个所述芯部分以形成混合凸块，其中每个所述第一连接层包括基部，突出部分和容纳空间，每个基部包括上表面，每个突出部分突出到上表面并且位于每个芯部的顶部，每个容纳空间位于每个突出部分的外侧，第二连接层覆盖突出部分和上表面，并且容纳空间被第二连接层填充; 去除第二光致抗蚀剂层以露出混合凸块。

20. 发明申请

US20140027905A1 SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MAKING THE SAME 审中-公开
标题翻译：半导体封装结构及其制造方法
公开(公告)号：US20140027905A1
公开(公告)日：2014-01-30
申请号：US14042979
申请日：2013-10-01
申请人： CHIPBOND TECHNOLOGY CORPORATION
发明人： Chin-Tang Hsieh , Chih-Ming Kuo , Chia-Jung Tu , Shih-Chieh Chang , Chih-Hsien Ni , Lung-Hua Ho , Chaun-Yu Wu , Kung-An Lin
IPC分类号： H01L23/498
CPC分类号： H01L23/49811 , H01L21/4846 , H01L21/563 , H01L23/3128 , H01L23/49816 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L2224/1147 , H01L2224/11472 , H01L2224/11831 , H01L2224/11903 , H01L2224/11906 , H01L2224/13011 , H01L2224/13017 , H01L2224/13019 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16058 , H01L2224/8114 , H01L2224/81193 , H01L2224/81345 , H01L2225/06513 , H01L2225/06565 , H01L2924/00014 , H01L2924/014
摘要： A semiconductor package structure includes a first substrate, a second substrate and an encapsulant. The first substrate comprises a plurality of first bumps and a plurality of first solder layers. Each of the first solder layers is formed on each of the first bumps and comprises a cone-shaped slot having an inner surface. The second substrate comprises a plurality of second bumps and a plurality of second solder layers. Each of the second solder layers is formed on each of the second bumps and comprises an outer surface. Each of the second solder layers is a cone-shaped body. The second solder layer couples to the first solder layer and is accommodated within the first solder layer. The inner surface of the cone-shaped slot contacts with the outer surface of the second solder layer. The encapsulant is formed between the first substrate and the second substrate.
摘要翻译：半导体封装结构包括第一衬底，第二衬底和密封剂。第一基板包括多个第一凸块和多个第一焊料层。每个第一焊料层形成在每个第一凸块上，并且包括具有内表面的锥形槽。第二基板包括多个第二凸块和多个第二焊料层。每个第二焊料层形成在每个第二凸块上并且包括外表面。每个第二焊料层是锥形体。第二焊料层耦合到第一焊料层并且容纳在第一焊料层内。锥形槽的内表面与第二焊料层的外表面接触。密封剂形成在第一基板和第二基板之间。

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