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1. 发明公开

US20240194646A1 SEMICONDUCTOR PACKAGE 审中-公开
公开(公告)号：US20240194646A1
公开(公告)日：2024-06-13
申请号：US18374725
申请日：2023-09-29
申请人： CHIPBOND TECHNOLOGY CORPORATION
发明人： Chin-Tang Hsieh , Lung-Hua Ho , Chih-Ming Kuo , Chen-Yu Wang , Chih-Hao Chiang , Pai-Sheng Cheng , Kung-An Lin , Chun-Ting Kuo , Yu-Hui Hu , Wen-Cheng Hsu
IPC分类号： H01L25/065 , H01L23/00 , H01L23/31 , H01L23/498 , H01L23/552
CPC分类号： H01L25/0657 , H01L23/3107 , H01L23/49822 , H01L23/552 , H01L24/13 , H01L24/16 , H01L25/0652 , H01L2224/13541 , H01L2224/16227 , H01L2224/16238 , H01L2225/06517 , H01L2924/3511
摘要： A semiconductor package includes a substrate, first bumps, a first chip, metal pillars, second bumps and a second chip. The substrate includes first and second conductive pads which are located on a top surface of the substrate. Both ends of the first bumps are connected to the first conductive pads and the first chip, respectively. Both ends of the metal pillars are connected to the second conductive pads and one end of the second bumps, respectively. A cross-sectional area of each of the metal pillars is larger than that of each of the second bumps. The second chip is connected to the other end of the second bumps and located above the first chip.

2. 发明申请

US20190252207A1 SEMICONDUCTOR SUBSTRATE AND PROCESSING METHOD THEREOF 审中-公开
公开(公告)号：US20190252207A1
公开(公告)日：2019-08-15
申请号：US15960707
申请日：2018-04-24
申请人： CHIPBOND TECHNOLOGY CORPORATION
发明人： Chin-Tang Hsieh
IPC分类号： H01L21/48 , H01L23/498 , H01L21/66
CPC分类号： H01L21/481 , H01L22/20 , H01L23/145 , H01L23/49838 , H01L23/4985
摘要： A semiconductor substrate includes a carrier and leads formed on the carrier, and a space exists between the adjacent leads and reveals a surface of the carrier. A processing method of the semiconductor substrate uses a laser beam passing through the space to etch the carrier such that there are ditches recessed on the carrier. The ditches can increase fluidity of coating fluid, such as underfill, ACF and solder resist. Furthermore, during etching the carrier, the laser beam also can remove residues remained between the leads to improve yield of the semiconductor substrate.

3. 发明授权

US09653376B1 Heat dissipation package structure 有权
公开(公告)号：US09653376B1
公开(公告)日：2017-05-16
申请号：US15162758
申请日：2016-05-24
申请人： CHIPBOND TECHNOLOGY CORPORATION
发明人： Chin-Tang Hsieh
IPC分类号： H01L23/10 , H01L23/34 , H01L23/367 , H01L23/373 , H01L23/00
CPC分类号： H01L23/3675 , H01L23/3736 , H01L23/562 , H01L24/16 , H01L24/32 , H01L24/73 , H01L2224/16238 , H01L2224/26175 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/16251 , H01L2924/3511
摘要： A heat dissipation package structure includes a substrate, a chip disposed on the substrate and a heat dissipation sheet. The heat dissipation sheet comprises a covering portion disposed on a back surface of the chip, a first lateral covering portion disposed on a first lateral surface of the chip and a first conducting portion disposed on the substrate. The back surface comprises a first width, the covering portion comprises a second width, the chip comprises a thickness, and there is an interval between the chip and the substrate. The second width is not larger than summation of the first width, double the interval and double the thickness for making the chip disposed between the heat dissipation sheet and the substrate is not within a completely sealed space so as to prevent the heat dissipation sheet from deformation and separation from the chip or the substrate cause of air expansion.

4. 发明授权

US08823169B2 Semiconductor manufacturing method and semiconductor structure thereof 有权
标题翻译：半导体制造方法及其半导体结构
公开(公告)号：US08823169B2
公开(公告)日：2014-09-02
申请号：US13644749
申请日：2012-10-04
申请人： Chipbond Technology Corporation
发明人： Chih-Ming Kuo , Lung-Hua Ho , Shih-Chieh Chang , Chia-Yeh Huang , Chin-Tang Hsieh
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/76885 , H01L21/4853 , H01L23/48 , H01L23/49811 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05568 , H01L2224/05644 , H01L2224/05647 , H01L2224/1147 , H01L2224/11849 , H01L2224/11903 , H01L2224/13006 , H01L2224/13016 , H01L2224/13023 , H01L2224/13076 , H01L2224/13082 , H01L2224/13083 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552
摘要： A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.
摘要翻译：半导体制造方法包括提供载体; 形成第一光致抗蚀剂层; 形成多个芯部; 去除第一光致抗蚀剂层; 形成第二光致抗蚀剂层; 形成多个连接部分，所述多个连接部分中的每一个包括第一连接层和第二连接层，并且连接到每个所述芯部分以形成混合凸块，其中每个所述第一连接层包括基部，突出部分和容纳空间，每个基部包括上表面，每个突出部分突出到上表面并且位于每个芯部的顶部，每个容纳空间位于每个突出部分的外侧，第二连接层覆盖突出部分和上表面，并且容纳空间被第二连接层填充; 去除第二光致抗蚀剂层以露出混合凸块。

5. 发明授权

US08796824B1 Semiconductor structure 有权
标题翻译：半导体结构
公开(公告)号：US08796824B1
公开(公告)日：2014-08-05
申请号：US14014568
申请日：2013-08-30
申请人： Chipbond Technology Corporation
发明人： Chin-Tang Hsieh , Shyh-Jen Guo , You-Ming Hsu
IPC分类号： H01L23/58 , H01L29/06 , H01L23/00 , H01L23/28 , H01L23/532
CPC分类号： H01L23/562 , H01L23/28 , H01L23/3192 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure having a first corner includes a carrier, a first protective layer, a second protective layer, and a third protective layer. The carrier comprises a carrier surface having a protection-layered disposing zone. The first protective layer comprises a first surface having a first disposing zone, a first anti-stress zone and a first exposing zone, the first anti-stress zone is located at a corner of the first disposing zone, the second protective layer is disposed at the first disposing zone. The second protective layer comprises a second surface having a second disposing zone, a second anti-stress zone and a second exposing zone, the second anti-stress zone is located at a corner of the second disposing zone. The first anti-stress zone and the second anti-stress zone are located at the first corner. An area of the first anti-stress zone is not smaller than that of the second anti-stress zone.
摘要翻译：具有第一角的半导体结构包括载体，第一保护层，第二保护层和第三保护层。载体包括具有保护层叠布置区的载体表面。第一保护层包括具有第一布置区，第一抗应力区和第一曝光区的第一表面，第一抗应力区位于第一布置区的拐角处，第二保护层设置在第一个处置区。第二保护层包括具有第二设置区，第二抗应力区和第二曝光区的第二表面，第二抗应力区位于第二处置区的拐角处。第一个抗应力区和第二个抗应力区位于第一个拐角处。第一抗应力区域的面积不小于第二抗应力区域的面积。

6. 发明申请

US20140021601A1 SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR STRUCTURE THEREOF 有权
公开(公告)号：US20140021601A1
公开(公告)日：2014-01-23
申请号：US13644749
申请日：2012-10-04
申请人： CHIPBOND TECHNOLOGY CORPORATION
发明人： Chih-Ming Kuo , Lung-Hua Ho , Shih-Chieh Chang , Chia-Yeh Huang , Chin-Tang Hsieh
IPC分类号： H01L23/48 , H01L21/60
CPC分类号： H01L21/76885 , H01L21/4853 , H01L23/48 , H01L23/49811 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05568 , H01L2224/05644 , H01L2224/05647 , H01L2224/1147 , H01L2224/11849 , H01L2224/11903 , H01L2224/13006 , H01L2224/13016 , H01L2224/13023 , H01L2224/13076 , H01L2224/13082 , H01L2224/13083 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2924/00014 , H01L2924/00012 , H01L2224/05552
摘要： A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.

7. 发明公开

US20230170301A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20230170301A1
公开(公告)日：2023-06-01
申请号：US17972648
申请日：2022-10-25
申请人： CHIPBOND TECHNOLOGY CORPORATION
发明人： Chin-Tang Hsieh , You-Ming Hsu , Chun-Ting Kuo , Lung-Hua Ho , Chih-Ming Kuo
IPC分类号： H01L23/528 , H01L21/768 , H01L23/552
CPC分类号： H01L23/5286 , H01L21/76802 , H01L21/76877 , H01L23/552
摘要： A semiconductor structure includes a substrate, a dielectric layer, a connection layer and wire layers. The dielectric layer is disposed on a surface of the substrate and includes vias showing the surface. The connection layer is disposed on the dielectric layer, a first connection portion of the connection layer is located in the vias and connected to the surface, a second connection portion of the connection layer is connected to the dielectric layer. A first ground portion of the ground metal layer is connected to the first connection portion of the connection layer, and a second ground portion of the ground metal layer is connected to the second connection portion of the connection layer. Each of the wire layers is disposed on the second connection portion of the connection layer, and the second ground portion is located between the adjacent wire layers.

8. 发明授权

US10797213B2 Chip package and chip thereof 有权
公开(公告)号：US10797213B2
公开(公告)日：2020-10-06
申请号：US16260528
申请日：2019-01-29
申请人： CHIPBOND TECHNOLOGY CORPORATION
发明人： Chin-Tang Hsieh , Cheng-Hung Shih
IPC分类号： H01L33/62 , H01L33/38
摘要： A microchip is electrically connected to a substrate to become a chip package, preferably for LED. A chip of the package includes a body and at least one electrode which is disposed and exposed on a surface of the body. The electrode includes a confining groove and a confining wall. The confining wall is peripherally located around the confining groove and provided to confine at least one conductive particle of an adhesive in the confining groove. The electrode of the chip is electrically connected to a bonding pad of a substrate via the conductive particle confined in the confining groove.

9. 发明申请

US20190279926A1 SEMICONDUCTOR PACKAGE AND CIRCUIT SUBSTRATE THEREOF 审中-公开
公开(公告)号：US20190279926A1
公开(公告)日：2019-09-12
申请号：US15990747
申请日：2018-05-28
申请人： CHIPBOND TECHNOLOGY CORPORATION
发明人： Chin-Tang Hsieh
IPC分类号： H01L23/498 , H01L23/31 , H01L23/00
摘要： A semiconductor package includes a chip and a circuit substrate having leads. Each of the leads has an upper wide portion and a lower wide portion in a bonding area so as there are an upper notch and a lower notch in the bonding area. The upper and lower notches face toward the upper and lower wide portions of the adjacent lead, respectively. The upper and lower wide portions are designed to prevent defective bonding caused by shifting between the leads and the chip humps. Additionally, there are adequate etching spaces between the leads because the wide portions and the notches are staggered with each other such that incomplete etching between the leads is preventable during etching process.

10. 发明授权

US09000569B2 Semiconductor structure 有权
标题翻译：半导体结构
公开(公告)号：US09000569B2
公开(公告)日：2015-04-07
申请号：US14042976
申请日：2013-10-01
申请人： Chipbond Technology Corporation
发明人： Chin-Tang Hsieh , You-Ming Hsu , Ming-Sheng Liu , Chih-Ping Wang
IPC分类号： H01L21/4763 , H01L23/00 , H01L23/28 , H01L23/532 , H01L23/31
CPC分类号： H01L23/562 , H01L23/28 , H01L23/3192 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure includes a carrier, a first protective layer, a second protective layer, and a third protective layer. A first surface of the first protective layer comprises a first anti-stress zone. A first extension line from a first bottom edge intersects with a second extension line from a second bottom edge to form a first base point. A first projection line is formed on the first surface, an extension line of the first projection line intersects with the second bottom edge to form a first intersection point, a second projection line is formed on the first surface, and an extension line of the second projection line intersects with the first bottom edge to form a second intersection point. A zone by connecting the first base point, the first intersection point and the second intersection point is the first anti-stress zone.
摘要翻译：半导体结构包括载体，第一保护层，第二保护层和第三保护层。第一保护层的第一表面包括第一抗应力区。来自第一底部边缘的第一延伸线与第二延伸线从第二底部边缘相交以形成第一基点。第一投影线形成在第一表面上，第一投影线的延长线与第二底边缘相交形成第一交点，第二投影线形成在第一表面上，第二投影线形成在第二表面的延伸线上投影线与第一底边相交形成第二交点。通过连接第一基点，第一交点和第二交点的区域是第一抗应力区域。

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