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11. 发明授权

US5146605A Direct control facility for multiprocessor network 失效
标题翻译：多处理器网络的直接控制设备
公开(公告)号：US5146605A
公开(公告)日：1992-09-08
申请号：US644799
申请日：1991-01-23
申请人： Bruce L. Beukema , David W. Marquart , Ronald D. Morse
发明人： Bruce L. Beukema , David W. Marquart , Ronald D. Morse
IPC分类号： G06F11/22 , G06F11/30
CPC分类号： G06F11/2289 , G06F11/30 , G06F11/3027 , G06F11/3089 , G06F11/22
摘要： Control panel function is provided to bus units coupled together by an I/O bus. At least one bus unit has the capability to issue control commands through the bus to one or more other bus units. A control facility is integrated into bus units, and makes full use of existing paths to processor registers and main storage. Control commands are distinguished from other bus communications, and executed by the control facility, to provide a full control panel function for each bus unit incorporating the control facility.
摘要翻译：控制面板功能提供给通过I / O总线耦合在一起的总线单元。至少一个总线单元具有通过总线向一个或多个其它总线单元发出控制命令的能力。控制设备集成到总线单元中，充分利用了现有的处理器寄存器和主存储器的路径。控制命令与其他总线通信不同，并由控制设备执行，为包含控制设备的每个总线单元提供完整的控制面板功能。

12. 发明申请

US20130166849A1 Physically Remote Shared Computer Memory 审中-公开
公开(公告)号：US20130166849A1
公开(公告)日：2013-06-27
申请号：US13525002
申请日：2012-06-15
申请人： Bruce L. Beukema , Patrick M. Bland , Randolph S. Kolvick , James A. Marcella , Makoto Ono , Paul G. Reuland
发明人： Bruce L. Beukema , Patrick M. Bland , Randolph S. Kolvick , James A. Marcella , Makoto Ono , Paul G. Reuland
IPC分类号： G06F12/00
CPC分类号： G06F15/167
摘要： A computing system with physically remote shared computer memory, the computing system including: a remote memory management module, a plurality of computing devices, a plurality of remote memory modules that are external to the plurality of computing devices, and a remote memory controller, the remote memory management module configured to partition the physically remote shared computer memory amongst a plurality of computing devices; each computing device including a computer processor and a local memory controller, the local memory controller including: a processor interface, a local memory interface, and a local interconnect interface; each remote memory controller including: a remote memory interface and a remote interconnect interface, wherein the remote memory controller is operatively coupled to the data communications interconnect via the remote interconnect interface such that the remote memory controller is coupled for data communications with the local memory controller over the data communications interconnect.

13. 发明申请

US20130166672A1 Physically Remote Shared Computer Memory 审中-公开
标题翻译：物理远程共享计算机内存
公开(公告)号：US20130166672A1
公开(公告)日：2013-06-27
申请号：US13334237
申请日：2011-12-22
申请人： Bruce L. Beukema , Patrick M. Bland , Randolph S. Kolvick , James A. Marcella , Makoto Ono , Paul G. Reuland
发明人： Bruce L. Beukema , Patrick M. Bland , Randolph S. Kolvick , James A. Marcella , Makoto Ono , Paul G. Reuland
IPC分类号： G06F15/167
CPC分类号： G06F15/167
摘要： A computing system with physically remote shared computer memory, the computing system including: a remote memory management module, a plurality of computing devices, a plurality of remote memory modules that are external to the plurality of computing devices, and a remote memory controller, the remote memory management module configured to partition the physically remote shared computer memory amongst a plurality of computing devices; each computing device including a computer processor and a local memory controller, the local memory controller including: a processor interface, a local memory interface, and a local interconnect interface; each remote memory controller including: a remote memory interface and a remote interconnect interface, wherein the remote memory controller is operatively coupled to the data communications interconnect via the remote interconnect interface such that the remote memory controller is coupled for data communications with the local memory controller over the data communications interconnect.
摘要翻译：一种具有物理上远程共享计算机存储器的计算系统，所述计算系统包括：远程存储器管理模块，多个计算设备，在所述多个计算设备外部的多个远程存储器模块以及远程存储器控制器，远程存储器管理模块被配置为在多个计算设备之间划分物理上远程的共享计算机存储器; 每个计算设备包括计算机处理器和本地存储器控制器，所述本地存储器控制器包括：处理器接口，本地存储器接口和本地互连接口; 每个远程存储器控制器包括：远程存储器接口和远程互连接口，其中远程存储器控制器经由远程互连接口可操作地耦合到数据通信互连，使得远程存储器控制器被耦合用于与本地存储器控制器的数据通信通过数据通信互连。

14. 发明授权

US07895383B2 Event queue in a logical partition 有权
标题翻译：逻辑分区中的事件队列
公开(公告)号：US07895383B2
公开(公告)日：2011-02-22
申请号：US12043361
申请日：2008-03-06
申请人： Thomas A. Gregg , Richard L. Arndt , Bruce L. Beukema , David Craddock , Ronald E. Fuhs , Steven L. Rogers , Donald W. Schmidt , Bruce M. Walk
发明人： Thomas A. Gregg , Richard L. Arndt , Bruce L. Beukema , David Craddock , Ronald E. Fuhs , Steven L. Rogers , Donald W. Schmidt , Bruce M. Walk
IPC分类号： G06F13/24 , G06F3/00 , G06F13/40
CPC分类号： G06F9/546 , G06F2209/548 , H04L49/901
摘要： An information processing system is provided which includes a plurality of system resources, and an event queue having a maximum number of entries. An event recording mechanism of the information processing system is operable to make entries regarding events in the event queue, wherein the entries are limited to a predetermined number of active entries in the event queue per each type of event per each of the system resources. In a particular embodiment, the number of entries per each type of event for each of the system resources is limited to one.
摘要翻译：提供了包括多个系统资源的信息处理系统和具有最大数量的条目的事件队列。信息处理系统的事件记录机制可操作用于对事件队列中的事件进行条目，其中每个系统资源每个事件类型事件限制事件队列中预定数量的活动条目。在特定实施例中，每个系统资源的每种类型的事件的条目数量被限制为一个。

15. 发明授权

US07548964B2 Performance counters for virtualized network interfaces of communications networks 有权
标题翻译：通信网络虚拟化网络接口的性能计数器
公开(公告)号：US07548964B2
公开(公告)日：2009-06-16
申请号：US11247872
申请日：2005-10-11
申请人： Richard L. Arndt , Bruce L. Beukema , David Craddock , Ronald E. Fuhs , Thomas A. Gregg , Donald W. Schmidt , Bruce M. Walk
发明人： Richard L. Arndt , Bruce L. Beukema , David Craddock , Ronald E. Fuhs , Thomas A. Gregg , Donald W. Schmidt , Bruce M. Walk
IPC分类号： G06F15/177 , G06F15/16 , G06F15/173 , G06F3/00 , G06F5/00 , H04L12/28 , H04L12/56
CPC分类号： H04L43/00 , H04L41/046 , H04L41/5009 , H04L43/0847
摘要： Performance counters are provided for virtualized network interfaces of communications networks, while minimizing the use of hardware resources. A virtualized network interface includes physical resources, as well as logical resources. Dedicated performance counters are provided for the physical resources of the virtualized network interface, as well as for logical partitions coupled to that interface, while non-dedicated performance counters are provided for the logical resources. This enables the provision of performance counters for virtualized network interfaces, while minimizing hardware resources consumed by those interfaces.
摘要翻译：为通信网络的虚拟网络接口提供性能计数器，同时最大限度地减少硬件资源的使用。虚拟化网络接口包括物理资源以及逻辑资源。为虚拟化网络接口的物理资源以及耦合到该接口的逻辑分区提供专用性能计数器，同时为逻辑资源提供非专用性能计数器。这使得能够为虚拟化网络接口提供性能计数器，同时最小化这些接口所消耗的硬件资源。

16. 发明授权

US07496753B2 Data encryption interface for reducing encrypt latency impact on standard traffic 失效
标题翻译：数据加密接口，用于减少加密延迟对标准流量的影响
公开(公告)号：US07496753B2
公开(公告)日：2009-02-24
申请号：US10932943
申请日：2004-09-02
申请人： Bruce L. Beukema , Jamie R. Kuesel , Robert A. Shearer
发明人： Bruce L. Beukema , Jamie R. Kuesel , Robert A. Shearer
IPC分类号： G06F9/00
CPC分类号： G06F21/72 , H04L9/00
摘要： Methods and apparatus that may be utilized in systems to reduce the impact of latency associated with encrypting data on non-encrypted data are provided. Secure and non-secure data may be routed independently. Thus, non-secure data may be forwarded on (e.g., to targeted write buffers), without waiting for previously sent secure data to be encrypted. As a result, non-secure data may be made available for subsequent processing much earlier than in conventional systems utilizing a common data path for both secure and non-secure data.
摘要翻译：提供了可以在系统中用于减少与未加密数据加密数据相关的延迟的影响的方法和装置。安全和非安全数据可以独立路由。因此，非安全数据可以被转发（例如，到目标写缓冲器），而不等待先前发送的安全数据被加密。因此，与使用用于安全和非安全数据的公共数据路径的常规系统相比，非安全数据可能比后续处理可用。

17. 发明申请

US20080198743A1 DATA FLOW CONTROL FOR SIMULTANEOUS PACKET RECEPTION 失效
标题翻译：数据流控制同步分组接收
公开(公告)号：US20080198743A1
公开(公告)日：2008-08-21
申请号：US12113102
申请日：2008-04-30
申请人： Bruce L. Beukema , Mark J. Hickey , Robert A. Shearer
发明人： Bruce L. Beukema , Mark J. Hickey , Robert A. Shearer
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L47/30 , H04L47/39
摘要： Embodiments of the present invention provide methods, a module, and a system for calculating a credit limit for an interface capable of receiving multiple packets simultaneously. Generally, the multiple packets are simultaneously received at an interface on the second device, each packet being one of a plurality of packet types, and a flow control credit limit to be transmitted to the first device is adjusted based on the combination of packet types of the simultaneously received packets.
摘要翻译：本发明的实施例提供了用于计算能够同时接收多个分组的接口的信用限额的方法，模块和系统。通常，在第二设备的接口处同时接收多个分组，每个分组是多个分组类型之一，并且基于分组类型的组合来调整要发送到第一设备的流控制信用限制同时接收的数据包。

18. 发明授权

US5586265A Priority arbitrating interface for a plurality of shared subsystems coupled to a plurality of system processing devices for selective association of subsystem to processing device 失效
标题翻译：用于耦合到多个系统处理设备的多个共享子系统的优先级仲裁接口，用于将子系统选择性地关联到处理设备
公开(公告)号：US5586265A
公开(公告)日：1996-12-17
申请号：US472852
申请日：1995-06-07
申请人： Bruce L. Beukema
发明人： Bruce L. Beukema
IPC分类号： G06F13/00 , G06F11/00 , G06F15/17 , G06F13/368 , G06F13/20
CPC分类号： G06F11/2007 , G06F11/2005 , G06F15/17
摘要： The electronic postage meter includes a printing unit which is responsive to a plurality of motors for printing of a postage indicia in response to a control circuit. The control circuit is comprised of a programmable microprocessor in bus communication with an accounting means having memory units for accounting for the postage printed by the printing unit responsive to the programming of the microprocessor. An integrated circuit includes an address decoding module means for generating a unique combination of ASIC control signals in response to a respective address placed on the bus by the microprocessor. A timer register is responsive to ones of the control signals from the address decoding module to enable writing of the timer data into the timer registers by the microprocessor. The timer unit is responsive to the timer data for timer data. Also included are a plurality of non-volatile memory units. The non-volatile memory unit responsive to other ones of the control signals from the address decoding module to enable the non-volatile memory units for writing data into the non-volatile memory unit by the microprocessor. The integrated circuit further includes a non-volatile memory access timer unit for causing the control signal from the address decoding module enabling the non-volatile memory units to stay active for a predetermined time of the non-volatile memory access timer.
摘要翻译：电子邮资计包括响应于多个电动机响应于控制电路打印邮资标记的打印单元。该控制电路包括与计费装置总线通信的可编程微处理器，该计费装置具有存储单元，用于根据微处理器的编程来计算由打印单元打印的邮资。集成电路包括地址解码模块装置，用于响应由微处理器放置在总线上的相应地址产生ASIC控制信号的唯一组合。定时器寄存器响应来自地址解码模块的控制信号中的一个，以使定时器数据能够由微处理器写入定时器寄存器。定时器单元响应于定时器数据用于定时器数据。还包括多个非易失性存储器单元。所述非易失性存储器单元响应来自所述地址解码模块的其他控制信号，以使得所述非易失性存储器单元能够由所述微处理器将数据写入所述非易失性存储器单元。集成电路还包括非易失性存储器访问定时器单元，用于使来自地址解码模块的控制信号使得非易失性存储器单元在非易失性存储器访问定时器的预定时间内保持活动。

19. 发明申请

US20140047175A1 IMPLEMENTING EFFICIENT CACHE TAG LOOKUP IN VERY LARGE CACHE SYSTEMS 审中-公开
标题翻译：在非常大的高速缓存系统中实现高效的高速缓存标签
公开(公告)号：US20140047175A1
公开(公告)日：2014-02-13
申请号：US13570778
申请日：2012-08-09
申请人： Bulent Abali , Bruce L. Beukema , James A. Marcella , Paul G. Reuland , Michael M. Tsao
发明人： Bulent Abali , Bruce L. Beukema , James A. Marcella , Paul G. Reuland , Michael M. Tsao
IPC分类号： G06F12/00
CPC分类号： G06F12/0895 , G06F12/0802 , G06F12/0897 , G06F12/123 , G06F2212/304
摘要： A method and circuit for implementing a cache directory and efficient cache tag lookup in very large cache systems, and a design structure on which the subject circuit resides are provided. A tag cache includes a fast partial large (LX) cache directory maintained separately on chip apart from a main LX cache directory (LXDIR) stored off chip in dynamic random access memory (DRAM) with large cache data (LXDATA). The tag cache stores most frequently accessed LXDIR tags. The tag cache contains predefined information enabling access to LXDATA directly on tag cache hit with matching address and data present in the LX cache. Only on tag cache misses the LXDIR is accessed to reach LXDATA.
摘要翻译：一种用于在非常大的缓存系统中实现高速缓存目录和高效缓存标签查找的方法和电路，以及提供了主题电路所在的设计结构。标签高速缓存包括除了存储在具有大缓存数据（LXDATA）的动态随机存取存储器（DRAM）中的芯片外的主LX高速缓存目录（LXDIR）之外分开保存的快速部分大（LX）高速缓存目录。标签缓存存储最常访问的LXDIR标签。标签缓存包含预定义信息，可以直接在标签缓存命中上访问LXDATA，匹配地址和LX缓存中存在的数据。只有在标签缓存未命中时才能访问LXDIR以达到LXDATA。

20. 发明授权

US07948894B2 Data flow control for simultaneous packet reception 失效
标题翻译：用于同时进行数据包接收的数据流控制
公开(公告)号：US07948894B2
公开(公告)日：2011-05-24
申请号：US12113102
申请日：2008-04-30
申请人： Bruce L. Beukema , Mark J. Hickey , Robert A. Shearer
发明人： Bruce L. Beukema , Mark J. Hickey , Robert A. Shearer
IPC分类号： H04L12/26
CPC分类号： H04L47/10 , H04L47/30 , H04L47/39
摘要： Embodiments of the present invention provide methods, a module, and a system for calculating a credit limit for an interface capable of receiving multiple packets simultaneously. Generally, the multiple packets are simultaneously received at an interface on the second device, each packet being one of a plurality of packet types, and a flow control credit limit to be transmitted to the first device is adjusted based on the combination of packet types of the simultaneously received packets.
摘要翻译：本发明的实施例提供了用于计算能够同时接收多个分组的接口的信用限额的方法，模块和系统。通常，在第二设备的接口处同时接收多个分组，每个分组是多个分组类型之一，并且基于分组类型的组合来调整要发送到第一设备的流控制信用限制同时接收的数据包。

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