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11. 发明授权

US06460120B1 Network processor, memory organization and methods 失效
标题翻译：网络处理器，内存组织和方法
公开(公告)号：US06460120B1
公开(公告)日：2002-10-01
申请号：US09384744
申请日：1999-08-27
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Piyush Chunilal Patel , Juan Guillermo Revilla , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Piyush Chunilal Patel , Juan Guillermo Revilla , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F1300
CPC分类号： H04Q11/0478 , H04L2012/5681
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate. The memory elements and interface processors together form a network processor capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by the plurality of processors.
摘要翻译：一种网络交换设备，用于这种设备的部件，以及操作这样的设备的方法，其中通过多个存储器元件和形成在半导体衬底上的多个接口处理器的协作来增强数据流处理和灵活性。存储器元件和接口处理器一起形成一个网络处理器，能够在执行指导网络中的数据流的指令中与其它元件协作。存储元件的访问以特定方式和操作规则进行控制，这些规则由多个处理器提供对多个存储器元件的受控多次访问。

12. 发明授权

US06449576B1 Network processor probing and port mirroring 失效
标题翻译：网络处理器探测和端口镜像
公开(公告)号：US06449576B1
公开(公告)日：2002-09-10
申请号：US09538247
申请日：2000-03-29
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken , Chad Everett Winemiller
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken , Chad Everett Winemiller
IPC分类号： G01R2728
CPC分类号： H04L43/50 , G01R31/31926
摘要： A method and system for systematically accessing and monitoring operating parameter signals within an IC device. A probe configuration logic selects a subset of signals from among a set of available signals within a physical or logical subdivision of the IC device. Signal access logic selectively provides physical or logical access from the selected subset of signals within the physical or logical subdivision of the IC device to a probe sensor, such that IC device operations may be flexibly and comprehensively monitored. A local mode selector provides remote access to the selected subset of signals at an input/output (I/O) data interface. Data packaging logic in communication with the probe sensor permits port mirroring of the I/O data interface.
摘要翻译：一种用于系统地访问和监视IC设备内的操作参数信号的方法和系统。探针配置逻辑从IC器件的物理或逻辑细分内的一组可用信号中选择一个信号子集。信号访问逻辑选择性地从IC器件的物理或逻辑细分中的选定的信号子集提供到探针传感器的物理或逻辑访问，使得可以灵活和全面地监视IC器件操作。本地模式选择器可在输入/输出（I / O）数据接口上远程访问选定的信号子集。与探头传感器通信的数据封装逻辑允许端口镜像I / O数据接口。

13. 发明授权

US07315901B1 Method and system for network processor scheduling outputs using disconnect/reconnect flow queues 失效
标题翻译：使用断开/重新连接流队列的网络处理器调度输出的方法和系统
公开(公告)号：US07315901B1
公开(公告)日：2008-01-01
申请号：US09548913
申请日：2000-04-13
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F15/173 , H04L12/24
CPC分类号： H04L47/522 , H04L47/2425 , H04L47/50 , H04L47/568 , H04L47/58 , H04L47/6235 , H04L47/6265
摘要： A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. A system for allowing peak bursts based on a system of credits and charges is taught along limits on such peak bursts. Also taught is a system for preventing a flow's disconnection and reconnection to the queues from allowing it to unfairly achieve an improved position.
摘要翻译：一种将信息单元从网络处理器移动到数据传输网络的系统和方法，其以容纳几个不同级别的服务的优先顺序排列。本发明包括一种方法和系统，用于根据存储的与信息单元的各种源相关联的优先级来调度来自网络处理单元的处理的信息单元（或帧）的出口。根据这种峰值突发的限制，教导了基于信用和费用系统允许峰值突发的系统。还教导了一种用于防止流动断开和重新连接到队列的系统，从而允许其不公平地实现改进的位置。

14. 发明授权

US07133931B1 Method and system for making a frame alteration in a network processing system 失效
标题翻译：在网络处理系统中进行帧改变的方法和系统
公开(公告)号：US07133931B1
公开(公告)日：2006-11-07
申请号：US09479026
申请日：2000-01-07
申请人： Samuel Steven Allison , Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Samuel Steven Allison , Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F15/16 , G06F15/167 , H04B7/216 , H04L12/28
CPC分类号： H04L49/30 , H04L49/109
摘要： A system and method of altering frames being processed by a network processing unit. The system includes a set of defined alterations, with some of the alterations being fixed alterations which are advantageously handled by hardware to accomplish the fixed alterations rapidly and without executing a stored program and other alterations which include a variable portion, with these variable alterations being accomplished through the use of stored programs allowing the variables to be used to effect variable alterations to a frame. The present system accommodates a change in the duration of life of a frame or information unit and addition or deletion of bits and also allows for a new cyclic redundancy checking to be accomplished for a revised information unit. Advantageously, the frame alteration system is on the same substrate as the processors.
摘要翻译：一种改变由网络处理单元处理的帧的系统和方法。该系统包括一组定义的改变，其中一些变化是固定的改变，其有利地被硬件处理以快速完成固定的变更，而不执行存储的程序和包括可变部分的其他改变，这些可变改变被完成通过使用存储的程序，允许使用变量来实现对框架的变化。本系统适应帧或信息单元的持续时间的改变以及比特的添加或删除，并且还允许为修改的信息单元完成新的循环冗余校验。有利地，框架改变系统在与处理器相同的衬底上。

15. 发明授权

US07120630B2 Full match (FM) search algorithm implementation for a network processor 失效
标题翻译：网络处理器的完全匹配（FM）搜索算法实现
公开(公告)号：US07120630B2
公开(公告)日：2006-10-10
申请号：US10650397
申请日：2003-08-28
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F7/00 , H04L12/56
CPC分类号： H04L45/742 , H04L45/7453 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935 , Y10S707/99936 , Y10S707/99937 , Y10S707/99943 , Y10S707/99945
摘要： Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key.
摘要翻译：用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。键输入，对密钥执行哈希函数，访问直接表（DT），并通过模式搜索控制块（PSCB），树直到达到叶。搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。检索所需的两个密钥和相应的信息都存储在Patricia树结构中。散列函数提供密钥的比特到散列密钥的比特的n> n映射。

16. 发明授权

US06977928B1 Method and system for data flow multicasting 有权
标题翻译：数据流多播的方法和系统
公开(公告)号：US06977928B1
公开(公告)日：2005-12-20
申请号：US09548906
申请日：2000-04-13
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Steven Kenneth Jenkins , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Steven Kenneth Jenkins , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： H04L12/18 , H04L12/28
CPC分类号： H04L12/18
摘要： A system and method of transmitting multiple output messages from a single input message system where the system is keeping the messages in order by correlating the output messages with the input messages. For each output message, an indicator is associated with the output message indicating whether this output message is the last message being generated for the given input message. This allows multicasting to occur in a system where the output is matched to the input by allowing multiple output messages to be associated with a single input message.
摘要翻译：从单个输入消息系统发送多个输出消息的系统和方法，其中系统通过将输出消息与输入消息相关联来保持消息的顺序。对于每个输出消息，指示符与输出消息相关联，指示该输出消息是否是针对给定输入消息生成的最后消息。这允许在通过允许多个输出消息与单个输入消息相关联的输出与输入匹配的系统中发生多播。

17. 发明授权

US06671280B1 Network processor for multiprotocol data flows 有权
标题翻译：用于多协议数据流的网络处理器
公开(公告)号：US06671280B1
公开(公告)日：2003-12-30
申请号：US09535794
申请日：2000-03-29
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： H04L1256
CPC分类号： H04L49/30 , H04L45/502 , H04L49/201 , H04L49/251 , H04L49/3009 , H04L49/602 , H04L49/606 , H04L2012/5618 , H04L2012/5665
摘要： A method for integrating Asynchronous Transfer Mode (ATM) and frame-based traffic flows within a telecommunications network is disclosed. The telecommunications network includes a network processor having upside processing means for delivering an incoming flow from the telecommunications network to a switch and downside processing means for delivering outgoing network traffic from the switch to the telecommunications network. The incoming flow is initially received at the upside processing means as a frame-based flow. The incoming flow may be characterized as belonging to a group having frame-based flows and ATM flows. In response to the receipt of the incoming flow, the incoming flow is determined if it is destined for a legacy, ATM-only device. The incoming flow is then processed according to the determined routing requirements and the incoming flow characterization before delivering the incoming flow to the switch.
摘要翻译：公开了一种在电信网络内集成异步传输模式（ATM）和基于帧的业务流的方法。电信网络包括具有上行处理装置的网络处理器，用于将来自电信网络的输入流传送到交换机，以及下行处理装置，用于将来自交换机的输出网络业务传送到电信网络。最初在上行处理装置处接收输入流作为基于帧的流。输入流可以被表征为属于具有基于帧的流和ATM流的组。响应于接收到的流入，确定进入流是否发往传统的仅ATM设备。然后根据确定的路由要求和输入流特性，将传入流量传送到交换机之前处理进入流。

18. 发明授权

US06557053B1 Queue manager for a buffer 失效
标题翻译：队列管理器为缓冲区
公开(公告)号：US06557053B1
公开(公告)日：2003-04-29
申请号：US09477179
申请日：2000-01-04
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Michael Raymond Trombley , Fabrice Jean Verplanken
IPC分类号： G06F1314
CPC分类号： G06F13/1673
摘要： A bandwidth conserving queue manager for a FIFO buffer is provided, preferably on an ASIC chip and preferably including separate DRAM storage that maintains a FIFO queue which can extend beyond the data storage space of the FIFO buffer to provide additional data storage space as needed. FIFO buffers are used on the ASIC chip to store and retrieve multiple queue entries. As long as the total size of the queue does not exceed the storage available in the buffers, no additional data storage is needed. However, when some predetermined amount of the buffer storage space in the FIFO buffers is exceeded, data are written to and read from the additional data storage, and preferably in packets which are of optimum size for maintaining peak performance of the data storage device and which are written to the data storage device in such a way that they are queued in a first-in, first-out (FIFO) sequence of addresses. Preferably, the data are written to and are read from the DRAM in burst mode.
摘要翻译：提供了用于FIFO缓冲器的带宽保存队列管理器，优选地在ASIC芯片上，并且优选地包括分离的DRAM存储器，其维持FIFO队列，其可以超出FIFO缓冲器的数据存储空间，以根据需要提供附加的数据存储空间。在ASIC芯片上使用FIFO缓冲器来存储和检索多个队列条目。只要队列的总大小不超过缓冲区中可用的存储空间，则不需要额外的数据存储。然而，当超过FIFO缓冲器中的一些预定量的缓冲存储空间时，数据被写入附加数据存储器并从其中读出，并且优选地是具有用于保持数据存储设备的峰值性能的最佳尺寸的数据包，以及哪个被写入数据存储设备，使得它们以先入先出（FIFO）地址序列排队。优选地，以突发模式将数据写入DRAM并从DRAM读取。

19. 发明授权

US07383244B2 Longest prefix match (LPM) algorithm implementation for a network processor 失效
标题翻译：用于网络处理器的最长前缀匹配（LPM）算法实现
公开(公告)号：US07383244B2
公开(公告)日：2008-06-03
申请号：US11045634
申请日：2005-01-28
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F7/00
CPC分类号： G06F17/30985 , H04L45/7457 , Y10S707/99931 , Y10S707/99933 , Y10S707/99936 , Y10S707/99942 , Y10S707/99943 , Y10S707/99945
摘要： Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first: match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.
摘要翻译：当搜索具有可变长度模式或前缀的表时，用于查找最长前缀的新型数据结构，方法和装置匹配搜索。要找到完全匹配或最佳匹配前缀，模式必须一次比较一下，直到找到完全匹配或第一个匹配。这需要“n”个比较或存储器访问来识别最接近的匹配模式。树的建立方式使得匹配结果保证是最佳匹配，无论是完全匹配还是最长匹配前缀。使用所有鸟的踪迹和相关的前缀长度可以确定路线中正确的前缀结果。通过构建，搜索树在步道或树的步行期间在第一次比较之前或之后提供最佳的匹配前缀。

20. 发明授权

US06952424B1 Method and system for network processor scheduling outputs using queueing 失效
标题翻译：使用排队的网络处理器调度输出的方法和系统
公开(公告)号：US06952424B1
公开(公告)日：2005-10-04
申请号：US09548912
申请日：2000-04-13
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： H04L12/28 , H04L12/56 , H04L29/06
CPC分类号： H04L49/90
摘要： A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a weighted fair queueing system where the position of the next service in a best efforts system for using bandwidth which is not used by committed bandwidth is determined based on the length of the frame and the weight of the particular flow. A “back pressure” system keeps a flow from being selected if its output cannot accept an additional frame because the current level of that port queue exceeds a threshold.
摘要翻译：一种将信息单元从网络处理器移动到数据传输网络的系统和方法，其以容纳几个不同级别的服务的优先顺序排列。本发明包括一种方法和系统，用于根据存储的与信息单元的各种源相关联的优先级来调度来自网络处理单元的处理的信息单元（或帧）的出口。优选实施例中的优先级包括低延迟服务，最小带宽，加权公平排队以及用于在较长时间内防止用户继续超过其服务水平的系统。本发明包括一个加权公平排队系统，其中基于帧的长度和特定流的权重确定用于使用未被承诺带宽使用的带宽的最佳努力系统中的下一个服务的位置。如果该端口队列的当前级别超过阈值，则“背压”系统的输出不能接受额外的帧，从而保持流量的选择。

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