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11. 发明授权

US6154384A Ternary content addressable memory cell 有权
标题翻译：三进制内容可寻址存储单元
公开(公告)号：US6154384A
公开(公告)日：2000-11-28
申请号：US439317
申请日：1999-11-12
申请人： Bindiganavale S. Nataraj , Sandeep Khanna , Varadarajan Srinivasan
发明人： Bindiganavale S. Nataraj , Sandeep Khanna , Varadarajan Srinivasan
IPC分类号： G11C15/04 , G11C15/00
CPC分类号： G11C15/04
摘要： A ternary content addressable memory (CAM) cell. For one embodiment, the ternary CAM cell includes a first memory cell, a compare circuit, a second memory cell and a mask circuit. The first memory cell is coupled to a first pair of bit lines that carries data to and from the first memory cell. The compare circuit receives comparand data on a pair of compare signal lines, and compares the comparand data with the data stored in the first memory cell. The compare circuit includes a pair of transistors and a match transistor. The pair of transistors receives the comparand data on the compare signal lines and also receives the data stored in the first memory cell. The match transistor determines the state of a match line. The second memory cell stores mask data that may mask the comparison result such that it does not affect the logical state of the match line.
摘要翻译：三元内容可寻址存储器（CAM）单元。对于一个实施例，三元CAM单元包括第一存储单元，比较电路，第二存储单元和掩模电路。第一存储器单元耦合到第一对位线，其将数据传送到第一存储器单元并从第一存储单元传送数据。比较电路在一对比较信号线上接收比较数据，并将比较数据与存储在第一存储单元中的数据进行比较。比较电路包括一对晶体管和匹配晶体管。该对晶体管在比较信号线上接收比较数据，并且还接收存储在第一存储单元中的数据。匹配晶体管确定匹配线的状态。第二存储器单元存储可以掩蔽比较结果使得其不影响匹配线的逻辑状态的掩码数据。

12. 发明授权

US6148364A Method and apparatus for cascading content addressable memory devices 失效
标题翻译：用于级联内容可寻址存储器件的方法和装置
公开(公告)号：US6148364A
公开(公告)日：2000-11-14
申请号：US001110
申请日：1997-12-30
申请人： Varadarajan Srinivasan , Bindiganavale S. Nataraj , Sandeep Khanna
发明人： Varadarajan Srinivasan , Bindiganavale S. Nataraj , Sandeep Khanna
IPC分类号： G11C15/00 , G11C15/04 , G06F12/02
CPC分类号： G11C15/04 , G11C15/00
摘要： A method and apparatus for cascading content addressable memory (CAM) devices is disclosed. The method and apparatus may be particularly useful when depth cascading CAM devices that operate in a flow-through mode. In the flow-through mode, a compare instruction may be simultaneously provided to each CAM device in the cascade, and the match address, data stored at the matched location, or other status information may then be output to a common output data bus by the highest priority matching CAM device in the same cycle that the instruction is provided to the CAM devices. Each CAM device may have a cascade input and a cascade output to perform the cascade function. The cascade output of a higher priority CAM device may be connected to the cascade input of the next lower priority CAM device. The higher priority CAM device may assert a cascade signal on its cascade output at a predetermined time after receiving an input signal (e.g., a clock signal). Asserting the cascade signal may indicate that the higher priority CAM device has completed the compare instruction. When the lower priority CAM device detects that the cascade signal has been asserted on its cascade input, the lower priority CAM device may sample the match flag of the higher priority CAM device to determine if the lower priority CAM device may output its data to the common output data bus.
摘要翻译：公开了用于级联内容可寻址存储器（CAM）设备的方法和装置。当以流通模式操作的深度级联CAM设备时，该方法和设备可能是特别有用的。在流通模式中，可以在级联中同时向每个CAM设备提供比较指令，并且匹配地址，存储在匹配位置的数据或其他状态信息然后可以被输出到公共输出数据总线在CAM指令提供给CAM设备的同一周期内，最高优先级的匹配CAM设备。每个CAM设备可以具有级联输入和级联输出以执行级联功能。较高优先级的CAM设备的级联输出可以连接到下一个较低优先级的CAM设备的级联输入。较高优先级的CAM设备可以在接收到输入信号（例如，时钟信号）之后的预定时间在其级联输出上断言级联信号。断开级联信号可能表明较高优先级的CAM设备已经完成了比较指令。当较低优先级的CAM设备检测到级联信号已经在其级联输入上被断言时，较低优先级的CAM设备可以对较高优先级的CAM设备的匹配标志进行采样，以确定较低优先级的CAM设备是否可以将其数据输出到公共输出数据总线。

13. 发明授权

US06125049A Match line control circuit for content addressable memory 失效
公开(公告)号：US06125049A
公开(公告)日：2000-09-26
申请号：US225919
申请日：1999-01-05
申请人： Bindiganavale S. Nataraj
发明人： Bindiganavale S. Nataraj
IPC分类号： G06F7/02 , G11C15/04 , G11C15/00
CPC分类号： G06F7/02 , G11C15/04
摘要： A match line control circuit includes a weak, static pull-up transistor and a strong, dynamic pull-up transistor coupled between a match line of an associated CAM and a supply voltage. Prior to compare operations, both the static pull-up transistor and the dynamic pull-up transistor are in a conductive state and thereby quickly charge the match line to the supply voltage. During compare operations, the dynamic transistor is turned off to reduce current flow between the supply voltage and the match line. In some embodiments, the static pull-up transistor and the dynamic pull-up transistor are configured to match the parasitics of the CAM cells 10 coupled to the match line, thereby increasing performance of the associated CAM.

14. 发明授权

US08913412B1 Incremental adaptive match line charging with calibration 有权
标题翻译：增量自适应匹配线充电与校准
公开(公告)号：US08913412B1
公开(公告)日：2014-12-16
申请号：US13306896
申请日：2011-11-29
申请人： Sandeep Khanna , Bindiganavale S. Nataraj , Varadarajan Srinivasan
发明人： Sandeep Khanna , Bindiganavale S. Nataraj , Varadarajan Srinivasan
IPC分类号： G11C15/04
CPC分类号： G11C15/04
摘要： A content addressable memory (CAM) device having any number of rows, each of the rows including a match line connected to a plurality of CAM cells, a match line detector circuit, and an incremental match line charge circuit. The detector circuit generates a feedback signal based on a detected match line voltage. The charge circuit partially pre-charges the match line to an intermediate voltage during a pre-charge phase of a compare operation, and then selectively charges the match line higher towards a supply voltage in response to the feedback signal.
摘要翻译：具有任意行数的内容可寻址存储器（CAM）器件，每行包括连接到多个CAM单元的匹配线，匹配线检测器电路和增量匹配线充电电路。检测器电路基于检测到的匹配线电压产生反馈信号。充电电路在比较操作的预充电阶段期间将匹配线部分预充电到中间电压，然后响应于反馈信号而选择性地将匹配线充电到电源电压。

15. 发明授权

US08324929B1 Integrated circuit with reconfigurable inputs/outputs 有权
标题翻译：具有可重配置输入/输出的集成电路
公开(公告)号：US08324929B1
公开(公告)日：2012-12-04
申请号：US12826124
申请日：2010-06-29
申请人： Vinay Raja Iyengar , Venkat Rajendher Reddy Gaddam , Bindiganavale S. Nataraj
发明人： Vinay Raja Iyengar , Venkat Rajendher Reddy Gaddam , Bindiganavale S. Nataraj
IPC分类号： H03K19/173 , H03K19/00
CPC分类号： H03K19/1732 , H03K19/17744
摘要： An integrated circuit device can include a core section coupled to a plurality of signal paths having a predetermined physical order with respect to one another. A configuration circuit can selectively connect each signal path to a corresponding one of a plurality of physical connection points to the IC device according to one of at least two different physical orders in response to configuration information.
摘要翻译：集成电路设备可以包括耦合到具有相对于彼此的预定物理顺序的多个信号路径的核心部分。响应于配置信息，配置电路可以根据至少两个不同的物理顺序中的一个选择性地将每个信号路径连接到多个物理连接点中的对应的一个到IC设备。

16. 发明授权

US08089794B1 Precharge circuits and methods for content addressable memory (CAM) and related devices 有权
标题翻译：内容可寻址存储器（CAM）及相关设备的预充电电路和方法
公开(公告)号：US08089794B1
公开(公告)日：2012-01-03
申请号：US12861084
申请日：2010-08-23
申请人： Chetan Deshpande , Bindiganavale S. Nataraj
发明人： Chetan Deshpande , Bindiganavale S. Nataraj
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A method may include selectively coupling a result line to a reference node in response to a compare data value being applied to a plurality of compare cell circuits; precharging the result line to the precharge potential by enabling a first precharge path while the compare data value is being applied; and after precharging the result line by enabling the first precharge path, disabling the first precharge path to place it in a high impedance state.
摘要翻译：响应于应用于多个比较单元电路的比较数据值，方法可以包括选择性地将结果行耦合到参考节点; 通过在应用比较数据值的同时启用第一预充电路径，将结果行预充电到预充电电位; 并且在通过启用第一预充电路径对结果行进行预充电之后，禁用第一预充电路径将其置于高阻抗状态。

17. 发明授权

US07848129B1 Dynamically partitioned CAM array 有权
标题翻译：动态分区CAM阵列
公开(公告)号：US07848129B1
公开(公告)日：2010-12-07
申请号：US12275160
申请日：2008-11-20
申请人： Chetan Deshpande , Vinay Iyengar , Bindiganavale S. Nataraj
发明人： Chetan Deshpande , Vinay Iyengar , Bindiganavale S. Nataraj
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A content addressable memory (CAM) device includes a comparand register, a CAM array, and partition logic. The comparand register has inputs to receive a search key, and outputs coupled to the CAM array, which includes a plurality of individually selectable sub-arrays. Each sub-array includes a number of rows of CAM cells and a control circuit, wherein each row of CAM cells is coupled to a match line, and wherein the control circuit has an input to receive a corresponding sub-array enable signal. The partition logic has an input to receive a partition select signal, and is configured to generate the sub-array enable signals in response to the partition select signal. The control circuits selectively propagate the search key through the sub-arrays in response to the sub-array enable signals.
摘要翻译：内容可寻址存储器（CAM）装置包括比较寄存器，CAM阵列和分区逻辑。比较寄存器具有用于接收搜索关键字的输入，并且耦合到CAM阵列的输出，其包括多个可单独选择的子阵列。每个子阵列包括多个CAM单元行和一个控制电路，其中每行CAM单元耦合到匹配线，并且其中控制电路具有用于接收对应的子阵列使能信号的输入。分区逻辑具有用于接收分区选择信号的输入，并且被配置为响应于分区选择信号而生成子阵列使能信号。响应于子阵列使能信号，控制电路通过子阵列选择性地传播搜索关键字。

18. 发明授权

US07830691B2 Low power content addressable memory 有权
标题翻译：低功耗内容可寻址内存
公开(公告)号：US07830691B2
公开(公告)日：2010-11-09
申请号：US12175272
申请日：2008-07-17
申请人： Varadarajan Srinivasan , Sandeep Khanna , Bindiganavale S. Nataraj
发明人： Varadarajan Srinivasan , Sandeep Khanna , Bindiganavale S. Nataraj
IPC分类号： G11C15/00
CPC分类号： G11C15/04
摘要： A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled to the N compare lines.
摘要翻译：低功率内容可寻址存储器（CAM）设备。 CAM设备接收N位比较值，并且作为响应，在CAM设备内激活小于N个比较线，以将比较值的N个比特中的每一个与耦合到N个比较线的CAM小区的内容进行比较。

19. 发明授权

US07461295B1 Timing failure analysis in a semiconductor device having a pipelined architecture 有权
标题翻译：具有流水线结构的半导体器件中的定时故障分析
公开(公告)号：US07461295B1
公开(公告)日：2008-12-02
申请号：US11194067
申请日：2005-07-29
申请人： Vinay Iyengar , Bindiganavale S. Nataraj
发明人： Vinay Iyengar , Bindiganavale S. Nataraj
IPC分类号： G06F11/00
CPC分类号： G01R31/31726 , G01R31/3016
摘要： A method of testing a semiconductor device having a pipelined architecture. Operation of a first pipeline stage of the semiconductor is disabled during a first pipelined operation to establish test data at an input of a second pipeline stage of the semiconductor device. A second pipelined operation is executed to enable the second pipeline stage to generate an intermediate result using the test data. A final result of the second pipelined operation is evaluated to determine whether the second pipeline stage produced a correct intermediate result.
摘要翻译：一种测试具有流水线结构的半导体器件的方法。在第一流水线操作期间禁用半导体的第一流水线级的操作以在半导体器件的第二流水线级的输入处建立测试数据。执行第二流水线操作以使得第二流水线级能够使用测试数据生成中间结果。评估第二流水线操作的最终结果以确定第二流水线阶段是否产生正确的中间结果。

20. 发明授权

US07171595B1 Content addressable memory match line detection 失效
标题翻译：内容可寻址内存匹配行检测
公开(公告)号：US07171595B1
公开(公告)日：2007-01-30
申请号：US10156532
申请日：2002-05-28
申请人： Charles C. Huse , Bindiganavale S. Nataraj , Kumaresh Kavedi
发明人： Charles C. Huse , Bindiganavale S. Nataraj , Kumaresh Kavedi
IPC分类号： G11C29/00
CPC分类号： G11C29/12 , G11C15/00
摘要： According to one embodiment of the present invention, a content addressable memory (CAM) device includes a CAM array that includes a plurality of rows of CAM cells each coupled to a corresponding match line, and a test circuit coupled to the match lines that outputs row match results from the match lines onto a match output.
摘要翻译：根据本发明的一个实施例，内容可寻址存储器（CAM）装置包括CAM阵列，其包括多个CAM单元阵列，每个CAM单元耦合到对应的匹配线，以及耦合到输出行的匹配线的测试电路将匹配行的结果与匹配输出进行匹配。

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