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11. 发明授权

US06706640B1 Metal silicide etch resistant plasma etch method 失效
标题翻译：金属硅化物抗蚀刻等离子体蚀刻方法
公开(公告)号：US06706640B1
公开(公告)日：2004-03-16
申请号：US10292355
申请日：2002-11-12
申请人： Ming-Huan Tsai , Ju-Wang Hsu , Peng-Fu Hsu , Hun-Jan Tao
发明人： Ming-Huan Tsai , Ju-Wang Hsu , Peng-Fu Hsu , Hun-Jan Tao
IPC分类号： H01L21302
CPC分类号： H01L21/28518 , H01L21/31116 , H01L21/76802
摘要： A plasma etch method for etching a dielectric layer and an etch stop layer to reach a metal silicide layer formed thereunder employs for etching the etch stop layer an etchant gas composition comprising a fluorine containing gas and a nitrogen containing gas, preferably with a carrier gas such as argon or helium, but without an oxygen containing gas or a carbon and oxygen containing gas. The plasma etch method is selective for the etch stop layer with respect to the metal silicide layer, thus maintaining the physical and electrical integrity of the metal silicide layer.
摘要翻译：用于蚀刻介电层和蚀刻停止层以达到其下形成的金属硅化物层的等离子体蚀刻方法用于蚀刻蚀刻停止层包括含氟气体和含氮气体的蚀刻剂气体组合物，优选地使用载气如作为氩或氦，但不含含氧气体或含碳和氧的气体。等离子体蚀刻方法对于蚀刻停止层相对于金属硅化物层是选择性的，从而保持金属硅化物层的物理和电气完整性。

12. 发明授权

US07271448B2 Multiple gate field effect transistor structure 有权
标题翻译：多栅场效应晶体管结构
公开(公告)号：US07271448B2
公开(公告)日：2007-09-18
申请号：US11057423
申请日：2005-02-14
申请人： Ju-Wang Hsu , Jyu-Horng Shieh , Hun-Jan Tao , Chang-Yun Chang , Zhong Tang Xuan , Sheng-Da Liu
发明人： Ju-Wang Hsu , Jyu-Horng Shieh , Hun-Jan Tao , Chang-Yun Chang , Zhong Tang Xuan , Sheng-Da Liu
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/78687
摘要： A multiple gate region FET device for forming up to 6 FET devices and method for forming the same, the device including a multiple fin shaped structure comprising a semiconductor material disposed on a substrate; said multiple fin shaped structure comprising substantially parallel spaced apart sidewall portions, each of said sidewall portions comprising major inner and outer surfaces and an upper surface; wherein, each of said surfaces comprises a surface for forming an overlying field effect transistor (FET).
摘要翻译：一种用于形成多达6个FET器件的多栅极区域FET器件及其形成方法，该器件包括多个鳍状结构，其包括设置在衬底上的半导体材料; 所述多个鳍状结构包括基本上平行的间隔开的侧壁部分，每个所述侧壁部分包括主要内表面和外表面以及上表面; 其中，每个所述表面包括用于形成上覆场效应晶体管（FET）的表面。

13. 发明申请

US20060148157A1 Geometrically optimized spacer to improve device performance 审中-公开
标题翻译：几何优化的垫片，以提高设备性能
公开(公告)号：US20060148157A1
公开(公告)日：2006-07-06
申请号：US11026010
申请日：2004-12-31
申请人： Hun-Jan Tao , Ju-Wang Hsu , Mong-Song Liang
发明人： Hun-Jan Tao , Ju-Wang Hsu , Mong-Song Liang
IPC分类号： H01L21/8238
CPC分类号： H01L29/6656 , H01L21/823864 , H01L29/665 , H01L29/7833
摘要： A CMOS device with trapezoid shaped spacers and a method for forming the same with improved critical dimension control and improved salicide formation, the CMOS device including a semiconductor substrate; a gate structure comprising a gate dielectric on the semiconductor substrate and a gate electrode on the gate dielectric; trapezoid shaped spacers adjacent either side of the gate structure; wherein, the trapezoid shaped spacers have a maximum height at an inner edge adjacent the gate electrode lower than an upper portion of the gate electrode to expose gate electrode sidewall portions.
摘要翻译：具有梯形间隔物的CMOS器件及其形成方法，具有改进的临界尺寸控制和改善的自对准硅化物形成，所述CMOS器件包括半导体衬底; 栅极结构，包括半导体衬底上的栅极电介质和栅极电介质上的栅电极; 靠近栅极结构两侧的梯形隔板; 其中，所述梯形隔离物在与所述栅极电极的上部相比低于所述栅电极的内边缘处具有最大高度，以露出栅电极侧壁部分。

14. 发明授权

US06787455B2 Bi-layer photoresist method for forming high resolution semiconductor features 失效
标题翻译：用于形成高分辨率半导体特征的双层光致抗蚀剂方法
公开(公告)号：US06787455B2
公开(公告)日：2004-09-07
申请号：US10032353
申请日：2001-12-21
申请人： Ming-Huan Tsai , Hun-Jan Tao , Ju-Wang Hsu , Cheng-Ku Chen
发明人： Ming-Huan Tsai , Hun-Jan Tao , Ju-Wang Hsu , Cheng-Ku Chen
IPC分类号： H01L214763
CPC分类号： G03F7/094 , H01L21/0274 , H01L21/76802
摘要： A method for semiconductor device feature development using a bi-layer photoresist including providing a non-silicon containing photoresist layer over a substrate; providing a silicon containing photoresist over the non-silicon containing photoresist layer; exposing said silicon containing photoresist layer to an activating light source an exposure surface defined by an overlying pattern according to a photolithographic process; developing said silicon containing photoresist layer according to a photolithographic process to reveal a portion the non-silicon containing photoresist layer; and, dry developing said non-silicon containing photoresist layer in a plasma reactor by igniting a plasma from an ambient mixture including at least oxygen, carbon monoxide, and argon.
摘要翻译：一种使用双层光致抗蚀剂的半导体器件特征显影的方法，包括在衬底上提供不含硅的光致抗蚀剂层; 在含硅光致抗蚀剂层上提供含硅光致抗蚀剂; 将所述含硅光致抗蚀剂层暴露于激活光源，根据光刻工艺由覆盖图案限定的曝光表面; 根据光刻工艺显影所述含硅光致抗蚀剂层以露出含有非硅的光致抗蚀剂层的一部分; 以及通过从包括至少氧，一氧化碳和氩的环境混合物点燃等离子体，在等离子体反应器中干燥显影所述不含硅的光致抗蚀剂层。

15. 发明申请

US20050136680A1 Plasma treatment and etching process for ultra-thin dielectric films 失效
标题翻译：超薄电介质膜的等离子体处理和蚀刻工艺
公开(公告)号：US20050136680A1
公开(公告)日：2005-06-23
申请号：US10738237
申请日：2003-12-17
申请人： Ju-Wang Hsu , Yuan-Hung Chiu , Hun-Jan Tao
发明人： Ju-Wang Hsu , Yuan-Hung Chiu , Hun-Jan Tao
IPC分类号： H01L21/311 , H01L21/314 , H01L21/336 , H01L21/768 , H01L21/3205 , H01L21/461 , H01L21/31
CPC分类号： H01L21/0234 , H01L21/0214 , H01L21/0217 , H01L21/02323 , H01L21/31116 , H01L21/3143 , H01L21/76826 , H01L21/76832 , H01L21/76834 , H01L29/6653 , H01L29/6656
摘要： A method for dry etching a dielectric layer including providing a substrate; forming at least one overlying dielectric layer over the substrate; subjecting the at least one overlying layer to a plasma oxidizing process; and, subjecting the at least one overlying layer to a plasma etching process.
摘要翻译：一种用于干蚀刻包括提供衬底的电介质层的方法; 在所述衬底上形成至少一个覆盖介质层; 对所述至少一个上覆层进行等离子体氧化处理; 以及对所述至少一个上覆层进行等离子体蚀刻工艺。

16. 发明授权

US07875547B2 Contact hole structures and contact structures and fabrication methods thereof 有权
标题翻译：接触孔结构及接触结构及其制造方法
公开(公告)号：US07875547B2
公开(公告)日：2011-01-25
申请号：US11035325
申请日：2005-01-12
申请人： Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Peng-Fu Hsu , Hun-Jan Tao
发明人： Ju-Wang Hsu , Jyu-Horng Shieh , Yi-Nien Su , Peng-Fu Hsu , Hun-Jan Tao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76835
摘要： Methods and structures for forming a contact hole structure are disclosed. These methods first form a substantially silicon-free material layer over a substrate. A material layer is formed over the substantially silicon-free material layer. A contact hole is formed within the substantially silicon-free material layer and the material layer without substantially damaging the substrate. In addition, a conductive layer is formed in the contact hole so as to form a contact structure.
摘要翻译：公开了形成接触孔结构的方法和结构。这些方法首先在衬底上形成基本上无硅的材料层。在基本无硅材料层上形成材料层。在基本无硅的材料层和材料层内形成接触孔，而基本上不损坏衬底。此外，在接触孔中形成导电层以形成接触结构。

17. 发明申请

US20060180854A1 Multiple gate field effect transistor structure 有权
标题翻译：多栅场效应晶体管结构
公开(公告)号：US20060180854A1
公开(公告)日：2006-08-17
申请号：US11057423
申请日：2005-02-14
申请人： Ju-Wang Hsu , Jyu-Horng Shieh , Hun-Jan Tao , Chang-Yun Chang , Zhong Xuan , Sheng-Da Liu
发明人： Ju-Wang Hsu , Jyu-Horng Shieh , Hun-Jan Tao , Chang-Yun Chang , Zhong Xuan , Sheng-Da Liu
IPC分类号： H01L31/113
CPC分类号： H01L29/785 , H01L29/66795 , H01L29/78687
摘要： A multiple gate region FET device for forming up to 6 FET devices and method for forming the same, the device including a multiple fin shaped structure comprising a semiconductor material disposed on a substrate; said multiple fin shaped structure comprising substantially parallel spaced apart sidewall portions, each of said sidewall portions comprising major inner and outer surfaces and an upper surface; wherein, each of said surfaces comprises a surface for forming an overlying field effect transistor (FET).
摘要翻译：一种用于形成多达6个FET器件的多栅极区域FET器件及其形成方法，该器件包括多个鳍状结构，其包括设置在衬底上的半导体材料; 所述多个鳍状结构包括基本上平行的间隔开的侧壁部分，每个所述侧壁部分包括主要内表面和外表面以及上表面; 其中，每个所述表面包括用于形成上覆场效应晶体管（FET）的表面。

18. 发明申请

US20060063322A1 Transistor with high dielectric constant gate and method for forming the same 有权
标题翻译：具有高介电常数栅极的晶体管及其形成方法
公开(公告)号：US20060063322A1
公开(公告)日：2006-03-23
申请号：US10946494
申请日：2004-09-21
申请人： Ju-Wang Hsu , Jyu-Horng Shieh , Ju-Chien Chiang
发明人： Ju-Wang Hsu , Jyu-Horng Shieh , Ju-Chien Chiang
IPC分类号： H01L21/8238 , H01L21/302
CPC分类号： H01L29/66553 , H01L21/28079 , H01L21/28088 , H01L29/495 , H01L29/4975 , H01L29/517 , H01L29/518 , H01L29/66583
摘要： A semiconductor device provides a gate structure that includes a conductive portion and a high-k dielectric material formed beneath and along sides of the conductive material. An additional gate dielectric material such as a gate oxide may be used in addition to the high-k dielectric material. The method for forming the structure includes forming an opening in an organic material, forming the high-k dielectric material and a conductive material within the opening and over the organic material then using chemical mechanical polishing to remove the high-k dielectric material and conductive material from regions outside the gate region.
摘要翻译：半导体器件提供了一种栅极结构，其包括在导电材料的下面和沿着导电材料的侧面形成的导电部分和高k电介质材料。除了高k电介质材料之外，可以使用诸如栅极氧化物的附加栅极介电材料。形成结构的方法包括在有机材料中形成开口，在开口内和有机材料上形成高k电介质材料和导电材料，然后使用化学机械抛光去除高k电介质材料和导电材料从门区域外的区域。

19. 发明申请

US20050258499A1 Resistance-reduced semiconductor device and methods for fabricating the same 有权
标题翻译：电阻降低半导体器件及其制造方法
公开(公告)号：US20050258499A1
公开(公告)日：2005-11-24
申请号：US11190913
申请日：2005-07-28
申请人： Yi-Chun Huang , Jyu-Horng Shieh , Ju-Wang Hsu
发明人： Yi-Chun Huang , Jyu-Horng Shieh , Ju-Wang Hsu
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/60 , H01L29/06 , H01L29/76 , H01L31/062
CPC分类号： H01L21/28052 , H01L21/28518 , H01L21/76897 , H01L29/665 , H01L29/6659
摘要： Semiconductor devices and methods for fabricating the same. The semiconductor device includes a resistance-reduced transistor with metallized bilayer overlying source/drain regions and gate electrode thereof. A first dielectric layer with a conductive contact overlies the resistance-reduced transistor. A second dielectric layer having a first conductive feature overlies the first dielectric layer. A third dielectric layer with a second conductive feature overlies the second dielectric layer, forming a conductive pathway down to the top surface of the metallized bilayer over one of the source/drain regions or the gate electrode layer.
摘要翻译：半导体器件及其制造方法。半导体器件包括具有覆盖源极/漏极区域的金属化双层的电阻降低的晶体管及其栅电极。具有导电接触的第一介电层覆盖电阻减小的晶体管。具有第一导电特征的第二介电层覆盖在第一介电层上。具有第二导电特征的第三电介质层覆盖在第二电介质层上，在源极/漏极区域或栅极电极层之一上形成向下至金属化双层的顶表面的导电通路。

20. 发明授权

US06884736B2 Method of forming contact plug on silicide structure 有权
标题翻译：在硅化物结构上形成接触塞的方法
公开(公告)号：US06884736B2
公开(公告)日：2005-04-26
申请号：US10265937
申请日：2002-10-07
申请人： Chii-Ming Wu , Mei-Yun Wang , Chih-Wei Chang , Chin-Hwa Hsieh , Shau-Lin Shue , Chu-Yun Fu , Ju-Wang Hsu , Ming-Huan Tsai , Yuan-Hung Chiu
发明人： Chii-Ming Wu , Mei-Yun Wang , Chih-Wei Chang , Chin-Hwa Hsieh , Shau-Lin Shue , Chu-Yun Fu , Ju-Wang Hsu , Ming-Huan Tsai , Yuan-Hung Chiu
IPC分类号： H01L21/311 , H01L21/60 , H01L21/768 , H01L21/302
CPC分类号： H01L21/76829 , H01L21/31105 , H01L21/31116 , H01L21/76802 , H01L21/76832
摘要： A method of manufacturing a semiconductor device is provided. A semiconductor element is formed on a substrate. The semiconductor element has at least one nickel silicide contact region, an etch stop layer formed over said element, and an insulating layer formed over said etch stop layer. A portion of the etch stop layer immediately over a selected contact region is removed using a process that does not substantially react with the contact region, to form a contact opening. The contact opening is then filled with a conductive material to form a contact.
摘要翻译：提供一种制造半导体器件的方法。半导体元件形成在基板上。半导体元件具有至少一个硅化镍接触区，在所述元件上形成的蚀刻停止层，以及形成在所述蚀刻停止层上的绝缘层。使用基本上不与接触区域反应的方法去除在所选择的接触区域上方的蚀刻停止层的一部分，以形成接触开口。然后用导电材料填充接触开口以形成接触。

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