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11. 发明授权

US07535907B2 TCP engine 有权
标题翻译： TCP引擎
公开(公告)号：US07535907B2
公开(公告)日：2009-05-19
申请号：US11218727
申请日：2005-09-02
申请人： Muhammad R. Hussain , Imran Badr , Faisal Masood , Philip H. Dickinson , Richard E. Kessler , Daniel A. Katz , Michael S. Bertone , Robert A. Sanzone , Thomas F. Hummel , Gregg A. Bouchard
发明人： Muhammad R. Hussain , Imran Badr , Faisal Masood , Philip H. Dickinson , Richard E. Kessler , Daniel A. Katz , Michael S. Bertone , Robert A. Sanzone , Thomas F. Hummel , Gregg A. Bouchard
IPC分类号： H04L12/28 , H04L12/56 , G06F15/16
CPC分类号： H04L69/16 , H04L49/90 , H04L49/9047 , H04L69/163
摘要： A network transport layer accelerator accelerates processing of packets so that packets can be forwarded at wire-speed. To accelerate processing of packets, the accelerator performs pre-processing on a network transport layer header encapsulated in a packet for a connection and performs in-line network transport layer checksum insertion prior to transmitting a packet. A timer unit in the accelerator schedules processing of the received packets. The accelerator also includes a free pool allocator which manages buffers for storing the received packets and a packet order unit which synchronizes processing of received packets for a same connection.
摘要翻译：网络传输层加速器加速数据包的处理，使数据包能够以线速转发。为了加速分组的处理，加速器在封装在用于连接的分组中的网络传输层报头上执行预处理，并且在发送分组之前执行在线网络传输层校验和插入。加速器中的定时器单元调度接收到的分组的处理。加速器还包括一个空闲池分配器，用于管理用于存储接收到的分组的缓冲器，以及分组顺序单元，用于同步用于相同连接的接收分组的处理。

12. 发明授权

US07213087B1 Mechanism to control the allocation of an N-source shared buffer 有权
标题翻译：控制N源共享缓冲区分配的机制
公开(公告)号：US07213087B1
公开(公告)日：2007-05-01
申请号：US09651924
申请日：2000-08-31
申请人： Michael S. Bertone , Richard E. Kessler , David H. Asher , Steve Lang
发明人： Michael S. Bertone , Richard E. Kessler , David H. Asher , Steve Lang
IPC分类号： G06F5/00
CPC分类号： H04L47/39 , H04L49/90
摘要： A method and apparatus for ensuring fair and efficient use of a shared memory buffer. A preferred embodiment comprises a shared memory buffer in a multi-processor computer system. Memory requests from a local processor are delivered to a local memory controller by a cache control unit and memory requests from other processors are delivered to the memory controller by an interprocessor router. The memory controller allocates the memory requests in a shared buffer using a credit-based allocation scheme. The cache control unit and the interprocessor router are each assigned a number of credits. Each must pay a credit to the memory controller when a request is allocated to the shared buffer. If the number of filled spaces in the shared buffer is below a threshold, the buffer immediately returns the credits to the source from which the credit and memory request arrived. If the number of filled spaces in the shared buffer is above a threshold, the buffer holds the credits and returns the credits in a round-robin manner only when a space in the shared buffer becomes free. The number of credits assigned to each source is sufficient to enable each source to deliver an uninterrupted burst of memory requests to the buffer without having to wait for credits to return from the buffer. The threshold is the point when the number of free spaces available in the buffer is equal to the total number of credits assigned to the cache control unit and the interprocessor router.
摘要翻译：一种用于确保公平和有效地使用共享存储器缓冲器的方法和装置。优选实施例包括在多处理器计算机系统中的共享存储器缓冲器。来自本地处理器的存储器请求由高速缓存控制单元传送到本地存储器控制器，并且来自其他处理器的存储器请求由处理器间路由器递送到存储器控制器。存储器控制器使用基于信用的分配方案在共享缓冲器中分配存储器请求。高速缓存控制单元和处理器间路由器分配有多个信用。当请求分配给共享缓冲区时，每个都必须向内存控制器支付抵免额。如果共享缓冲区中的填充空间数量低于阈值，则缓冲区立即将信用返回到信用和存储器请求到达的来源。如果共享缓冲器中的填充空间数目高于阈值，则缓冲器只有当共享缓冲器中的空间变得空闲时才保存信用并以循环方式返回信用。分配给每个源的信用点数量足以使每个源能够将不间断的存储器请求发送到缓冲器，而不必等待信用从缓冲器返回。阈值是缓冲器中可用空间的数量等于分配给缓存控制单元和处理器间路由器的总信用数量的点。

13. 发明授权

US07099913B1 Speculative directory writes in a directory based cache coherent nonuniform memory access protocol 失效
标题翻译：推测目录写入基于目录的缓存相干非均匀内存访问协议
公开(公告)号：US07099913B1
公开(公告)日：2006-08-29
申请号：US09652834
申请日：2000-08-31
申请人： Michael S. Bertone , Richard E. Kessler
发明人： Michael S. Bertone , Richard E. Kessler
IPC分类号： G06F15/16 , G06F12/00 , G06F9/26
CPC分类号： G06F12/0817 , G06F12/0813 , G06F2212/2542 , G06F2212/507
摘要： A system and method is disclosed that reduces the latency of directory updates in a directory based Distributed Shared Memory computer system by speculating the next directory state. The distributed multiprocessing computer system contains a number of processor nodes each connected to main memory. Each main memory may store data that is shared between the processor nodes. A Home processor node for a memory block includes the original data block and a coherence directory for the data block in its main memory. An Owner processor node includes a copy of the original data block in its associated main memory, the copy of the data block residing exclusively in the main memory of the Owner processor node. A Requestor processor node may encounter a read or write miss of the original data block and request the data block from the Home processor node. The Home processor node receives the request for the data block from the Requestor processor node, forwards the request to the Owner processor node for the data block and performs a speculative write of the next directory state to the coherence directory for the data block without waiting for the Owner processor node to respond to the request.
摘要翻译：公开了一种系统和方法，其通过推测下一个目录状态来减少基于目录的分布式共享存储器计算机系统中的目录更新的延迟。分布式多处理计算机系统包含多个处理器节点，每个处理器节点连接到主存储器。每个主存储器可以存储在处理器节点之间共享的数据。用于存储器块的家庭处理器节点包括其主存储器中的数据块的原始数据块和一致性目录。所有者处理器节点包括在其相关联的主存储器中的原始数据块的副本，专用于所有者处理器节点的主存储器中的数据块的副本。请求者处理器节点可能会遇到原始数据块的读或写错，并从家庭处理器节点请求数据块。家庭处理器节点从请求者处理器节点接收对数据块的请求，将该请求转发给数据块的所有者处理器节点，并且将数据块的相干目录的下一个目录状态的推测性写入，而不等待所有者处理器节点响应请求。

14. 发明授权

US06622225B1 System for minimizing memory bank conflicts in a computer system 有权
标题翻译：用于最小化计算机系统中的存储器组冲突的系统
公开(公告)号：US06622225B1
公开(公告)日：2003-09-16
申请号：US09652325
申请日：2000-08-31
申请人： Richard E. Kessler , Michael S. Bertone , Michael C. Braganza , Gregg A. Bouchard , Maurice B. Steinman
发明人： Richard E. Kessler , Michael S. Bertone , Michael C. Braganza , Gregg A. Bouchard , Maurice B. Steinman
IPC分类号： G06F1200
CPC分类号： G06F13/1642
摘要： A computer system includes a memory controller interfacing the processor to a memory system. The memory controller supports a memory system with a plurality of memory devices, with multiple memory banks in each memory device. The memory controller supports simultaneous memory accesses to different memory banks. Memory bank conflicts are avoided by examining each transaction before it is loaded in the memory transaction queue. On a first clock cycle, the new pending memory request is transferred from a pending request queue to a memory mapper. On the subsequent clock cycle, the memory mapper formats the pending memory request into separate signals identifying the DEVICE, BANK, ROW and COLUMN to be accessed by the pending transaction. In the next clock cycle, the DEVICE and BANK signals are compared with every entry in the memory transaction queue to determine if a bank conflict exists. If so, the new memory request is rejected and recycled to the pending request queue.
摘要翻译：计算机系统包括将处理器与存储器系统接口的存储器控制器。存储器控制器支持具有多个存储器设备的存储器系统，每个存储器设备中具有多个存储体。存储器控制器支持对不同存储体的同时存储器访问。通过在每个事务加载到内存事务队列中之前检查每个事务来避免存储器组冲突。在第一个时钟周期中，新的挂起的存储器请求从挂起的请求队列传送到存储器映射器。在随后的时钟周期中，存储器映射器将待处理的存储器请求格式化成单独的信号，标识要由待处理事务访问的DEVICE，BANK，ROW和COLUMN。在下一个时钟周期中，将DEVICE和BANK信号与存储器事务队列中的每个条目进行比较，以确定是否存在存储库冲突。如果是这样，新的内存请求被拒绝并被回收到挂起的请求队列。

15. 发明授权

US09612934B2 Network processor with distributed trace buffers 有权
公开(公告)号：US09612934B2
公开(公告)日：2017-04-04
申请号：US13284289
申请日：2011-10-28
申请人： Bradley D. Dobbie , David H. Asher , Richard E. Kessler
发明人： Bradley D. Dobbie , David H. Asher , Richard E. Kessler
IPC分类号： G06F3/00 , G06F11/34 , G06F13/40 , G06F12/084 , G06F3/16 , G06F1/32 , G06F13/38
CPC分类号： G06F11/3495 , G06F1/3203 , G06F3/16 , G06F11/349 , G06F12/084 , G06F13/385 , G06F13/4022
摘要： A network processor includes a cache and a several groups of processors for accessing the cache. A memory interconnect provides for connecting the processors to the cache via a plurality of memory buses. A number of trace buffers are also connected to the bus and operate to store information regarding commands and data transmitted across the bus. The trace buffers share a common address space, thereby enabling access to the trace buffers as a single entity.

16. 发明授权

US08885480B2 Packet priority in a network processor 有权
标题翻译：网络处理器中的包优先级
公开(公告)号：US08885480B2
公开(公告)日：2014-11-11
申请号：US13277613
申请日：2011-10-20
申请人： Wilson P. Snyder, II , Daniel A. Katz , Richard E. Kessler , Srikanth Gummalla
发明人： Wilson P. Snyder, II , Daniel A. Katz , Richard E. Kessler , Srikanth Gummalla
IPC分类号： H04L1/00 , H04L12/931 , H04L12/825
CPC分类号： H04L49/205 , H04L47/263 , H04L49/505
摘要： In a network processor, a “port-kind” identifier (ID) is assigned to each port. Parsing circuitry employs the port-kind ID to select the configuration information associate with a received packet. The port kind ID can also be stored at a data structure presented to software, along with a larger port number (indicating an interface and/or channel). Based on the port kind ID and extracted information about the packet, a backpressure ID is calculated for the packet. The backpressure ID is implemented to assign a priority to the packet, as well as determine whether a traffic threshold is exceeded, thereby enabling a backpressure signal to limit packet traffic associated with the particular backpressure ID.
摘要翻译：在网络处理器中，为每个端口分配“端口类型”标识符（ID）。解析电路使用端口种类ID来选择与接收到的分组相关联的配置信息。端口种类ID也可以存储在呈现给软件的数据结构以及更大的端口号（指示接口和/或信道）上。根据端口种类ID和关于分组的提取信息，计算分组的背压ID。背压ID被实现以分配分组的优先级，并且确定是否超过流量阈值，从而使背压信号能够限制与特定背压ID相关联的分组流量。

17. 发明申请

US20100023626A1 METHOD AND APPARATUS FOR REDUCING HOST OVERHEAD IN A SOCKET SERVER IMPLEMENTATION 有权
标题翻译：用于减少插座服务器实现中的主机的方法和装置
公开(公告)号：US20100023626A1
公开(公告)日：2010-01-28
申请号：US12574263
申请日：2009-10-06
申请人： Muhammad R. Hussain , Richard E. Kessler , Faisal Masood , Robert A. Sanzone , Imran Badr
发明人： Muhammad R. Hussain , Richard E. Kessler , Faisal Masood , Robert A. Sanzone , Imran Badr
IPC分类号： G06F15/16
CPC分类号： H04L69/16 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9063 , H04L69/162 , H04L69/163 , H04L69/165
摘要： A network application executing on a host system provides a list of application buffers in host memory stored in a queue to a network services processor coupled to the host system. The application buffers are used for storing data transferred on a socket established between the network application and a remote network application executing in a remote host system. Using the application buffers, data received by the network services processor over the network is transferred between the network services processor and the application buffers. After the transfer, a completion notification is written to one of the two control queues in the host system. The completion notification includes the size of the data transferred and an identifier associated with the socket. The identifier identifies a thread associated with the transferred data and the location of the data in the host system.
摘要翻译：在主机系统上执行的网络应用程序将存储在队列中的主机存储器中的应用缓冲器列表提供给耦合到主机系统的网络服务处理器。应用程序缓冲区用于存储在网络应用程序和在远程主机系统中执行的远程网络应用程序之间建立的套接字上传输的数据。使用应用缓冲器，由网络服务处理器通过网络接收的数据在网络服务处理器和应用缓冲器之间传送。在传输之后，将完成通知写入主机系统中的两个控制队列之一。完成通知包括传输的数据的大小和与套接字相关联的标识符。标识符标识与传送的数据相关联的线程和主机系统中数据的位置。

18. 发明授权

US07594081B2 Direct access to low-latency memory 有权
标题翻译：直接访问低延迟内存
公开(公告)号：US07594081B2
公开(公告)日：2009-09-22
申请号：US11024002
申请日：2004-12-28
申请人： Gregg A. Bouchard , David A. Carlson , Richard E. Kessler , Muhammad R. Hussain
发明人： Gregg A. Bouchard , David A. Carlson , Richard E. Kessler , Muhammad R. Hussain
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F9/3824 , G06F9/3885 , G06F12/0888
摘要： A content aware application processing system is provided for allowing directed access to data stored in a non-cache memory thereby bypassing cache coherent memory. The processor includes a system interface to cache coherent memory and a low latency memory interface to a non-cache coherent memory. The system interface directs memory access for ordinary load/store instructions executed by the processor to the cache coherent memory. The low latency memory interface directs memory access for non-ordinary load/store instructions executed by the processor to the non-cache memory, thereby bypassing the cache coherent memory. The non-ordinary load/store instruction can be a coprocessor instruction. The memory can be a low-latency type memory. The processor can include a plurality of processor cores.
摘要翻译：提供内容感知应用处理系统，用于允许定向访问存储在非高速缓冲存储器中的数据，从而绕过高速缓存一致存储器。该处理器包括用于缓存相干存储器的系统接口和用于非高速缓存一致记忆体的低延迟存储器接口。系统接口将由处理器执行的普通加载/存储指令的存储器访问指向高速缓存一致存储器。低延迟存储器接口将由处理器执行的非普通加载/存储指令的存储器访问引导到非高速缓存存储器，从而绕过高速缓存一致存储器。非普通的加载/存储指令可以是协处理器指令。存储器可以是低延迟型存储器。处理器可以包括多个处理器核。

19. 发明授权

US07558925B2 Selective replication of data structures 有权
标题翻译：数据结构的选择性复制
公开(公告)号：US07558925B2
公开(公告)日：2009-07-07
申请号：US11335189
申请日：2006-01-18
申请人： Gregg A. Bouchard , David A. Carlson , Richard E. Kessler
发明人： Gregg A. Bouchard , David A. Carlson , Richard E. Kessler
IPC分类号： G06F12/02
CPC分类号： G06F12/06 , G06F12/0653 , G06F2212/174
摘要： Methods and apparatus are provided for selectively replicating a data structure in a low-latency memory. The memory includes multiple individual memory banks configured to store replicated copies of the same data structure. Upon receiving a request to access the stored data structure, a low-latency memory access controller selects one of the memory banks, then accesses the stored data from the selected memory bank. Selection of a memory bank can be accomplished using a thermometer technique comparing the relative availability of the different memory banks. Exemplary data structures that benefit from the resulting efficiencies include deterministic finite automata (DFA) graphs and other data structures that are loaded (i.e., read) more often than they are stored (i.e., written).
摘要翻译：提供了用于在低延迟存储器中选择性地复制数据结构的方法和装置。存储器包括被配置为存储相同数据结构的复制副本的多个单独存储体。在接收到访问所存储的数据结构的请求时，低延迟存储器访问控制器选择存储体之一，然后从所选存储体存取所存储的数据。可以使用比较不同存储体的相对可用性的温度计技术来实现存储体的选择。受益于所产生的效率的示例性数据结构包括确定性有限自动机（DFA）图和与它们被存储（即，写入）相比更加加载（即读）的其他数据结构。

20. 发明授权

US07024533B2 Mechanism for synchronizing multiple skewed source-synchronous data channels with automatic initialization feature 失效
公开(公告)号：US07024533B2
公开(公告)日：2006-04-04
申请号：US10441451
申请日：2003-05-20
申请人： Richard E. Kessler , Peter J. Bannon , Maurice B. Steinman , Scott E. Breach , Allen J. Baum , Gregg A. Bouchard
发明人： Richard E. Kessler , Peter J. Bannon , Maurice B. Steinman , Scott E. Breach , Allen J. Baum , Gregg A. Bouchard
IPC分类号： G06F12/00
CPC分类号： G06F13/1689
摘要： A computer system has a memory controller that includes read buffers coupled to a plurality of memory channels. The memory controller advantageously eliminates the inter-channel skew caused by memory modules being located at different distances from the memory controller. The memory controller preferably includes a channel interface and synchronization logic circuit for each memory channel. This circuit includes read and write buffers and load and unload pointers for the read buffer. Unload pointer logic generates the unload pointer and load pointer logic generates the load pointer. The pointers preferably are free-running pointers that increment in accordance with two different clock signals. The load pointer increments in accordance with a clock generated by the memory controller but that has been routed out to and back from the memory modules. The unload pointer increments in accordance with a clock generated by the computer system itself Because the trace length of each memory channel may differ, the time that it takes for a memory module to provide read data back to the memory controller may differ for each channel. The “skew” is defined as the difference in time between when the data arrives on the earliest channel and when data arrives on the latest channel. During system initialization, the pointers are synchronized. After initialization, the pointers are used to load and unload the read buffers in such a way that the effects of inner-channel skew is eliminated.

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