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11. 发明申请

US20120261724A1 STACKABLE PROGRAMMABLE PASSIVE DEVICE AND A TESTING METHOD 失效
标题翻译：可堆叠可编程被动设备和测试方法
公开(公告)号：US20120261724A1
公开(公告)日：2012-10-18
申请号：US13529557
申请日：2012-06-21
申请人： Fen Chen , Douglas D. Coolbaugh , Baozhen Li
发明人： Fen Chen , Douglas D. Coolbaugh , Baozhen Li
IPC分类号： H01L23/52 , H01L21/326
CPC分类号： H01L27/101 , H01L23/5252 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable passive device comprising a first node and a second node. A plurality of passive device elements electrically coupled to the first node. A plurality of switches are electrically coupled to at least the second node and selectively coupled to a number of the plurality of passive device elements to provide the programmable passive device with a pre-determined value.
摘要翻译：一种包括第一节点和第二节点的可编程无源设备。电耦合到第一节点的多个无源器件元件。多个开关电耦合到至少第二节点并且选择性地耦合到多个无源器件元件，以向可编程无源器件提供预定值。

12. 发明申请

US20110049674A1 INTERDIGITATED VERTICAL PARALLEL CAPACITOR 有权
标题翻译： INTERDIGITATED垂直并联电容器
公开(公告)号：US20110049674A1
公开(公告)日：2011-03-03
申请号：US12548484
申请日：2009-08-27
申请人： Roger A. Booth, Jr. , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He
发明人： Roger A. Booth, Jr. , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He
IPC分类号： H01L29/92 , H01L21/02
CPC分类号： H01L28/90 , H01L23/5223 , H01L28/86 , H01L2924/0002 , H01L2924/00
摘要： An interdigitated structure may include at least one first metal line, at least one second metal line parallel to the at least one first metal line and separated from the at least one first metal line, and a third metal line contacting ends of the at least one first metal line and separated from the at least one second metal line. The at least one first metal line does not vertically contact any metal via and at least one second metal line may vertically contact at least one metal via. Multiple layers of interdigitated structure may be vertically stacked. Alternately, an interdigitated structure may include a plurality of first metal lines and a plurality of second metal lines, each metal line not vertically contacting any metal via. Multiple instances of interdigitated structure may be laterally replicated and adjoined, with or without rotation, and/or vertically stacked to form a capacitor.
摘要翻译：叉指结构可以包括至少一个第一金属线，平行于至少一个第一金属线并与至少一个第一金属线分离的至少一个第二金属线，以及接触至少一个第一金属线的端部的第三金属线第一金属线并且与所述至少一个第二金属线分离。所述至少一个第一金属线不垂直接触任何金属通孔，并且至少一个第二金属线可垂直接触至少一个金属通孔。多层交错结构可以垂直堆叠。替代地，叉指结构可以包括多个第一金属线和多个第二金属线，每个金属线不垂直地接触任何金属通孔。交错结构的多个实例可以横向复制和邻接，具有或不具有旋转和/或垂直堆叠以形成电容器。

13. 发明授权

US07518215B2 One mask hyperabrupt junction varactor using a compensated cathode contact 有权
标题翻译：一个掩模超破坏结变容二极管使用补偿阴极接触
公开(公告)号：US07518215B2
公开(公告)日：2009-04-14
申请号：US10905486
申请日：2005-01-06
申请人： Douglas D. Coolbaugh , Stephen S. Furkay , Jeffrey B. Johnson , Robert M. Rassel
发明人： Douglas D. Coolbaugh , Stephen S. Furkay , Jeffrey B. Johnson , Robert M. Rassel
IPC分类号： H01L29/93
CPC分类号： H01L29/93
摘要： A semiconductor structure comprising a hyperabrupt junction varactor with a compensated cathode contact as well as a method of fabricating the same are disclosed. The method includes a single implant mask which is used in forming the subcollector/cathode, collector/well and hyperabrupt junction.
摘要翻译：公开了一种半导体结构，其包括具有补偿的阴极接触的超级连接变容二极管及其制造方法。该方法包括用于形成子集电极/阴极，集电极/阱和超破裂结的单个注入掩模。

14. 发明授权

US07511940B2 Formation of metal-insulator-metal capacitor simultaneously with aluminum metal wiring level using a hardmask 失效
标题翻译：金属绝缘体金属电容器与铝金属布线层同时使用硬掩模形成
公开(公告)号：US07511940B2
公开(公告)日：2009-03-31
申请号：US11838939
申请日：2007-08-15
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Natalie B. Feilchenfeld , Michael L. Gautsch , Zhong-Xiang He , Matthew D. Moon , Vidhya Ramachandran , Barbara Waterhouse
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Natalie B. Feilchenfeld , Michael L. Gautsch , Zhong-Xiang He , Matthew D. Moon , Vidhya Ramachandran , Barbara Waterhouse
IPC分类号： H01G4/38
CPC分类号： H01L23/5223 , H01L27/016 , H01L27/0805 , H01L28/40 , H01L2924/0002 , Y10T29/49002 , H01L2924/00
摘要： Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.
摘要翻译：公开了一种制造金属 - 绝缘体 - 金属（MIM）电容器的方法。在该方法中，在下导体层的上方形成电介质层，在电介质层的上方形成上导体层。然后，本发明在上导体层和电介质层之上形成蚀刻停止层，并在蚀刻停止层上形成硬掩模（氧化硅硬掩模，氮化硅硬掩模等）。接下来，在硬掩模上形成光致抗蚀剂，这允许通过光致抗蚀剂蚀刻硬掩模，蚀刻停止层，电介质层和下导体层。

15. 发明授权

US07494912B2 Terminal pad structures and methods of fabricating same 有权
标题翻译：端子焊盘结构及其制造方法
公开(公告)号：US07494912B2
公开(公告)日：2009-02-24
申请号：US11953927
申请日：2007-12-11
申请人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02166 , H01L2224/0401 , H01L2224/05006 , H01L2224/05007 , H01L2224/05022 , H01L2224/05554 , H01L2224/05568 , H01L2224/05572 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/16 , H01L2224/45124 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2224/48 , H01L2224/05552
摘要： Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.
摘要翻译：端子焊盘和制造端子焊盘的方法。所述方法包括在由包括扩散阻挡层的多个电介质层组成的钝化层的内部或与其重叠的导电焊盘下方形成导电扩散阻挡层。所述方法包括减法地形成端子焊盘或通过镶嵌工艺。

16. 发明申请

US20080173981A1 INTEGRATED CIRCUIT (IC) CHIP WITH ONE OR MORE VERTICAL PLATE CAPACITORS AND METHOD OF MAKING THE CAPACITORS 审中-公开
标题翻译：具有一个或多个垂直板电容器的集成电路（IC）芯片和制造电容器的方法
公开(公告)号：US20080173981A1
公开(公告)日：2008-07-24
申请号：US11624712
申请日：2007-01-19
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L27/06 , H01L21/02
CPC分类号： H01L28/91 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： An Integrated Circuit (IC) chip with one or more vertical plate capacitors, each vertical plate capacitor connected to circuits on the IC chip and a method of making the chip capacitors. The vertical plate capacitors are formed with base plate pattern (e.g., damascene copper) on a circuit layer and at least one upper plate layer (e.g., dual damascene copper) above, connected to and substantially identical with the base plate pattern. A vertical pair of capacitor plates are formed by the plate layer and base plate. Capacitor dielectric between the vertical pair of capacitor plates is, at least in part, a high-k dielectric.
摘要翻译：具有一个或多个垂直板电容器的集成电路（IC）芯片，每个垂直板电容器连接到IC芯片上的电路和制造芯片电容器的方法。垂直板电容器在电路层上形成有底板图案（例如，镶嵌铜），以及与基板图案连接并基本相同的至少一个上板层（例如双镶嵌铜）。一对电容器板由板层和底板形成。垂直对电容器板之间的电容电介质至少部分地是高k电介质。

17. 发明申请

US20080132026A1 OPTIMUM PADSET FOR WIRE BONDING RF TECHNOLOGIES WITH HIGH-Q INDUCTORS 失效
标题翻译：用于具有高Q电感器的线束焊接RF技术的最佳焊盘
公开(公告)号：US20080132026A1
公开(公告)日：2008-06-05
申请号：US11551537
申请日：2006-10-20
申请人： Douglas D. Coolbaugh , Zhong-Xiang He , Wolfgang Sauter , Barbara A. Waterhouse
发明人： Douglas D. Coolbaugh , Zhong-Xiang He , Wolfgang Sauter , Barbara A. Waterhouse
IPC分类号： H01L21/02
CPC分类号： H01L24/05 , H01L23/5227 , H01L24/03 , H01L24/45 , H01L2224/02166 , H01L2224/04042 , H01L2224/05624 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48624 , H01L2224/48639 , H01L2224/48644 , H01L2224/48647 , H01L2224/48724 , H01L2224/48739 , H01L2224/48747 , H01L2224/48839 , H01L2224/48844 , H01L2224/48847 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/12042 , H01L2924/1305 , H01L2924/14 , H01L2924/1423 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/30107 , H01L2924/00014 , H01L2224/48824 , H01L2924/00 , H01L2224/48744
摘要： An RF structure that includes an optimum padset for wire bonding and a high performance inductor that contains relatively thick metal inductor wires, both of which are located atop the final interconnect level of an interconnect structure. Specifically, the RF structure includes a dielectric layer having metal inductor wires of a first thickness and a metal bond pad having a major area of a second thickness located on a surface thereof, wherein the first thickness is greater than the second thickness. In the inventive RF structure, the majority of the metal bond pad is thinned for wire bonding, while maintaining the fill metal wire thickness in the other areas of the structure for inductor performance requirements, such as, for example, low resistivity. Methods for fabricating the aforementioned RF structure are also provided.
摘要翻译： RF结构包括用于引线键合的最佳焊盘和包含相对较厚的金属电感器导线的高性能电感器，两者都位于互连结构的最终互连级别的顶部。具体地，RF结构包括具有第一厚度的金属电感器线和位于其表面上的具有第二厚度的主要面积的金属接合焊盘的电介质层，其中第一厚度大于第二厚度。在本发明的RF结构中，大部分金属焊盘被薄化以进行引线接合，同时保持结构的其它区域中的填充金属线厚度用于电感器性能要求，例如低电阻率。还提供了制造上述RF结构的方法。

18. 发明授权

US07382055B2 Integrated thin-film resistor with direct contact 有权
标题翻译：集成薄膜电阻直接接触
公开(公告)号：US07382055B2
公开(公告)日：2008-06-03
申请号：US11846595
申请日：2007-08-29
申请人： Eric M. Coker , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Matthew D. Moon , Anthony K. Stamper
发明人： Eric M. Coker , Douglas D. Coolbaugh , Ebenezer E. Eshun , Zhong-Xiang He , Matthew D. Moon , Anthony K. Stamper
IPC分类号： H01L29/40
CPC分类号： H01L27/016
摘要： A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.
摘要翻译：适用于灵活集成的BEOL薄膜电阻依赖于第一层ILD。 ILD的第一层的厚度和电阻器厚度相结合，以匹配所涉及的层中的通孔的标称设计厚度。第二层ILD匹配电阻器厚度，并平坦化到电阻器的顶表面。 ILD的第三层具有等于该层上互连的标称值的厚度。同时形成用于与电阻器接触的双镶嵌互连孔和孔，电阻器中的蚀刻停止上盖层保护电阻层，同时形成双镶嵌孔中的通孔。

19. 发明申请

US20080122574A1 POLYSILICON CONTAINING RESISTOR WITH ENHANCED SHEET RESISTANCE PRECISION AND METHOD FOR FABRICATION THEREOF 失效
标题翻译：具有增强型电阻精度的多晶硅电容器及其制造方法
公开(公告)号：US20080122574A1
公开(公告)日：2008-05-29
申请号：US11458494
申请日：2006-07-19
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , John E. Florkey , Robert M. Rassel , Kunal Vaed
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Ebenezer E. Eshun , John E. Florkey , Robert M. Rassel , Kunal Vaed
IPC分类号： H01C1/06 , H01L21/20
CPC分类号： H01L27/0802 , H01L21/26513 , H01L28/20
摘要： A polysilicon containing resistor includes: (1) a p dopant selected from the group consisting of boron and boron difluoride; and (2) an n dopant selected from the group consisting of arsenic and phosphorus. Each of the p dopant and the n dopant has a dopant concentration from about 1e18 to about 1e21 dopant atoms per cubic centimeter. A method for forming the polysilicon resistor uses corresponding implant doses from about 1e14 to about 1e16 dopant ions per square centimeter. The p dopant and the n dopant may be provided simultaneously or sequentially. The method provides certain polysilicon resistors with a sheet resistance percentage standard deviation of less than about 1.5%, for a polysilicon resistor having a sheet resistance from about 100 to about 5000 ohms per square.
摘要翻译：含多晶硅的电阻器包括：（1）选自硼和二氟化硼的p掺杂剂; 和（2）选自砷和磷的n掺杂剂。 p掺杂剂和n掺杂剂中的每一个掺杂剂的掺杂剂浓度从每立方厘米约1e18至约1e21掺杂剂原子。用于形成多晶硅电阻器的方法使用相对于每平方厘米约1e14至约1e16掺杂剂离子的注入剂量。 p掺杂剂和n掺杂剂可以同时或顺序地提供。对于具有约100至约5000欧姆/平方的薄层电阻的多晶硅电阻器，该方法提供某些多晶硅电阻器的薄层电阻百分比标准偏差小于约1.5％。

20. 发明授权

US07301752B2 Formation of metal-insulator-metal capacitor simultaneously with aluminum metal wiring level using a hardmask 有权
标题翻译：金属绝缘体金属电容器与铝金属布线层同时使用硬掩模形成
公开(公告)号：US07301752B2
公开(公告)日：2007-11-27
申请号：US10709907
申请日：2004-06-04
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Natalie B. Feilchenfeld , Michael L. Gautsch , Zhong-Xiang He , Matthew D. Moon , Vidhya Ramachandran , Barbara Waterhouse
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Natalie B. Feilchenfeld , Michael L. Gautsch , Zhong-Xiang He , Matthew D. Moon , Vidhya Ramachandran , Barbara Waterhouse
IPC分类号： H01G4/38
CPC分类号： H01L23/5223 , H01L27/016 , H01L27/0805 , H01L28/40 , H01L2924/0002 , Y10T29/49002 , H01L2924/00
摘要： Disclosed is a method of fabricating a metal-insulator-metal (MIM) capacitor. In this method, a dielectric layer is formed above a lower conductor layer and an upper conductor layer is formed above the dielectric layer. The invention then forms an etch stop layer above the upper conductor layer and the dielectric layer, and forms a hardmask (silicon oxide hardmask, a silicon nitride hardmask, etc.) over the etch stop layer. Next, a photoresist is patterned above the hardmask, which allows the hardmask, the etch stop layer, the dielectric layer, and the lower conductor layer to be etched through the photoresist.
摘要翻译：公开了一种制造金属 - 绝缘体 - 金属（MIM）电容器的方法。在该方法中，在下导体层的上方形成电介质层，在电介质层的上方形成上导体层。然后，本发明在上导体层和电介质层之上形成蚀刻停止层，并在蚀刻停止层上形成硬掩模（氧化硅硬掩模，氮化硅硬掩模等）。接下来，在硬掩模上形成光致抗蚀剂，这允许通过光致抗蚀剂蚀刻硬掩模，蚀刻停止层，电介质层和下导体层。

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