专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07884696B2 Lead frame-based discrete power inductor 有权
公开(公告)号：US07884696B2
公开(公告)日：2011-02-08
申请号：US12011489
申请日：2008-01-25
申请人： François Hébert , Tao Feng , Xiaotian Zhang , Jun Lu
发明人： François Hébert , Tao Feng , Xiaotian Zhang , Jun Lu
IPC分类号： H01F5/00
CPC分类号： H01F17/062
摘要： A lead frame-based discrete power inductor is disclosed. The power inductor includes top and bottom lead frames, the leads of which form a coil around a single closed-loop magnetic core. The coil includes interconnections between inner and outer contact sections of the top and bottom lead frames, the magnetic core being sandwiched between the top and bottom lead frames. Ones of the leads of the top and bottom lead frames have a generally non-linear, stepped configuration such that the leads of the top lead frame couple adjacent leads of the bottom lead frame about the magnetic core to form the coil.

12. 发明授权

US07868431B2 Compact power semiconductor package and method with stacked inductor and integrated circuit die 有权
标题翻译：紧凑型功率半导体封装和堆叠电感和集成电路管芯的方法
公开(公告)号：US07868431B2
公开(公告)日：2011-01-11
申请号：US12391251
申请日：2009-02-23
申请人： Tao Feng , Xiaotian Zhang , François Hébert , Ming Sun
发明人： Tao Feng , Xiaotian Zhang , François Hébert , Ming Sun
IPC分类号： H01L23/495 , H01L21/44 , H01L21/48 , H01L21/50 , H01F5/00
CPC分类号： H01L23/49861 , H01F17/0033 , H01F2027/2814 , H01L21/4832 , H01L21/563 , H01L23/495 , H01L23/4951 , H01L23/49548 , H01L23/49816 , H01L23/49827 , H01L24/48 , H01L24/49 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/48091 , H01L2224/49175 , H01L2924/00014 , H01L2924/01079 , H01L2924/14 , H01L2924/15311 , H01L2924/19107 , H01L2924/30107 , H01L2224/05599 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A power semiconductor package is disclosed with high inductance rating while exhibiting a reduced foot print. It has a bonded stack of power IC die at bottom, a power inductor at top and a circuit substrate, made of leadframe or printed circuit board, in the middle. The power inductor has a inductor core of closed magnetic loop. The circuit substrate has a first number of bottom half-coil forming conductive elements beneath the inductor core. A second number of top half-coil forming conductive elements, made of bond wires, three dimensionally formed interconnection plates or upper leadframe leads, are located atop the inductor core with both ends of each element connected to respective bottom half-coil forming conductive elements to jointly form an inductive coil enclosing the inductor core. A top encapsulant protectively encases the inductor core, the top half-coil forming conductive elements, the bottom half-coil forming conductive elements and the circuit substrate.
摘要翻译：公开了一种功率半导体封装，其具有高电感额定值，同时显示出减少的脚印。底部有一个电源IC芯片，顶部有一个功率电感器和一个由引线框或印刷电路板制成的电路基板。功率电感器具有闭合磁环的电感芯。电路衬底具有在电感器芯下方形成导电元件的第一数量的底部半线圈。由接合线，三维形成的互连板或上引线框引线构成的第二数量的上半线圈形成导电元件位于电感器芯的顶部，每个元件的两端连接到形成导电元件的相应底部半线圈，共同形成围绕电感器芯的感应线圈。顶部密封剂保护性地封装电感器芯，顶部半线圈形成导电元件，底部半线圈形成导电元件和电路衬底。

13. 发明申请

US20090160045A1 WAFER LEVEL CHIP SCALE PACKAGING 有权
标题翻译： WAFER LEVEL CHIP SCALE包装
公开(公告)号：US20090160045A1
公开(公告)日：2009-06-25
申请号：US11963690
申请日：2007-12-21
申请人： Ming Sun , Tao Feng , Francois Hebert , Yueh-Se Ho
发明人： Ming Sun , Tao Feng , Francois Hebert , Yueh-Se Ho
IPC分类号： H01L23/06 , H01L21/304
CPC分类号： H01L21/6835 , H01L21/568 , H01L24/02 , H01L24/11 , H01L24/17 , H01L2221/68354 , H01L2224/0231 , H01L2224/0233 , H01L2224/0239 , H01L2224/0401 , H01L2224/04042 , H01L2224/13099 , H01L2224/16 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01072 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/05042 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H01L2924/00
摘要： A method for making back-to-front electrical connections in a wafer level chip scale packaging process is disclosed. A wafer containing a plurality of semiconductor chips is mounted on a package substrate. Each semiconductor chip in the plurality includes one or more electrodes on an exposed back side. Scribe lines between two or more adjacent chips on the wafer are removed to form relatively wide gaps. A conductive material is applied to the back side of the semiconductor chips and in the gaps. The conductive material in the gaps between two or more of the chips is then cut through leaving conductive material on the back side and on side walls of the two or more chips. As a result, the conductive material provides an electrical connection from the electrode on the back side of the chip to the front side of the chip.
摘要翻译：公开了一种用于在晶片级芯片级封装工艺中进行背对背电连接的方法。将包含多个半导体芯片的晶片安装在封装基板上。多个半导体芯片包括暴露背面的一个或多个电极。去除晶片上的两个或更多个相邻芯片之间的划痕线以形成较宽的间隙。将导电材料施加到半导体芯片的背面和间隙中。然后通过在两个或更多个芯片的背侧和侧壁上留下导电材料来切割两个或更多个芯片之间的间隙中的导电材料。结果，导电材料提供从芯片的背面上的电极到芯片的前侧的电连接。

14. 发明申请

US20090020854A1 Process of forming ultra thin wafers having an edge support ring 有权
标题翻译：形成具有边缘支撑环的超薄晶片的工艺
公开(公告)号：US20090020854A1
公开(公告)日：2009-01-22
申请号：US11880455
申请日：2007-07-20
申请人： Tao Feng , Sung-Shan Tai
发明人： Tao Feng , Sung-Shan Tai
IPC分类号： H01L21/304 , B24B1/00
CPC分类号： H01L21/02035 , H01L21/02013 , H01L21/3043 , H01L2924/0002 , Y10S438/977 , H01L2924/00
摘要： A process of forming ultra thin wafers having an edge support ring is disclosed. The process provides an edge support ring having an angled inner wall compatible with spin etch processes.
摘要翻译：公开了一种形成具有边缘支撑环的超薄晶片的工艺。该工艺提供了具有与旋转蚀刻工艺兼容的成角度的内壁的边缘支撑环。

15. 发明授权

US07373618B1 Method and system for selection and replacement of subcircuits in equivalence checking 有权
标题翻译：在等效检查中选择和更换子电路的方法和系统
公开(公告)号：US07373618B1
公开(公告)日：2008-05-13
申请号：US11271269
申请日：2005-11-10
申请人： Kei-Yong Khoo , Tao Feng , Debjyoti Paul , Chih-Chang Lin
发明人： Kei-Yong Khoo , Tao Feng , Debjyoti Paul , Chih-Chang Lin
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A system, method, computer program, and article of manufacture for generating a golden circuit including datapath components for equivalence checking of synthesized revised circuit. The method includes generating a set of static, dynamic and derived candidates for the datapath component subcircuit, evaluating the similarity degree for each candidate in relation to the revised circuits and selecting one candidate for implementation in the golden circuit. As a result, the subcircuit of datapath component in the golden circuit is replaced with the subcircuit which is more similar to the revised circuit to improve the efficiency of the equivalence checking.
摘要翻译：一种用于产生包含用于合成修正电路的等效检查的数据通路组件的黄金电路的系统，方法，计算机程序和制造。该方法包括为数据通路组件子电路生成一组静态，动态和导出候选，评估每个候选人相对于修订电路的相似度，并选择一个在黄金电路中实现的候选项。结果，黄金电路中的数据路径分量的子电路被更换类似于修正电路的子电路所取代，以提高等效性检查的效率。

16. 发明申请

US20160089795A1 A ROTARY JOINT OF A ROBOT AND THE ROBOT INCLUDING THE SAME 有权
标题翻译：机器人的旋转接头和包括它的机器人
公开(公告)号：US20160089795A1
公开(公告)日：2016-03-31
申请号：US14786275
申请日：2013-06-17
申请人： Xiaodong Cao , Tao Feng , Zhu Zhu , ABB TECHNOLOGY LTD.
发明人： Xiaodong Cao , Tao Feng , Zhu Zhu
IPC分类号： B25J19/00 , B25J17/00
CPC分类号： B25J19/0041 , B25J17/00 , B25J19/0029 , H02G11/02
摘要： A rotary joint, a hollow gear and a hollow wiring unit having a first flexible printed circuit board therein, to allow hose to pass through both the hollow gear and the hollow wiring unit. A robot includes the rotary joint.
摘要翻译：旋转接头，中空齿轮和中空配线单元，其中具有第一柔性印刷电路板，以允许软管通过中空齿轮和中空配线单元。机器人包括旋转接头。

17. 发明申请

US20140129843A1 Methods and Apparatus for Managing Service Access Using a Touch-Display Device Integrated with Fingerprint Imager 审中-公开
标题翻译：使用与指纹成像仪集成的触摸显示设备来管理服务访问的方法和装置
公开(公告)号：US20140129843A1
公开(公告)日：2014-05-08
申请号：US13667235
申请日：2012-11-02
申请人： Weidong Shi , Tao Feng , Yang Lu
发明人： Weidong Shi , Tao Feng , Yang Lu
IPC分类号： G06F21/32
CPC分类号： G06F21/32
摘要： The present invention with an apparatus enables biometric based access control to services and/or resources that comprises a crypto processor, a biometric processor, a fingerprint controller, a frame hash engine, a display repeater and/or a display controller, a touch-panel controller and a biometric touch-display panel. The frame hash engine and/or the display controller computes a frame hash of the frame displayed on the biometric touch-display panel. When a fingerprint is captured, in the registration scenario, the biometric processor extracts biometric identity and stores it in a service biometric credential repository identity, and submits a registration proof to the server; in the service access scenarios, the biometric processor verifies user identity by matching fingerprint, and submits an access identity to the server.
摘要翻译：具有装置的本发明使得能够对包括密码处理器，生物测定处理器，指纹控制器，帧散列引擎，显示中继器和/或显示控制器的服务和/或资源进行基于生物特征的访问控制，触摸面板控制器和生物识别触摸显示面板。帧散列引擎和/或显示控制器计算显示在生物测定触摸显示面板上的帧的帧散列。当捕获指纹时，在注册场景中，生物识别处理器提取生物识别身份并将其存储在服务生物认证证书库身份中，并向服务器提交注册证明; 在服务访问场景中，生物特征处理器通过匹配指纹验证用户身份，并向服务器提交访问标识。

18. 发明授权

US08716063B2 Wafer level chip scale package and process of manufacture 有权
标题翻译：晶圆级芯片级封装及制造工艺
公开(公告)号：US08716063B2
公开(公告)日：2014-05-06
申请号：US13007356
申请日：2011-01-14
申请人： Tao Feng , François Hébert , Ming Sun , Yueh-Se Ho
发明人： Tao Feng , François Hébert , Ming Sun , Yueh-Se Ho
IPC分类号： H01L21/00
CPC分类号： H01L29/7827 , H01L21/76898 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/81 , H01L29/0657 , H01L29/41741 , H01L29/4175 , H01L29/45 , H01L29/49 , H01L29/7802 , H01L2224/02371 , H01L2224/03464 , H01L2224/0347 , H01L2224/0401 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/06181 , H01L2224/06183 , H01L2224/16225 , H01L2224/16227 , H01L2224/81815 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.
摘要翻译：封装了功率晶圆级芯片级封装（CSP）和制造工艺。功率晶片级芯片级封装包括位于器件一侧的所有源极，栅极和漏极，便于用焊膏安装到印刷电路板（PCB）。

19. 发明申请

US20140076846A1 METHOD AND APPARATUS FOR ULTRA THIN WAFER BACKSIDE PROCESSING 有权
标题翻译：用于超薄薄膜后处理的方法和装置
公开(公告)号：US20140076846A1
公开(公告)日：2014-03-20
申请号：US13621289
申请日：2012-09-16
申请人： Tao Feng , Ming Sun
发明人： Tao Feng , Ming Sun
IPC分类号： B32B38/00
CPC分类号： B32B38/0012 , B32B2038/0016 , B32B2038/0092 , B32B2309/10 , B32B2457/14 , H01L21/67132 , H01L21/6836 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2221/68327 , H01L2221/68336 , H01L2221/6834 , H01L2224/0345 , H01L2224/0401 , H01L2224/0556 , H01L2224/05568 , H01L2224/06183 , H01L2224/131 , H01L2224/16105 , H01L2224/16238 , H01L2224/17051 , H01L2224/17104 , H01L2224/81192 , H01L2224/81815 , H01L2224/97 , H01L2924/00014 , H01L2924/00012 , H01L2224/03 , H01L2924/014 , H01L2224/05552
摘要： A method and apparatus for ultra thin wafer backside processing are disclosed. The apparatus includes an outer ring holding a high temperature grinding and/or dicing tape to form a support structure. An ultra thin wafer or diced wafer is adhered to the tape within the ring for wafer backside processing. The wafer backside processing includes ion implantation, annealing, etching, sputtering and evaporation while the wafer is in the support structure. Alternative uses of the support structure are also disclosed including the fabrication of dies having metalized side walls.
摘要翻译：公开了一种用于超薄晶片背面处理的方法和装置。该装置包括保持高温研磨和/或切割胶带以形成支撑结构的外圈。超薄晶片或切片晶片粘附在环内用于晶片背面处理的带子上。晶片背面处理包括离子注入，退火，蚀刻，溅射和蒸发，而晶片处于支撑结构中。还公开了支撑结构的替代用途，包括制造具有金属化侧壁的模具。

20. 发明申请

US20130287272A1 Methods and Apparatus of Integrating Fingerprint Imagers with Touch Panels and Displays 审中-公开
标题翻译：将指纹成像器与触摸屏和显示器集成的方法和装置
公开(公告)号：US20130287272A1
公开(公告)日：2013-10-31
申请号：US13459207
申请日：2012-04-29
申请人： Yang Lu , Weidong Shi , Tao Feng , Ziyi Liu
发明人： Yang Lu , Weidong Shi , Tao Feng , Ziyi Liu
IPC分类号： G06K9/62 , G06F3/041
CPC分类号： G06F3/041 , G06F21/32 , G06K9/00013 , H04M1/66 , H04M2250/22
摘要： The present invention provides systems and methods of an apparatus that comprises a layer of fingerprint imagers, an addressing circuit, a fingerprint controller, an electronic storage devices, a layer of touch panel and a display panel. The touch panel behind the layer of fingerprint imagers can sense touch position when touched. The specific fingerprint imagers can be activated according to the touch panel coordinates when touched by a user. After fingerprint is captured, the system evaluates quality of the captured fingerprint and admits fingerprint for recognition when its quality is above a threshold value. User of a computing system can be accepted or rejected based on the comparison between the captured fingerprint and an authorized fingerprint list.
摘要翻译：本发明提供一种装置的系统和方法，该装置包括指纹成像器层，寻址电路，指纹控制器，电子存储装置，触摸屏层和显示面板。指纹成像器层后面的触摸面板可以在触摸时感知触摸位置。当用户触摸时，可以根据触摸面板的坐标激活特定的指纹成像器。捕获指纹后，系统评估捕获的指纹的质量，并在其质量高于阈值时承认指纹进行识别。可以基于捕获的指纹和授权指纹列表之间的比较来接受或拒绝计算系统的用户。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式