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11. 发明授权

US08400866B2 Voltage boosting in MRAM current drivers 有权
标题翻译： MRAM电流驱动器的升压电压
公开(公告)号：US08400866B2
公开(公告)日：2013-03-19
申请号：US12852335
申请日：2010-08-06
申请人： Krishnakumar Mani , Anil Gupta
发明人： Krishnakumar Mani , Anil Gupta
IPC分类号： G11C8/00
CPC分类号： G11C11/16 , G11C5/145 , G11C8/08
摘要： A current driving mechanism for a magnetic memory device, comprising: a) a current driver circuit; and b) a current decoding block coupled to the current driver circuit, wherein the current decoding block comprises a transistor (M18) to control driver currents from the current driver circuit, and wherein the transistor (M18) has a smaller form factor then otherwise possible by virtue of maintaining a gate thereof at a negative voltage.
摘要翻译：一种用于磁存储器件的电流驱动机构，包括：a）电流驱动电路; 以及b）耦合到当前驱动器电路的当前解码块，其中当前解码块包括用于控制来自当前驱动器电路的驱动器电流的晶体管（M18），并且其中晶体管（M18）具有较小的形状因数，否则可能由于其栅极保持在负电压。

12. 发明授权

US07688643B2 Device and method for controlling solid-state memory system 失效
标题翻译：用于控制固态存储器系统的装置和方法
公开(公告)号：US07688643B2
公开(公告)日：2010-03-30
申请号：US10809061
申请日：2004-03-24
申请人： Karl M. J. Lofgren , Jeffrey Donald Stai , Anil Gupta , Robert D. Norman , Sanjay Mehrotra
发明人： Karl M. J. Lofgren , Jeffrey Donald Stai , Anil Gupta , Robert D. Norman , Sanjay Mehrotra
IPC分类号： G11C16/04 , G06F13/00
CPC分类号： G11C5/04 , G06F3/0613 , G06F3/0659 , G06F3/0679 , G06F12/0676 , G06F13/1668 , G06F13/4243 , G11C5/00 , G11C5/066 , G11C8/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A memory system includes an array of solidstate memory devices which are in communication with and under the control of a controller module via a device bus with very few lines. This forms an integrated-circuit mass storage system which is contemplated to replace a mass storage system such as a disk drive memory in a computer system. Command, address and data information are serialized into component strings and multiplexed before being transferred between the controller module and the array of memory devices. The serialized information are is accompanied by a control signal to help sort out the multiplexed components. Each memory device in the array is mounted on a multi-bit mount and assigned an array address by it an array mount. An A memory device is selected by an appropriate address broadcast over the device bus, without requiring the usual dedicated select signal. A reserved array particular mount multi-bit configuration is used to unconditionally select the device mounted thereon. A reserved predefined address broadcast over the device bus deselects all previously selected memory devices. Read performance is enhanced by a read streaming technique in which while a current chunk of data is being serialized and shifted out of the memory subsystem devices to the controller module, the controller module is also setting up the address for the next chunk of data to begin to address the memory system.
摘要翻译：存储器系统包括固态存储器件的阵列，其经由具有极少行的器件总线与控制器模块通信并处于控制器模块的控制之下。这形成了集成电路大容量存储系统，其被设想来替代大容量存储系统，例如计算机系统中的磁盘驱动器存储器。命令，地址和数据信息被串行化为组件字符串，并在控制器模块和存储器件阵列之间传输之前被多路复用。串行化信息伴随着一个控制信号，以帮助整理复用的组件。阵列中的每个存储器件都安装在多位安装上，并通过阵列安装分配阵列地址。通过在设备总线上广播的适当地址来选择存储器件，而不需要通常的专用选择信号。使用保留阵列特定安装多位配置来无条件地选择安装在其上的装置。通过设备总线广播的保留的预定义地址取消选择所有先前选择的存储设备。读取性能通过读取流技术得到增强，其中当当前块的数据被序列化并从存储器子系统设备移出到控制器模块时，控制器模块还设置下一个数据块开始的地址寻址内存系统。

13. 发明申请

US20080195516A1 Method for creating and delivering customized compliance information 审中-公开
标题翻译：创建和提供定制化合规信息的方法
公开(公告)号：US20080195516A1
公开(公告)日：2008-08-14
申请号：US12011588
申请日：2008-01-28
申请人： Jeffrey B. Levering , Alex Magary , Craig LeClair , Larry Kunz , Anil Gupta , Brigitte Tuller , Garett Wiley
发明人： Jeffrey B. Levering , Alex Magary , Craig LeClair , Larry Kunz , Anil Gupta , Brigitte Tuller , Garett Wiley
IPC分类号： G06Q40/00
CPC分类号： G06Q40/04 , G06Q30/00 , G06Q30/018 , G06Q40/00 , G06Q40/06 , G06Q40/12
摘要： A method and system to create personalized investor information packages, based on investor information, to be delivered to the investor to satisfy both compliance regulations and investor preferences. The method and system may deliver information in a paper or electronic format.
摘要翻译：一种基于投资者信息创建个性化投资者信息包的方法和系统，将交付给投资者以满足合规规定和投资者偏好。该方法和系统可以以纸或电子格式传送信息。

14. 发明授权

US07317630B2 Nonvolatile semiconductor memory apparatus 有权
标题翻译：非易失性半导体存储装置
公开(公告)号：US07317630B2
公开(公告)日：2008-01-08
申请号：US11182374
申请日：2005-07-15
申请人： Nicola Telecco , Vijay P. Adusumilli , Anil Gupta , Edward Hui , Steven J. Schumann
发明人： Nicola Telecco , Vijay P. Adusumilli , Anil Gupta , Edward Hui , Steven J. Schumann
IPC分类号： G11C5/06
CPC分类号： G11C7/10 , H01L2224/05553 , H01L2224/48137 , H01L2224/49175
摘要： A nonvolatile memory apparatus includes a separate controller circuit and memory circuit. The controller circuit is fabricated on a first integrated circuit chip. The controller circuit includes a plurality of charge pump circuits, a system interface logic circuit, a memory control logic circuit, and one or more analog circuits. The memory circuit is fabricated on a second integrated circuit chip and includes a column decoder, a row decoder, a control register, and a data register. A memory-controller interface area includes a first plurality of die bond pads on the first integrated circuit chip and a second plurality of die bond pads on the second integrated circuit chip such that the first and second integrated circuit chips may be die-bonded together. A single controller circuit may interface with a plurality of memory circuits, thus further reducing overall costs as each memory circuit does not require a dedicated controller circuit.
摘要翻译：非易失性存储装置包括单独的控制器电路和存储器电路。控制器电路制造在第一集成电路芯片上。控制器电路包括多个电荷泵电路，系统接口逻辑电路，存储器控制逻辑电路和一个或多个模拟电路。存储器电路制造在第二集成电路芯片上，并且包括列解码器，行解码器，控制寄存器和数据寄存器。存储器控制器接口区域包括第一集成电路芯片上的第一多个管芯接合焊盘和第二集成电路芯片上的第二多个管芯接合焊盘，使得第一和第二集成电路芯片可以芯片结合在一起。单个控制器电路可以与多个存储器电路接口，从而进一步降低总体成本，因为每个存储器电路不需要专用控制器电路。

15. 发明申请

US20050125316A1 Method for creating and delivering customized compliance information 审中-公开
标题翻译：创建和提供定制化合规信息的方法
公开(公告)号：US20050125316A1
公开(公告)日：2005-06-09
申请号：US10877904
申请日：2004-06-25
申请人： Jeffrey Levering , Alex Magary , Craig LeClair , Larry Kunz , Anil Gupta , Brigitte Tuller , Garett Wiley
发明人： Jeffrey Levering , Alex Magary , Craig LeClair , Larry Kunz , Anil Gupta , Brigitte Tuller , Garett Wiley
IPC分类号： G06F20060101 , G06Q40/00 , G06F17/60
CPC分类号： G06Q40/04 , G06Q30/00 , G06Q30/018 , G06Q40/00 , G06Q40/06 , G06Q40/12
摘要： A method and system to create personalized investor information packages, based on investor information, to be delivered to the investor to satisfy both compliance regulations and investor preferences. The method and system may deliver information in a paper or electronic format.
摘要翻译：一种基于投资者信息创建个性化投资者信息包的方法和系统，将交付给投资者以满足合规规定和投资者偏好。该方法和系统可以以纸或电子格式传送信息。

16. 发明授权

US6161197A Method and system for controlling a bus with multiple system hosts 失效
标题翻译：用多台系统主机控制总线的方法和系统
公开(公告)号：US6161197A
公开(公告)日：2000-12-12
申请号：US079130
申请日：1998-05-14
申请人： Mark Lanus , Charles Christopher Hill , Anil Gupta
发明人： Mark Lanus , Charles Christopher Hill , Anil Gupta
IPC分类号： G06F13/14 , G06F11/20 , G06F15/177 , G06F11/16
CPC分类号： G06F11/2007 , G06F11/20 , G06F11/2023
摘要： In a method for swapping a system host board (150,160,170,180), when a failure is detected on a first system processor board (150), control of a first CompactPCI bus (110) is transferred from a first system processor board system host (154) to a first bridge board system host(164). In an active/standby configuration, control of a second CompactPCI bus (120) is transferred from a second bridge board system host (184) to a second system processor board system host (174), and control of the devices on the first CompactPCI bus (110) and second CompactPCI bus (120) is transferred from the first system processor (152) to the second system processor (172) without resetting any devices on the system.
摘要翻译：在用于交换系统主机板（150,160,170,180）的方法中，当在第一系统处理器板（150）上检测到故障时，从第一系统处理器板系统主机（154）传送第一CompactPCI总线（110）的控制，到第一桥板系统主机（164）。在主动/待机配置中，第二CompactPCI总线（120）的控制从第二桥接板系统主机（184）传送到第二系统处理器板系统主机（174），并且控制第一CompactPCI总线上的设备（110）和第二CompactPCI总线（120）从第一系统处理器（152）传送到第二系统处理器（172），而不重置系统上的任何设备。

17. 发明授权

US6118705A Page mode erase in a flash memory array 失效
公开(公告)号：US6118705A
公开(公告)日：2000-09-12
申请号：US42244
申请日：1998-03-13
申请人： Anil Gupta , Steven J. Schumann
发明人： Anil Gupta , Steven J. Schumann
IPC分类号： G11C16/02 , G11C11/40 , G11C16/00 , G11C16/04 , G11C16/16
CPC分类号： G11C16/16
摘要： In a sector in a flash memory array PAGE ERASE and MULTIPLE PAGE ERASE modes of operation are provided. In the PAGE ERASE and MULTIPLE PAGE ERASE modes of operation, a preferred tunneling potential of approximately -10 Volts is applied to the gates of the flash memory cells on the row or rows being selected for erasure, and the bitlines connected to the drains of the flash memory cells are driven to a preferred voltage of approximately 6.5 Volts. To reduce the unintended erasure of memory cells in rows other than the selected row or rows, a preferred bias voltage of approximately 1 to 2 Volts is applied to the gates of all the flash memory cells in the rows other than the selected row or rows.

18. 发明授权

US6081447A Wear leveling techniques for flash EEPROM systems 失效
公开(公告)号：US6081447A
公开(公告)日：2000-06-27
申请号：US262813
申请日：1999-03-05
申请人： Karl M. J. Lofgren , Robert D. Norman , Gregory B. Thelin , Anil Gupta
发明人： Karl M. J. Lofgren , Robert D. Norman , Gregory B. Thelin , Anil Gupta
IPC分类号： G11C8/12 , G11C16/34 , G11C16/00
CPC分类号： G11C16/3495 , G06F12/0246 , G11C16/349 , G11C8/12 , G06F2212/1036 , G06F2212/7211
摘要： A mass storage system made of flash electrically erasable and programmable read only memory ("EEPROM") cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experienced by the memory banks in order to extend the service lifetime of the memory system. Since this type of memory cell becomes unusable after a finite number of erase and rewrite cycles, although in the tens of thousands of cycles, uneven use of the memory banks is avoided so that the entire memory does not become inoperative because one of its banks has reached its end of life while others of the banks are little used. Relative use of the memory banks is monitored and, in response to detection of uneven use, have their physical addresses periodically swapped for each other in order to even out their use over the lifetime of the memory.

19. 发明授权

US5822590A dbX: a persistent programming language model 失效
标题翻译： dbX：一种持久的编程语言模型
公开(公告)号：US5822590A
公开(公告)日：1998-10-13
申请号：US785961
申请日：1991-10-31
申请人： Anil Gupta
发明人： Anil Gupta
IPC分类号： G06F9/44
CPC分类号： G06F9/4435
摘要： The dbX persistent programming language model solves the problem of seamlessly providing an unfragmented, persistible, complex object heap space that extends beyond virtual memory to a program in a host programming language X. It does so without rewriting a compiler for X and without operating system or hardware dependencies. It uses a memory pointer as a pointer to a persistible object, with the lvalue of the pointer providing a hook to the OID of the object. The lvalues of pointers to persistible objects, their associated OIDs and other information about persistible objects are maintained in a global data structure. Unresolved pointers to persistible objects point to an unusable area of memory, and dereferencing them triggers object faulting. A keyword and an overloaded allocation operator are used to identify statically and dynamically allocated pieces of memory respectively as persistible. A preprocessor processes occurrences of the keyword and operator, and some operations on pointers to persistible objects in a dbX program and generates X code. Object translation uses a `pointer view of memory` and an `allocation view of memory` to determine the runtime structure of an object graph, and it is resilient to pointer casting and pointing to objects embedded in larger objects.
摘要翻译： dbX持久性编程语言模型解决了无缝地提供未分片的，可持续的，复杂的对象堆空间的问题，该空间将虚拟内存扩展到主机编程语言X中的程序。它不需要重写X的编译器，而不需要操作系统或硬件依赖。它使用内存指针作为可持续对象的指针，指针的左值提供了对象的OID的钩子。指向可持续对象的指针，其关联的OID和关于可持久对象的其他信息的值保持在全局数据结构中。未解决的指向可持续对象的指针指向不可用的内存区域，并且取消引用它们会触发对象故障。一个关键字和一个重载的分配运算符被用来分别识别静态和动态分配的内存块。预处理程序处理关键字和运算符的出现以及对dbX程序中可持久对象的指针的一些操作，并生成X代码。对象转换使用“存储器的指针视图”和“存储器的分配视图”来确定对象图形的运行时结构，并且它对指针转换和指向嵌入在较大对象中的对象是有弹性的。

20. 发明授权

US5471478A Flash EEPROM array data and header file structure 失效
标题翻译：闪存EEPROM阵列数据和头文件结构
公开(公告)号：US5471478A
公开(公告)日：1995-11-28
申请号：US401942
申请日：1995-03-10
申请人： John S. Mangan , Robert D. Norman , Jeffrey Craig , Richard Albert , Anil Gupta , Jeffrey D. Stai , Karl M. J. Lofgren
发明人： John S. Mangan , Robert D. Norman , Jeffrey Craig , Richard Albert , Anil Gupta , Jeffrey D. Stai , Karl M. J. Lofgren
IPC分类号： G06F3/06 , G06F11/10 , G11C16/10 , G11C29/00 , G06F11/00
CPC分类号： G11C29/765 , G06F3/0601 , G11C16/102 , G06F11/1068 , G06F2003/0694
摘要： A file structure employed in a flash electrically erasable and programmable read only memory ("EEPROM") system and aspects of forming and using certain data fields within such a file structure. An array of rows and columns of EEPROM memory cells is divided into blocks of cells that are separately addressable for the purpose of erasing an entire block of cells at the same time. Each block contains several rows of cells with certain columns thereof storing a sector of data, typically 512 bytes of data, and other columns of cells within the same rows being used as spare cells to replace any defective sector data cells and store overhead (header) information about the block and the data sector. Such overhead information includes pointers to locations of any defective sector data cells within the block, whether the block has been mapped out in favor of another block, error correction codes for the sector data and the header information, and other similar types of information.
摘要翻译：在闪存电可擦除和可编程只读存储器（“EEPROM”）系统中采用的文件结构以及在这样的文件结构内形成和使用某些数据字段的方面。 EEPROM存储器单元的行和列的阵列被划分为可单独寻址以便同时擦除整个单元块的单元的单元块。每个块包含几行单元，其中某些列存储数据扇区（通常为512字节的数据），同一行内的其他单元格列用作备用单元以替代任何缺陷扇区数据单元并存储开销（标题）关于块和数据扇区的信息。这种开销信息包括指向块内的任何缺陷扇区数据单元的位置的指针，该块是否被映射到有利于另一个块，扇区数据的纠错码和头部信息以及其他类似类型的信息。

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