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11. 发明授权

US08848194B2 Integrated plasmonic nanocavity sensing device 有权
标题翻译：集成等离子体纳米腔感测装置
公开(公告)号：US08848194B2
公开(公告)日：2014-09-30
申请号：US13639716
申请日：2011-04-06
申请人： Robert Walters , Jurriaan Schmitz , Albert Polman , Ihor Brunets
发明人： Robert Walters , Jurriaan Schmitz , Albert Polman , Ihor Brunets
IPC分类号： G01N21/55 , G01N21/64 , H01L31/12 , B82Y20/00 , G02B6/122 , G01N21/77 , B01L3/00
CPC分类号： G01N21/55 , B01L3/502715 , B01L2300/0654 , B01L2300/0663 , B82Y20/00 , G01N21/554 , G01N21/6454 , G01N21/648 , G01N21/6489 , G01N21/7746 , G01N2021/7776 , G01N2021/7786 , G01N2021/7789 , G02B6/1226 , H01L31/125
摘要： An integrated plasmonic sensing device is described wherein the integrated device comprises: at least one optical source comprising a first conductive layer and a second conductive layer, and a optical active layer between at least part of said first and second conductive layers; at least one nanocavity extending through said first and second conductive layers and said optical active layer, wherein said optical source is configured to generate surface plasmon modes suitable for optically activating one or more resonances in said nanocavity; and, at least one optical detector comprising at least one detection region formed in said substrate in the vicinity of said nanocavity resonator, wherein said optical detector is configured to sense optically activated resonances in said nanocavity.
摘要翻译：描述了集成等离子体激元感测装置，其中集成装置包括：至少一个光源，包括第一导电层和第二导电层，以及在所述第一和第二导电层的至少一部分之间的光学有源层; 至少一个延伸穿过所述第一和第二导电层和所述光学有源层的纳米腔，其中所述光源被配置为产生适于光学激活所述纳米腔中的一个或多个谐振的表面等离子体模式; 以及至少一个光学检测器，其包括在所述纳米腔谐振器附近形成在所述衬底中的至少一个检测区域，其中所述光学检测器被配置为感测所述纳米腔中的光学激活的共振。

12. 发明申请

US20060049453A1 Vertical insulated gate transistor and manufacturing method 有权
标题翻译：垂直绝缘栅晶体管及其制造方法
公开(公告)号：US20060049453A1
公开(公告)日：2006-03-09
申请号：US10538216
申请日：2003-12-08
申请人： Jurriaan Schmitz , Raymond Hueting , Erwin Hijzen , Andreas Montree , Michael In't Zandt , Gerrit Koops
发明人： Jurriaan Schmitz , Raymond Hueting , Erwin Hijzen , Andreas Montree , Michael In't Zandt , Gerrit Koops
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/42368 , H01L29/66666 , H01L29/7827
摘要： A vertical insulated gate transistor is manufactured by providing a trench (26) extending through a source layer (8) and a channel layer (6) towards a drain layer (2). A spacer etch is used to form gate portions (20) along the trench side walls, a dielectric material (30) is filled into the trench between the sidewalls gate portions (20), and a gate electrical connection layer (30) is formed at the top of the trench electrically connecting the gate portions (20) across the trench.
摘要翻译：通过向漏极层（2）提供延伸穿过源极层（8）和沟道层（6）的沟槽（26）来制造垂直绝缘栅极晶体管。使用间隔物蚀刻沿着沟槽侧壁形成栅极部分（20），电介质材料（30）被填充到侧壁栅极部分（20）之间的沟槽中，并且栅极电连接层（30）形成在所述沟槽的顶部电连接所述栅极部分（20）穿过所述沟槽。

13. 发明授权

US06743682B2 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06743682B2
公开(公告)日：2004-06-01
申请号：US10100595
申请日：2002-03-18
申请人： Pierre Hermanus Woerlee , Jurriaan Schmitz , Andreas Hubertus Montree
发明人： Pierre Hermanus Woerlee , Jurriaan Schmitz , Andreas Hubertus Montree
IPC分类号： H01L21336
CPC分类号： H01L21/76895 , H01L29/4966 , H01L29/66537 , H01L29/66545
摘要： In a method of manufacturing a semiconductor device comprising a semiconductor body 1 which is provided at a surface 2 with a transistor comprising a gate structure 21, a patterned layer 10 is applied defining the area of the gate structure 21. Subsequently, a dielectric layer 18 is applied in such a way, that the thickness of the dielectric layer 18 next to the patterned layer 10 is substantially equally large or larger than the height of the patterned layer 10, which dielectric layer 18 is removed over part of its thickness until the patterned layer 10 is exposed. Then, the patterned layer 10 is subjected to a material removing treatment, thereby forming a recess 19 in the dielectric layer 18, and a contact window 28,29 is provided in the dielectric layer. A conductive layer 30 is applied filling the recess 19 and the contact window 28,29, which conductive layer 30 is subsequently shaped into the gate structure 21 and a contact structure 26,27 establishing an electrical contact with the surface 2 of the semiconductor body 1.
摘要翻译：在制造半导体器件的方法中，该半导体器件包括半导体本体1，半导体本体1在表面2处设置有包括栅极结构21的晶体管，施加限定栅极结构21的区域的图案化层10.随后，介电层18 以这样的方式施加，图案化层10旁边的电介质层18的厚度基本上等于或大于图案化层10的高度，该图案层10的厚度在其厚度的一部分上被去除，直到图案化层层10暴露。然后，对图案层10进行材料去除处理，从而在电介质层18中形成凹部19，并且在电介质层中设置接触窗28,29。填充导电层30，其填充凹部19和接触窗28,29，该导电层30随后成形为栅极结构21，以及与半导体主体1的表面2建立电接触的接触结构26,27 。

14. 发明申请

US20060030118A1 Method of manufacturing a semiconductor device with field isolation regions consisting of grooves filled with isolation material 有权
标题翻译：制造具有由隔离材料填充的槽组成的场隔离区域的半导体器件的方法
公开(公告)号：US20060030118A1
公开(公告)日：2006-02-09
申请号：US10529962
申请日：2003-09-30
申请人： Jurriaan Schmitz , Clarie Ravit , Rita Rooyachkers
发明人： Jurriaan Schmitz , Clarie Ravit , Rita Rooyachkers
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A method of manufacturing a semiconductor device comprising a silicon body (1) having a surface (4) provided with field isolation regions (2) enclosing active regions (3). In this method, on the surface of the silicon body there is formed an auxiliary layer (5) of a material on which, during an oxidation treatment, a thicker layer of silicon oxide is formed than on the silicon of the silicon body. Here, an auxiliary layer comprising silicon and germanium is formed on the surface, said auxiliary layer preferably being a layer of SixGe1-x-yCy, where 0.70
摘要翻译：一种制造半导体器件的方法，包括具有表面（4）的硅体（1），所述硅体（1）设置有包围有源区（3）的场隔离区（2）。在该方法中，在硅体的表面上形成辅助层（5），在氧化处理期间形成比硅体的硅上形成更厚的氧化硅层。这里，在表面上形成包括硅和锗的辅助层，所述辅助层优选为SixGe1-x-yCy层，其中0.70

15. 发明授权

US06969645B2 Method of manufacturing a semiconductor device comprising a non-volatile memory with memory cells 失效
标题翻译：包括具有存储单元的非易失性存储器的半导体器件的制造方法
公开(公告)号：US06969645B2
公开(公告)日：2005-11-29
申请号：US10482185
申请日：2002-07-03
申请人： Jurriaan Schmitz , Franciscus Petrus Widdershoven , Michiel Slotboom
发明人： Jurriaan Schmitz , Franciscus Petrus Widdershoven , Michiel Slotboom
IPC分类号： H01L21/8247 , H01L21/28 , H01L21/336 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , H01L21/8238
CPC分类号： H01L21/28273 , H01L29/42328
摘要： A method of manufacturing a semiconductor device comprising a non-volatile memory with memory cells (Mij) including a select transistor (T1) with a select gate (1) and including a memory transistor (T2) with a floating gate (2) and a control gate (3). In a semiconductor body (10), active semiconductor regions are formed which are mutually insulated by field oxide regions (12). Next, the surface (11) is provided with a gate oxide layer (14) and a first layer of a conductive material wherein the select gate (1) is etched. Subsequently, the walls of the select gate extending perpendicularly to the surface are provided with an isolating material (17). The gate oxide next to the select gate is replaced by a layer of tunnel oxide (18). Next, a second layer of a conductive material (21), an interlayer dielectric (25) and a third layer of a conductive material (26) are deposited. The control gate (3) extending above and next to the select gate is formed in the third layer. Using the control gate as a mask, the floating gate (2) is subsequently etched in the second layer of conductive material. In this method, the second layer is deposited in a larger thickness than the select gate, after which this layer is planarized prior to the deposition of the interlayer dielectric and the third layer of conductive material. In this manner, a compact memory cell can be manufactured.
摘要翻译：一种制造包括非易失性存储器的半导体器件的方法，所述非易失性存储器具有包括具有选择栅极（1）并且包括具有浮置栅极（2）的存储晶体管（T 2）的选择晶体管（T 1）的存储器单元（Mij）和控制门（3）。在半导体本体（10）中，形成由场氧化物区域（12）相互绝缘的有源半导体区域。接下来，表面（11）设置有栅极氧化物层（14）和其中蚀刻选择栅极（1）的导电材料的第一层。随后，垂直于表面延伸的选择栅的壁设置有隔离材料（17）。选择栅极旁边的栅极氧化层被隧道氧化物层（18）代替。接下来，沉积第二层导电材料（21），层间电介质（25）和第三层导电材料（26）。在第三层中形成在选择栅极上方和下方延伸的控制栅极（3）。使用控制栅极作为掩模，随后在第二层导电材料中蚀刻浮栅（2）。在该方法中，第二层被沉积成比选择栅极更大的厚度，然后在沉积层间电介质和第三层导电材料之前将该层平坦化。以这种方式，可以制造紧凑的存储单元。

16. 发明授权

US06472706B2 Semiconductor device 有权
公开(公告)号：US06472706B2
公开(公告)日：2002-10-29
申请号：US09902920
申请日：2001-07-11
申请人： Franciscus Petrus Widdershoven , Jurriaan Schmitz
发明人： Franciscus Petrus Widdershoven , Jurriaan Schmitz
IPC分类号： H01L2972
CPC分类号： H01L27/11568 , H01L29/792
摘要： A semiconductor device comprising a non-volatile memory cell, for storing at least one bit, in a semiconductor substrate (1) having, in the substrate, a source region (6), a drain region (7) and a channel region (10) between the source (6) and drain (7) regions, and having, on top of the substrate, a floating gate (9) separated from the channel region (10) by a floating gate insulating layer, a select gate (11) adjacent to the floating gate and separated from the channel region by a select gate insulating layer (8), and a control gate (5) separated from the floating gate (9) by a control gate insulating layer, the floating gate being a non-conducting charge trapping dielectric layer (9).

17. 发明申请

US20130148126A1 INTEGRATED PLASMONIC NANOCAVITY SENSING DEVICE 有权
标题翻译：集成的等离子体纳米传感器件
公开(公告)号：US20130148126A1
公开(公告)日：2013-06-13
申请号：US13639716
申请日：2011-04-06
申请人： Robert Walters , Jurriaan Schmitz , Albert Polman , Ihor Brunets
发明人： Robert Walters , Jurriaan Schmitz , Albert Polman , Ihor Brunets
IPC分类号： G01N21/55
CPC分类号： G01N21/55 , B01L3/502715 , B01L2300/0654 , B01L2300/0663 , B82Y20/00 , G01N21/554 , G01N21/6454 , G01N21/648 , G01N21/6489 , G01N21/7746 , G01N2021/7776 , G01N2021/7786 , G01N2021/7789 , G02B6/1226 , H01L31/125
摘要： An integrated plasmonic sensing device is described wherein the integrated device comprises: at least one optical source comprising a first conductive layer and a second conductive layer, and a optical active layer between at least part of said first and second conductive layers; at least one nanocavity extending through said first and second conductive layers and said optical active layer, wherein said optical source is configured to generate surface plasmon modes suitable for optically activating one or more resonances in said nanocavity; and, at least one optical detector comprising at least one detection region formed in said substrate in the vicinity of said nanocavity resonator, wherein said optical detector is configured to sense optically activated resonances in said nanocavity.
摘要翻译：描述了集成等离子体激元感测装置，其中集成装置包括：至少一个光源，包括第一导电层和第二导电层，以及在所述第一和第二导电层的至少一部分之间的光学有源层; 至少一个延伸穿过所述第一和第二导电层和所述光学有源层的纳米腔，其中所述光源被配置为产生适于光学激活所述纳米腔中的一个或多个谐振的表面等离子体模式; 以及至少一个光学检测器，其包括在所述纳米腔谐振器附近形成在所述衬底中的至少一个检测区域，其中所述光学检测器被配置为感测所述纳米腔中的光学激活的共振。

18. 发明授权

US07157349B2 Method of manufacturing a semiconductor device with field isolation regions consisting of grooves filled with isolation material 有权
标题翻译：制造具有由隔离材料填充的槽组成的场隔离区域的半导体器件的方法
公开(公告)号：US07157349B2
公开(公告)日：2007-01-02
申请号：US10529962
申请日：2003-09-30
申请人： Jurriaan Schmitz , Claire Ravit , Rita Victoire Theodosie Rooyackers
发明人： Jurriaan Schmitz , Claire Ravit , Rita Victoire Theodosie Rooyackers
IPC分类号： H01L21/76
CPC分类号： H01L21/76224
摘要： A method of manufacturing a semiconductor device comprising a silicon body (1) having a surface (4) provided with field isolation regions (2) enclosing active regions (3). In this method, on the surface of the silicon body there is formed an auxiliary layer (5) of a material on which, during an oxidation treatment, a thicker layer of silicon oxide is formed than on the silicon of the silicon body. Here, an auxiliary layer comprising silicon and germanium is formed on the surface, said auxiliary layer preferably being a layer of SixGe1−x−yCy, where 0.70
摘要翻译：一种制造半导体器件的方法，包括具有表面（4）的硅体（1），所述硅体（1）设置有包围有源区（3）的场隔离区（2）。在该方法中，在硅体的表面上形成辅助层（5），在氧化处理期间形成比硅体的硅上形成更厚的氧化硅层。这里，在表面上形成包括硅和锗的辅助层，所述辅助层优选为SixGe1-x-yCy层，其中0.70

19. 发明授权

US06656760B2 Solid state imaging sensor in a submicron technology and method of manufacturing and use of a solid state imaging sensor 失效
标题翻译：固态成像传感器在亚微米技术和制造和使用固态成像传感器的方法中
公开(公告)号：US06656760B2
公开(公告)日：2003-12-02
申请号：US09803336
申请日：2001-03-09
申请人： Jurriaan Schmitz , Edwin Roks , Daniel Wilhelmus Elisabeth Verbugt
发明人： Jurriaan Schmitz , Edwin Roks , Daniel Wilhelmus Elisabeth Verbugt
IPC分类号： H01L2100
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14643
摘要： A detector and a camera system for electromagnetic radiation being integrated in a solid state substrate are disclosed. Said substrate comprises a first region of a first conductivity and a second region of a second conductivity, said first region being adjacent to said second region, and said first and second region forming a detection junction, at least part of said junction being substantially orthogonal with respect to the plane of the surface of the substrate above said detection junction. The camera system comprises a configuration of pixels in an imaging sensor being integrated in a solid state substrate, essentially each of the pixels comprising a region of a first conductivity type being at least partly surrounded by a region of a second conductivity type, thereby forming a junction region, and wherein the region of the first conductivity type includes at least one contact area. The camera system further comprises means for collecting charge carriers being generated by the radiation impinging on said substrate at least in said region of said first conductivity type and in said junction region, in said contact area.
摘要翻译：公开了一种用于电磁辐射的检测器和照相机系统集成在固态衬底中。所述衬底包括第一导电性的第一区域和第二导电性的第二区域，所述第一区域与所述第二区域相邻，所述第一和第二区域形成检测结，所述接合区的至少一部分基本上与相对于所述检测结上方的衬底的表面的平面。相机系统包括集成在固态基板中的成像传感器中的像素的配置，基本上每个像素包括第一导电类型的区域，至少部分地被第二导电类型的区域包围，从而形成并且其中所述第一导电类型的区域包括至少一个接触区域。照相机系统还包括用于收集至少在所述第一导电类型的所述区域中和在所述接合区域中的所述接合区域中的照射在所述衬底上的辐射产生的电荷载体的装置。

20. 发明授权

US06406963B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06406963B2
公开(公告)日：2002-06-18
申请号：US09738917
申请日：2000-12-14
申请人： Pierre Hermanus Woerlee , Jurriaan Schmitz , Andreas Hubertus Montree
发明人： Pierre Hermanus Woerlee , Jurriaan Schmitz , Andreas Hubertus Montree
IPC分类号： H01L21336
CPC分类号： H01L21/76895 , H01L29/4966 , H01L29/66537 , H01L29/66545
摘要： In a method of manufacturing a semiconductor device comprising a semiconductor body 1 which is provided at a surface 2 with a transistor comprising a gate structure 21, a patterned layer 10 is applied defining the area of the gate structure 21. Subsequently, a dielectric layer 18 is applied in such a way, that the thickness of the dielectric layer 18 next to the patterned layer 10 is substantially equally large or larger than the height of the patterned layer 10, which dielectric layer 18 is removed over part of its thickness until the patterned layer 10 is exposed. Then, the patterned layer 10 is subjected to a material removing treatment, thereby forming a recess 19 in the dielectric layer 18, and a contact window 28,29 is provided in the dielectric layer. A conductive layer 30 is applied filling the recess 19 and the contact window 28,29, which conductive layer 30 is subsequently shaped into the gate structure 21 and a contact structure 26,27 establishing an electrical contact with the surface 2 of the semiconductor body 1.
摘要翻译：在制造半导体器件的方法中，该半导体器件包括半导体本体1，半导体本体1在表面2处设置有包括栅极结构21的晶体管，施加限定栅极结构21的区域的图案化层10.随后，介电层18 以这样的方式施加，图案化层10旁边的电介质层18的厚度基本上等于或大于图案化层10的高度，该图案层10的厚度在其厚度的一部分上被去除，直到图案化层层10暴露。然后，对图案层10进行材料去除处理，从而在电介质层18中形成凹部19，并且在电介质层中设置接触窗28,29。填充导电层30，其填充凹部19和接触窗28,29，该导电层30随后成形为栅极结构21，以及与半导体主体1的表面2建立电接触的接触结构26,27 。

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